TWI674571B - Display device and compensation capacitor operating method - Google Patents

Abstract

A display device has a display area and a plurality of non-display areas. The display device includes a substrate, a plurality of pixel units, a plurality of first gate lines, a plurality of second gate lines, a plurality of first data lines, a plurality of second data lines, and a plurality of capacitor compensation structures. The pixel unit matrix is arranged on the substrate. The first gate line and the second gate line are arranged in a row on the substrate. The first data line and the second data line are arranged in a row on the substrate. The capacitor compensation structure matrix is arranged in the non-display area. The capacitance compensation structure includes a part of the second gate line, an insulating layer, a semiconductor layer, and a part of the second data line. The insulating layer is disposed on a part of the second gate line. The semiconductor layer is disposed on the insulating layer. Part of the second data line is disposed on the semiconductor layer. Part of the second data line and part of the second gate line are located on opposite sides of the semiconductor layer, respectively.

Description

Display device and operation method of compensation capacitor

The present invention relates to a display device, and more particularly to a display device with a capacitance compensation structure and an operation method for compensating capacitance.

At present, in an electronic product (for example, a mobile phone) having a liquid crystal display device, a notch is often provided in the upper center of the liquid crystal display device to place a camera or a sensor; even its liquid crystal display device The four corners are rounded to meet consumer demand for the appearance of electronic products. However, compared to other areas of the liquid crystal display device, the number of pixels corresponding to the gate lines at the recesses and fillets is relatively small, so that the gate load of the gate lines at the recesses and fillets is smaller than The gate loads of the gate lines in other regions are different, which causes the LCD display device to have uneven display brightness and discontinuous pictures.

The invention provides a display device including a capacitance compensation structure, which can have a more uniform display brightness and can avoid the problem of discontinuous pictures.

The invention provides an operation method for compensating capacitance. By using the display device with a capacitance compensation structure, the problems of uneven display brightness and discontinuous pictures can be improved.

A display device of the present invention has a display area and a plurality of non-display areas. The display device includes a substrate, a plurality of pixel units, a plurality of first gate lines, a plurality of second gate lines, a plurality of first data lines, a plurality of second data lines, and a plurality of capacitor compensation structures. The pixel unit matrix is arranged on the substrate and is located in the display area. The first gate line and the second gate line are arranged in a row on the substrate and are located in the display area. The first data line and the second data line are arranged in a row on the substrate and are located in the display area. The capacitor compensation structure matrix is arranged in the non-display area. The capacitance compensation structure includes a part of the second gate line, an insulating layer, a semiconductor layer, and a part of the second data line. The insulating layer is disposed on a part of the second gate line. The semiconductor layer is disposed on the insulating layer. Part of the second data line is disposed on the semiconductor layer. Part of the second data line and part of the second gate line are located on opposite sides of the semiconductor layer, respectively.

A method for operating a compensation capacitor of the present invention utilizes the display device described above, and the method includes the following steps. When the gate load of the second gate line is larger than that of the first gate line, the potential of the second data line in the capacitance compensation structure is increased to reduce the compensation capacitance and the second gate line. Total capacitance. When the gate load of the second gate line is smaller than the gate load of the first gate line, the potential of the second data line in the capacitance compensation structure is reduced to increase the compensation capacitance and the Total capacitance. When the potential fall time of the second gate line is slower than that of the first gate line, the potential of the second data line in the capacitance compensation structure is increased to reduce the compensation capacitance and the second gate line. Total capacitance. When the electricity of the second gate line When the bit fall time is faster than the potential fall time of the first gate line, the potential of the second data line in the capacitance compensation structure is decreased to increase the total capacitance of the compensation capacitor and the second gate line.

The display device in one of the above embodiments has a capacitance compensation structure, can have a more uniform display brightness, and can avoid the problem of discontinuous pictures.

In the method for operating the compensation capacitor in one of the above embodiments, the problems of uneven display brightness and discontinuous pictures can be improved.

Based on the above, the display device of this embodiment has a plurality of capacitance compensation structures arranged in the non-display area. The capacitance compensation structure includes a part of the second gate line, an insulating layer, a semiconductor layer, and a part of the second data line. Wherein, the insulating layer is disposed on part of the second gate line, the semiconductor layer is disposed on the insulating layer, part of the second data line is disposed on the semiconductor layer, and part of the second data line and part of the second gate line are respectively Located on opposite sides of the semiconductor layer. With this design, the above display device can have a more uniform display brightness and can avoid the problem of discontinuous pictures.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100, 100a, 100b‧‧‧ display device

101‧‧‧display area

102a, 102b, 102c, 102d, 102e ‧‧‧ non-display area

110‧‧‧ substrate

120‧‧‧ Pixel Unit

130‧‧‧first gate line

140, G1, G2, G3, G4, G5, G6, G7, G8‧‧‧Second gate line

150‧‧‧The first data line

160‧‧‧Second data line

170‧‧‧Capacitance compensation structure

172‧‧‧Insulation

174‧‧‧Semiconductor layer

180‧‧‧ flat outline

182‧‧‧ rounded corners

184‧‧‧concave hole

190‧‧‧Drive element

200‧‧‧Speed Camera

210‧‧‧ Computer

220‧‧‧light fixture

310, 310a‧‧‧ Low potential

320, 320a‧‧‧ wave detection element

330, 330a‧‧‧High potential

A‧‧‧Area

G‧‧‧Gate

R‧‧‧ Cross Overlap

S‧‧‧Source

T1, T2, T3, T4, T5, T6, T7, T8, T (A), T (B) ‧‧‧Transistors

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention.

FIG. 1B is an enlarged view of a region A in FIG. 1A.

FIG. 1C is an enlarged view of the cross-overlap region R in FIG. 1B.

Fig. 1D is a schematic cross-sectional view taken along the line I-I 'in Fig. 1C.

FIG. 2A is a schematic diagram illustrating an operation method of a compensation capacitor according to an embodiment of the present invention.

2B and 2C illustrate applications of the method for operating the compensation capacitor of FIG. 2A.

3A is a schematic diagram illustrating an operation method of a compensation capacitor according to another embodiment of the present invention.

FIG. 3B illustrates an application of the operation method of the compensation capacitor of FIG. 3A.

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. FIG. 1B is an enlarged view of a region A in FIG. 1A. FIG. 1C is an enlarged view of the cross-overlap region R in FIG. 1B. Fig. 1D is a schematic cross-sectional view taken along the line I-I 'in Fig. 1C.

Please refer to FIGS. 1A and 1B at the same time. In this embodiment, the display device 100 includes a display area 101 and a plurality of non-display areas 102a, 102b, 102c, 102d, and 102e. The display device 100 includes a substrate 110, a plurality of pixel units 120, a plurality of first gate lines 130, a plurality of second gate lines 140, a plurality of first data lines 150, a plurality of second data lines 160, and a plurality of Capacitance compensation structure 170. The pixel units 120 are arranged in a matrix on the substrate 110 and are located in the display area 101. The first gate line 130 and the second gate line 140 are arranged in a row on the substrate 110 and are located in the display area 101. The first data line 150 and the second data line 160 are arranged in a row on the substrate 110 and are located in the display area 101. capacitance The compensation structures 170 are arranged in a matrix in the non-display areas 102a, 102b, 102c, 102d, 102e (a plurality of capacitance compensation structures 170 in the non-display area 102a are schematically shown in FIG. 1B).

1C and FIG. 1D at the same time, the capacitor compensation structure 170 includes a portion of the second gate line 140, an insulating layer 172, a semiconductor layer 174, and a portion of the second data line 160. The insulating layer 172 is disposed on a portion of the second gate line 140. The semiconductor layer 174 is disposed on the insulating layer 172. A portion of the second data line 160 is disposed on the semiconductor layer 174. Part of the second data line 160 and part of the second gate line 140 are located on opposite sides of the semiconductor layer 174, respectively. In this embodiment, the potential difference (VGS = gate potential-source) between the second gate line 140 (gate G) and the second data line 160 (source S) of the capacitor compensation structure 170 can be changed. Potential) to determine the semiconductor layer 174 of the capacitance compensation structure 170 as a conductor or an insulator, and then change the size of the compensation capacitance of the capacitance compensation structure 170. Here, the material of the semiconductor layer 174 includes single crystal silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials.

In detail, please refer to FIG. 1A again. In this embodiment, the planar profile 180 of the display device 100 has rounded corners 182 or recessed holes 184. The non-display area 102a is located outside the recessed hole 184 of the planar outline 180, and the non-display area 102b, 102c, 102d, 102e is located outside the rounded corner 182 of the planar outline 180.

In addition, in this embodiment, the first gate line 130, the second gate line 140, the first data line 150, and the second data line 160 are electrically connected to the pixel unit 120, respectively. Among them, since the second gate line 140 extends into the non-display areas 102a, 102b, 102c, 102d, and 102e outside the rounded corners 182 or the recessed holes 184, the second gate line 140 The number of pixel units 120 electrically connected to 140 is smaller than the number of pixel units 120 electrically connected to the first gate line 130.

Specifically, in this embodiment, the second gate line 140 and the second data line 160 may extend into the non-display areas 102a, 102b, 102c, 102d, and 102e, respectively, and in the non-display areas 102a, 102b, and 102c. , 102d, and 102e overlap each other, thus forming a plurality of overlapping regions R, as shown in FIG. 1B. The capacitance compensation structure 170 is located in the cross-overlap region R. In other words, the plurality of overlapping regions R formed by the second gate line 140 and the second data line 160 crossing each other have a capacitance compensation structure 170.

In short, the display device 100 of this embodiment has a plurality of capacitance compensation structures 170 arranged in the non-display areas 102a, 102b, 102c, 102d, and 102e. The capacitance compensation structure 170 includes a portion of the second gate line 140, an insulation layer 172, a semiconductor layer 174, and a portion of the second data line 160. Among them, the insulating layer 172 is disposed on part of the second gate line 140, the semiconductor layer 174 is disposed on the insulating layer 172, part of the second data line 160 is disposed on the semiconductor layer 174, and part of the second data line 160 and Part of the second gate lines 140 are located on opposite sides of the semiconductor layer 174, respectively. With this design, the display device 100 of this embodiment can have a more uniform display brightness and can avoid the problem of discontinuous pictures.

In the following, other embodiments are listed as illustrations, and how to use a display device with a capacitance compensation structure to perform an operation method for compensating capacitance. It must be noted here that the following embodiments use the component numbers and parts of the foregoing embodiments, in which the same reference numerals are used to indicate the same or similar components, and the same components are omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

FIG. 2A is a schematic diagram illustrating an operation method of a compensation capacitor according to an embodiment of the present invention. Referring to FIG. 2A, the method for operating the compensation capacitor in this embodiment includes a display device 100a, a high-speed camera 200, a computer 210, a lighting fixture 220, and the like. The computer 210 is electrically connected to the high-speed camera 200 and the lighting fixture 220. The high-speed camera 200 can capture the flicker amount of each pixel unit 120 on the display device 100 a and transmit the shooting result to a computer 210. The lighting fixture 220 can also be electrically connected to the driving element 190 on the display device 100a to drive the display device 100a.

In this embodiment, the display device 100a is the same as the display device 100 of FIG. 1A. Therefore, when the display device 100a is turned on, the flicker amount of the pixel unit 120 on the second gate line 140 on the display device 100a It may be larger or smaller than the flicker amount of the pixel unit 120 on the first gate line 130, thus causing the display device 100a to have problems of uneven display brightness and discontinuous pictures. Therefore, for such a problem, the method for operating the compensation capacitor of this embodiment can be used to adjust the capacitance compensation structure 170 corresponding to one second gate line 140 as follows.

When the high-speed camera 200 detects that the amount of flicker of the pixel unit 120 on the second gate line 140 is greater than the amount of flicker of the pixel unit 120 on the first gate line 130, and the gate load of the second gate line 140 is Compared with the case where the gate load of the first gate line 130 is large, the potential of the second data line 160 in the capacitor compensation structure 170 can be increased by increasing the potential of the second data line 160 before the potential of the second gate line 140 drops, for example, by 2V. ~ 3V, for example, to change the potential of the second data line 160 from a negative potential to a positive potential to reduce the capacitance The VGS of the compensation structure 170, the compensation capacitance of the reduced capacitance compensation structure 170, and the total capacitance of the second gate line 140 are reduced. Specifically, since each of the second gate lines 140 corresponds to a plurality of capacitance compensation structures 170 and a plurality of second data lines 160, the capacitance compensation structure 170 on each of the second gate lines 140 can be targeted. The potential of the second data line 160 is adjusted to increase the number of positive potentials of the second data line 160 of the compensation capacitor, so that the compensation capacitance of the adjusted capacitance compensation structure 170 is reduced and the second gate line 140 is adjusted. The total capacitance is reduced, so that the flicker amount of the pixel unit 120 on the adjusted second gate line 140 is reduced, as shown in FIG. 2B.

Conversely, when the high-speed camera 200 detects that the amount of flicker of the pixel unit 120 on the second gate line 140 is greater than the amount of flicker of the pixel unit 120 on the first gate line 130 and the gate of the second gate line 140 Compared with the gate load of the first gate line 130 when the gate load is small, the capacitance of the second data line 160 in the capacitance compensation structure 170 can be increased to reduce the capacitance before the potential of the second gate line 140 drops. The VGS of the compensation structure 170, the compensation capacitance of the capacitance compensation structure 170 is increased, and the total capacitance of the second gate line 140 is increased. In other words, the number of the second data lines 160 of the compensation capacitor to be a positive potential can be reduced, so that the compensation capacitance of the adjusted capacitance compensation structure 170 is increased and the total capacitance of the second gate line 140 is increased, so that the adjusted The amount of flicker of the pixel unit 120 on the second gate line 140 is reduced, as shown in FIG. 2C.

Next, after obtaining the adjustment conditions of the potential of the second data line 160 corresponding to the two capacitor compensation structures 170 of the one second gate line 140, these adjustment conditions can be programmed into the driving element 190 so that The display device 100a adjusted by the operation method of the compensation capacitor in this embodiment may have a more uniform display brightness. It can avoid the problem of discontinuous pictures.

FIG. 3A illustrates an operation method of a compensation capacitor according to another embodiment of the present invention. Referring to FIG. 3A, in the method for operating the compensation capacitor in this embodiment, the display device 100b may include a plurality of second gate lines G1 to G8, and the second gate lines G1 to G8 are sequentially arranged in the display device 100b. . Next, a plurality of transistors T1, T3, T5, and T7 are arranged in parallel, so that the second gate lines G1, G3, G5, and G7 are electrically connected to corresponding gates of one transistor T1, T3, T5, and T7, respectively. And one end of the transistors T1, T3, T5, and T7 is connected to the low potential 310, and the other ends (outputs) of the transistors T1, T3, T5, and T7 are connected to the wave shape detection element 320 and the other transistor T (A). At this time, one end of the transistor T (A) is connected to the high potential 330 and Vgs of the transistor T (A) = 0.

In a similar manner, a plurality of transistors T2, T4, T6, and T8 are provided in parallel, so that the second gate lines G2, G4, G6, and G8 are electrically connected to the corresponding transistors T2, T4, T6, and T8, respectively. And connect one end of the transistors T2, T4, T6, and T8 to low potential 310a, and connect the other end (output) of the transistors T2, T4, T6, and T8 to the wave shape detection element 320a and the other Transistor T (B). At this time, one end of the transistor T (B) is connected to the high potential 330a and Vgs of the transistor T (B) = 0.

Therefore, the signal of a second gate line G1 ~ G8 can generate an amplified signal through the other end (output end) of the transistors T1 ~ T8 which are electrically connected to it, and then the wave shape detection element 320, 320a to show its waveform, as shown in Figure 3B.

Please refer to FIG. 3B. The solid line in the figure is the ideal potential change (it can be considered as the potential change of the first gate line), and the dotted line is the actual potential of the second gate line G1, G3, G5. Variety. As can be seen from FIG. 3B, since the fall time of the potential of the second gate line G1, G3 is slower than the fall time of the ideal potential (the potential of the first gate line 130), it can be Before the two gate lines G1 and G3 are turned off, the potential of the second data line 160 in the capacitance compensation structure 170 is increased (or the number of the second data line 160 increased by the compensation capacitance is positive and the number of The two data lines 160 are the number of negative potentials) to reduce the compensation capacitance of the capacitance compensation structure 170 and the total capacitance of the second gate lines G1 and G3.

In addition, since the fall time of the potential of the second gate line G5 is faster than the fall time of the ideal potential (the potential of the first gate line 130), the second gate G5 can be used in the next frame. Before closing, the potential of the second data line 160 in the capacitance compensation structure 170 is reduced (or the number of the second data line 160 that decreases the compensation capacitance is positive and the number of the second data line 160 that increases the compensation capacitance is negative To increase the compensation capacitance of the capacitance compensation structure 170 and the total capacitance of the second gate line G5.

In summary, in the display device and the method for operating the compensation capacitor in this embodiment, since the non-display area of the display device has a plurality of capacitance compensation structures, and the capacitance compensation structure includes a part of the second gate line and the insulation layer , Semiconductor layer and some second data lines. Therefore, when the gate load of the second gate line is larger (or smaller) than that of the first gate line, the potential of the second data line in the structure can be compensated by increasing (or decreasing) the capacitance. To reduce (or increase) the total capacitance of the compensation capacitor and the second gate line. When the potential fall time of the second gate line is slower (or faster) than the potential fall time of the first gate line, the potential of the second data line in the capacitor compensation structure can be increased (or decreased) by Reduce (or increase) the total capacitance of the compensation capacitor and the second gate line. With this design, The display device of this embodiment can have a more uniform display brightness and can avoid the problem of discontinuous pictures, and can use the operation method of the compensation capacitor of this embodiment to improve the problems of uneven display brightness and discontinuous pictures.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (7)

A display device has a display area and a plurality of non-display areas. The display device includes: a substrate; a plurality of pixel units arranged in a matrix on the substrate and located in the display area; a plurality of first gate lines and a plurality of A plurality of second gate lines arranged in a row on the substrate and located in the display area; a plurality of first data lines and a plurality of second data lines arranged in a row on the substrate and located in the display area; a plurality of A capacitor compensation structure is arranged in a matrix in the non-display areas, and each of the capacitor compensation structures includes: a part of the second gate line; an insulating layer disposed on part of the second gate line; a semiconductor layer configured On the insulating layer; and part of the second data line disposed on the semiconductor layer, part of the second data line and part of the second gate line are located on opposite sides of the semiconductor layer, respectively. The display device according to item 1 of the scope of patent application, wherein a flat outline of the display device has a rounded corner or a recessed hole, and the non-display areas are located outside the rounded corner or the recessed hole of the flat outline. The display device according to item 1 of the scope of patent application, wherein the first gate lines, the second gate lines, the first data lines, and the second data lines are electrically connected to the respective ones. The pixel units, wherein the number of the pixel units electrically connected by the second gate lines are smaller than the number of the pixel units electrically connected by the first gate lines. The display device according to item 1 of the scope of patent application, wherein the second gate lines and the second data lines respectively extend into the non-display areas and overlap each other, and have a plurality of overlapping areas. The display device according to item 4 of the scope of patent application, wherein the capacitor compensation structures are located in the overlapping areas. The display device according to item 1 of the patent application scope, wherein the semiconductor layer includes single crystal silicon, polycrystalline silicon, or amorphous silicon. An operation method for compensating capacitors uses the display device described in item 1 of the scope of patent application, and the operation method includes: when a gate load of the second gate lines is compared with that of the first gate lines; When the gate load is large, the potential of the second data lines in the capacitance compensation structures is increased to reduce the total capacitance of the compensation capacitance and the second gate lines; when the second gate lines are Compared with the gate load of the first gate lines, when the gate load of the gate is smaller, the potential of the second data lines in the capacitance compensation structures is reduced to increase the compensation capacitance and the second gates. The total capacitance of the polar lines; when the potential fall times of the second gate lines are slower than the potential fall times of the first gate lines, the second data in the structure is compensated by increasing the capacitances To reduce the total capacitance of the second gate lines and the total capacitance of the second gate lines; when the potential drop times of the second gate lines are faster than the potential drop times of the first gate lines, By reducing the second data lines in the capacitor compensation structures The potential to increase the total capacitance of the compensation capacitor, and the plurality of second gate lines.