TWI669918B - Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same - Google Patents

Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same Download PDF

Info

Publication number
TWI669918B
TWI669918B TW106137620A TW106137620A TWI669918B TW I669918 B TWI669918 B TW I669918B TW 106137620 A TW106137620 A TW 106137620A TW 106137620 A TW106137620 A TW 106137620A TW I669918 B TWI669918 B TW I669918B
Authority
TW
Taiwan
Prior art keywords
signal
common
mode voltage
input terminal
terminal
Prior art date
Application number
TW106137620A
Other languages
Chinese (zh)
Other versions
TW201919349A (en
Inventor
巫朝發
Original Assignee
北京集創北方科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京集創北方科技股份有限公司 filed Critical 北京集創北方科技股份有限公司
Priority to TW106137620A priority Critical patent/TWI669918B/en
Publication of TW201919349A publication Critical patent/TW201919349A/en
Application granted granted Critical
Publication of TWI669918B publication Critical patent/TWI669918B/en

Links

Landscapes

  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

一種具有自適應發送端等化器調節功能的傳輸電路,其在一差動傳輸通道的一發送端及一接收端分別具有一前饋等化器及一接收等化器,其特徵在於,具有:一自適應補償調節模組,用以對該接收等化器之一輸出電壓信號進行一偽誤碼率運算以產生一共模電壓控制信號;一共模電壓產生模組,用以依該共模電壓控制信號產生一共模電壓,並將該共模電壓耦接至該差動傳輸通道;以及一共模電壓檢測模組,用以依該差動傳輸通道之一傳輸共模電壓與一參考電壓的一比較結果產生一回饋信號,並將該回饋信號傳送至該前饋等化器以調整該前饋等化器之一增益頻率響應分布或一補償電壓。A transmission circuit with an adaptive equalizer adjustment function at a transmitting end, which has a feedforward equalizer and a receive equalizer at a transmitting end and a receiving end of a differential transmission channel, respectively. : An adaptive compensation adjustment module for performing a pseudo bit error rate operation on an output voltage signal of the receiving equalizer to generate a common-mode voltage control signal; a common-mode voltage generating module for using the common mode The voltage control signal generates a common-mode voltage and couples the common-mode voltage to the differential transmission channel; and a common-mode voltage detection module for transmitting the common-mode voltage and a reference voltage according to one of the differential transmission channels. A comparison result generates a feedback signal, and the feedback signal is transmitted to the feedforward equalizer to adjust a gain frequency response distribution or a compensation voltage of the feedforward equalizer.

Description

具有自適應發送端等化器調節功能的傳輸電路及利用其之通信裝置Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same

本發明係關於一種發送端等化器調節電路,特別是關於用以實現一高速傳輸介面電路的具有自適應發送端等化器調節功能的傳輸電路。 The present invention relates to an equalizer adjustment circuit at the transmitting end, and more particularly to a transmission circuit with an adaptive equalizer adjustment function at the transmission end for realizing a high-speed transmission interface circuit.

在高速串列資料通信中,由於受通道衰減和趨膚效應等影響,接收端資料會受到嚴重的符號間干擾(inter-symbol interference;ISI)。 In high-speed serial data communication, due to the influence of channel attenuation and skin effects, the receiving end data will be subject to severe inter-symbol interference (ISI).

為解決符號間干擾的問題,一般的作法係在串列資料接收端通過一等化器補償通道衰減,例如採用一決策回饋等化器來消除符號間干擾。然而,由於通道衰減幅度的不確定性和等化器會有工藝的偏差等因素,其補償電路易產生欠補償或者過度補償的現象,而導致接收端的資料恢復裕量變小。 In order to solve the problem of inter-symbol interference, a common method is to compensate channel attenuation by an equalizer at the receiving end of the serial data. For example, a decision feedback equalizer is used to eliminate inter-symbol interference. However, due to the uncertainty of the channel attenuation amplitude and the equalizer's process deviation, the compensation circuit is prone to under- or over-compensation, which results in a smaller data recovery margin at the receiving end.

現有的補償模式一般包括:方法(1)上電後發送端和接收端的協定補償調節;方法(2)通過檢測補償後的資料高頻、低頻分量的比例關係自我調整一連續時間線性等化器;以及方法(3)基於最小平方法(least squares)的自我調整通道補償。然而,方法(1)需要次要通道方能完成,方法(2)需要複雜的頻譜檢測電路,而方法(3)則需複雜的計算。 The existing compensation modes generally include: method (1) agreement compensation adjustment between the sender and receiver after power-on; method (2) self-adjustment by detecting the proportional relationship between the high-frequency and low-frequency components of the compensated data-a continuous-time linear equalizer And method (3) self-adjusting channel compensation based on least squares. However, method (1) requires a secondary channel to complete, method (2) requires a complex spectrum detection circuit, and method (3) requires complex calculations.

為解決上述問題,本領域亟需一新穎的等化器補償電路。 In order to solve the above problems, a novel equalizer compensation circuit is urgently needed in the art.

本發明之一目的在於揭露一種具有自適應發送端等化器調節功能的傳輸電路,其可利用位於接收端的一自適應補償調節模組調整一發送端等化器的補償參數,從而快速又準確的補償一通道衰減效應。 An object of the present invention is to disclose a transmission circuit with an adaptive equalizer adjustment function at the transmitting end, which can use an adaptive compensation adjustment module located at the receiving end to adjust the compensation parameters of an equalizer at the transmitting end, thereby being fast and accurate The compensation of the one-channel attenuation effect.

本發明之另一目的在於揭露一種具有自適應發送端等化器調節功能的傳輸電路,其可利用位於接收端的一自適應補償調節模組調整一差動傳輸共模電壓以調整一發送端等化器的補償參數,從而快速又準確的消除資料信號的符號間干擾現象。 Another object of the present invention is to disclose a transmission circuit with an adaptive equalizer adjustment function at the transmitting end, which can adjust a differential transmission common-mode voltage to adjust a transmitting end, etc. using an adaptive compensation adjustment module located at the receiving end. Compensation parameters of the modulator, thereby quickly and accurately eliminating the phenomenon of intersymbol interference of data signals.

本發明之另一目的在於揭露一種具有自適應發送端等化器調節功能的傳輸電路,其可利用位於接收端的一自適應補償調節模組調整一發送端等化器的補償參數,從而快速又準確的修正電路參數因工藝偏差所造成的影響。 Another object of the present invention is to disclose a transmission circuit with an adaptive equalizer adjustment function at the transmitting end. The adaptive compensation adjustment module located at the receiving end can be used to adjust the compensation parameters of an equalizer at the transmitting end. Accurately correct the influence of circuit parameters due to process deviation.

本發明之又一目的在於揭露一種具有自適應發送端等化器調節功能的傳輸電路,其可在一次補償調節結束後關閉一自適應補償調節模組以節省功耗。 Another object of the present invention is to disclose a transmission circuit with an adaptive equalizer adjustment function at the transmitting end, which can turn off an adaptive compensation adjustment module after one compensation adjustment is completed to save power consumption.

為達前述目的,一種具有自適應發送端等化器調節功能的傳輸電路乃被提出,其具有:一前饋等化器,具有一信號輸入端以接收一傳送資料信號,一回饋輸入端以接收一回饋信號,以及一信號輸出端以提供一傳送電壓信號,所述回饋信號係用以調整該前饋等化器之一增益頻率響應分布或一補償電壓;一驅動單元,具有一輸入端以接收該傳送電壓信號,及二輸出端以輸出一差動電壓信號至一差動傳輸通道;一接收等化器,具有一正接收端、一負接收端及一輸出端,其中,該正接收端及該負接收端係用以與該差動傳輸通道耦接以接收一差動輸入電壓信號,且該輸出端係用以提供一輸出電壓信號;一自適應補償調節模組,具有一輸入端以接收該輸出電壓信號,及一輸出端以提供一共模電壓控制信號,且其係用以對該輸出電壓信號進行一偽誤碼率運算以產生該共模電壓控制信號;一共模電壓產生模組,用以依該共模電壓控制信號產生一共模電壓,並將該共模電壓耦接至該差動傳輸通道;以及一共模電壓檢測模組,具有一輸入端以與該差動傳輸通道耦接以接收一傳輸共模電壓,及一輸出端以提供該回饋信號,且其係用以依該傳輸共模電壓與一第一參考電壓的一比較結果產生該回饋信號。 In order to achieve the foregoing object, a transmission circuit having an adaptive equalizer adjustment function at the transmitting end is proposed, which has: a feedforward equalizer, having a signal input terminal for receiving a transmission data signal, and a feedback input terminal for Receiving a feedback signal and a signal output terminal to provide a transmission voltage signal, the feedback signal is used to adjust a gain frequency response distribution or a compensation voltage of the feedforward equalizer; a driving unit having an input terminal To receive the transmitted voltage signal, and two output terminals to output a differential voltage signal to a differential transmission channel; a receiving equalizer having a positive receiving terminal, a negative receiving terminal and an output terminal, wherein the positive The receiving end and the negative receiving end are used for coupling with the differential transmission channel to receive a differential input voltage signal, and the output end is used for providing an output voltage signal; an adaptive compensation adjustment module having a An input terminal receives the output voltage signal, and an output terminal provides a common-mode voltage control signal, and is used to perform a pseudo bit error rate operation on the output voltage signal to produce The common mode voltage control signal; a common mode voltage generating module for generating a common mode voltage according to the common mode voltage control signal, and coupling the common mode voltage to the differential transmission channel; and a common mode voltage detection module Having an input terminal coupled to the differential transmission channel to receive a transmission common-mode voltage, and an output terminal to provide the feedback signal, and is used to transmit the common-mode voltage and a first reference voltage according to A comparison results in the feedback signal.

在一實施例中,該自適應補償調節模組具有:一第一比較器,具有一第一正輸入端、一第一負輸入端、一第一控制端及一 第一輸出端,該第一正輸入端係與該輸出端耦接,該第一負輸入端係與一第二參考電壓耦接,該第一控制端係與一資料時鐘信號耦接;一第二比較器,具有一第二正輸入端、一第二負輸入端、一第二控制端及一第二輸出端,該第二正輸入端係與該輸出端耦接,該第二負輸入端係與該第二參考電壓耦接,該第二控制端係與一輔助時鐘信號耦接,該輔助時鐘信號和該資料時鐘信號之間具有一相位差;一互斥或運算單元,具有一第一輸入端、一第二輸入端及一第三輸出端,該第一輸入端係與該第一輸出端耦接,該第二輸入端係與該第二輸出端耦接;以及一偽誤碼率計算模組,具有一位元資料輸入端、一第三控制端及一回饋輸出端,該位元資料輸入端係與該第三輸出端耦接,該第三控制端係與一系統時鐘信號耦接,所述回饋輸出端係用以輸出所述共模電壓控制信號,其中,該偽誤碼率計算模組係用以依該系統時鐘信號的控制對由該位元資料輸入端所接收的一互斥或輸出信號進行一偽誤碼率計算之後而產生所述共模電壓控制信號。 In one embodiment, the adaptive compensation adjustment module has: a first comparator having a first positive input terminal, a first negative input terminal, a first control terminal and a A first output terminal, the first positive input terminal is coupled to the output terminal, the first negative input terminal is coupled to a second reference voltage, and the first control terminal is coupled to a data clock signal; The second comparator has a second positive input terminal, a second negative input terminal, a second control terminal, and a second output terminal. The second positive input terminal is coupled to the output terminal and the second negative terminal. The input terminal is coupled to the second reference voltage, the second control terminal is coupled to an auxiliary clock signal, and there is a phase difference between the auxiliary clock signal and the data clock signal; a mutually exclusive OR operation unit having A first input terminal, a second input terminal, and a third output terminal, the first input terminal is coupled to the first output terminal, and the second input terminal is coupled to the second output terminal; and The pseudo bit error rate calculation module has a bit data input terminal, a third control terminal and a feedback output terminal. The bit data input terminal is coupled with the third output terminal, and the third control terminal is connected with A system clock signal is coupled, and the feedback output terminal is used to output the common mode voltage. Control signal, wherein the pseudo bit error rate calculation module is used to generate a pseudo bit error rate calculation for a mutually exclusive or output signal received by the bit data input terminal according to the control of the system clock signal. The common-mode voltage control signal.

在一實施例中,該前饋等化器及該接收等化器均係一連續時間線性等化器或一決策回饋等化器。 In an embodiment, the feedforward equalizer and the receive equalizer are both a continuous-time linear equalizer or a decision feedback equalizer.

在一實施例中,所述之具有自適應發送端等化器調節功能的傳輸電路進一步包含一輔助時鐘產生電路,該輔助時鐘產生電路係用以依該資料時鐘信號產生該輔助時鐘信號。 In an embodiment, the transmission circuit having an adaptive equalizer adjustment function on the transmitting end further includes an auxiliary clock generating circuit, and the auxiliary clock generating circuit is configured to generate the auxiliary clock signal according to the data clock signal.

在一實施例中,該輔助時鐘產生電路包括一相位內插器。 In one embodiment, the auxiliary clock generating circuit includes a phase interpolator.

在一實施例中,該輔助時鐘產生電路包括一延遲鎖相迴路。 In one embodiment, the auxiliary clock generating circuit includes a delay-locked loop.

在一實施例中,該輔助時鐘產生電路包括一延遲電路。 In one embodiment, the auxiliary clock generating circuit includes a delay circuit.

在一實施例中,該偽誤碼率計算係對該互斥或輸出信號進行一脈衝數目統計作業。 In one embodiment, the pseudo bit error rate calculation is performed on the number of pulses of the mutually exclusive or output signal.

也就是說,本發明的具有自適應發送端等化器調節功能的傳輸電路是在一差動傳輸通道的一發送端及一接收端分別設有一前饋等化器及一接收等化器,且其特徵在於,具有:一自適應補償調節模組,具有一輸入端以接收該接收等化器之一輸出電壓信號,及一輸出端以提供一共模電壓控制信號,且其係用以對該輸出電壓信號進行一偽誤碼率運算以產生該共模電壓控制信號;一共模電壓產生模組,用以依該共模電壓控制信號產生一共模電壓,並將該共模電壓耦接至該差動傳輸通道;以及一共模電壓檢測模組,具有一輸入端以與該差動傳輸通道耦接以接收一傳輸共模電壓,及一輸出端以提供一回饋信號至該前饋等化器以調整該前饋等化器之一增益頻率響應分布或一補償電壓,且該共模電壓檢測模組係用以依該傳輸共模電壓與一參考電壓的一比較結果產生該回饋信號。 That is to say, the transmission circuit with the adaptive equalizer adjustment function of the present invention is provided with a feedforward equalizer and a receive equalizer on a transmitting end and a receiving end of a differential transmission channel, respectively. And it is characterized by having an adaptive compensation adjustment module, having an input terminal to receive an output voltage signal from one of the receiving equalizers, and an output terminal to provide a common-mode voltage control signal, and it is used for The output voltage signal performs a pseudo bit error rate operation to generate the common mode voltage control signal; a common mode voltage generating module is used to generate a common mode voltage according to the common mode voltage control signal, and couple the common mode voltage to The differential transmission channel; and a common-mode voltage detection module having an input terminal coupled to the differential transmission channel to receive a transmission common-mode voltage, and an output terminal to provide a feedback signal to the feedforward equalization The modulator adjusts a gain frequency response distribution or a compensation voltage of the feedforward equalizer, and the common-mode voltage detection module is used to generate a comparison result of the transmitted common-mode voltage and a reference voltage. Feedback signal.

另外,為達前述目的,本發明進一步提出一種通信裝置,其具有如前述之具有自適應發送端等化器調節功能的傳輸電路。 In addition, in order to achieve the foregoing object, the present invention further provides a communication device having a transmission circuit with an adaptive equalizer adjustment function as described above.

為使 貴審查委員能進一步瞭解本發明之結構、特徵及其目的,茲附以圖式及較佳具體實施例之詳細說明如後。 In order to enable your reviewers to further understand the structure, characteristics, and purpose of the present invention, drawings and detailed descriptions of the preferred embodiments are attached below.

100‧‧‧前饋等化器 100‧‧‧ Feedforward Equalizer

110‧‧‧驅動單元 110‧‧‧Drive unit

120‧‧‧差動傳輸通道 120‧‧‧ differential transmission channel

130‧‧‧接收等化器 130‧‧‧ receive equalizer

140‧‧‧自適應補償調節模組 140‧‧‧Adaptive compensation adjustment module

141‧‧‧第一比較器 141‧‧‧first comparator

142‧‧‧第二比較器 142‧‧‧Second Comparator

143‧‧‧互斥或運算單元 143‧‧‧mutex or arithmetic unit

144‧‧‧偽誤碼率計算模組 144‧‧‧False Bit Error Rate Calculation Module

150‧‧‧共模電壓產生模組 150‧‧‧ Common Mode Voltage Generation Module

151‧‧‧共模電壓產生單元 151‧‧‧common mode voltage generating unit

152、153‧‧‧耦接電阻 152, 153‧‧‧ Coupling resistance

160‧‧‧共模電壓檢測模組 160‧‧‧Common mode voltage detection module

161‧‧‧比較器 161‧‧‧ Comparator

170‧‧‧輔助時鐘產生電路 170‧‧‧ auxiliary clock generation circuit

圖1繪示本發明之具有自適應發送端等化器調節功能的傳輸電路之一實施例方塊圖。 FIG. 1 is a block diagram of an embodiment of a transmission circuit with an adaptive equalizer adjustment function at the transmitting end according to the present invention.

圖2為利用一輔助時鐘產生電路以依圖1所示之一資料時鐘信號CLK_DATA產生圖1所示之一輔助時鐘信號CLK_AUX的方塊圖。 FIG. 2 is a block diagram of generating an auxiliary clock signal CLK_AUX according to a data clock signal CLK_DATA shown in FIG. 1 using an auxiliary clock generating circuit.

圖3a為經一傳統等化器處理過的資料信號所產生的眼圖。 FIG. 3a is an eye diagram generated by a data signal processed by a conventional equalizer.

圖3b為經本發明的技術方案處理過的資料信號所產生的眼圖。 FIG. 3b is an eye diagram generated by a data signal processed by the technical solution of the present invention.

請參照圖1,其繪示本發明之具有自適應發送端等化器調節功能的傳輸電路之一實施例方塊圖。 Please refer to FIG. 1, which illustrates a block diagram of an embodiment of a transmission circuit with an adaptive equalizer adjustment function at the transmitting end according to the present invention.

如圖1所示,該具有自適應發送端等化器調節功能的傳輸電路包括一前饋等化器100、一驅動單元110、一差動傳輸通道120、一接收等化器130、一自適應補償調節模組140、一共模電壓產生模組150以及一共模電壓檢測模組160。 As shown in FIG. 1, the transmission circuit with an adaptive equalizer adjustment function at the transmitting end includes a feedforward equalizer 100, a drive unit 110, a differential transmission channel 120, a receiving equalizer 130, and a The adaptive compensation adjustment module 140, a common-mode voltage generating module 150, and a common-mode voltage detecting module 160.

前饋等化器100,可為一連續時間線性等化器或一決策回饋等化器,具有一信號輸入端以接收一傳送資料信號DTX,一回饋輸入端以接收一回饋信號FB,以及一信號輸出端以提供一傳送電壓信號VTX,所述回饋信號FB係用以調整該前饋等化器100之一增益頻率響應分布或一補償電壓。由於連續時間線性等化器及決策回饋等化器均為習知的等化器,故在此不擬對其做進一步敘述。 The feedforward equalizer 100 may be a continuous-time linear equalizer or a decision feedback equalizer, having a signal input terminal to receive a transmission data signal D TX , a feedback input terminal to receive a feedback signal FB, and A signal output terminal provides a transmission voltage signal V TX . The feedback signal FB is used to adjust a gain frequency response distribution or a compensation voltage of the feedforward equalizer 100. Since the continuous time linear equalizer and the decision feedback equalizer are conventional equalizers, they are not intended to be further described here.

驅動單元110具有一輸入端以接收該傳送電壓信號VTX,及二輸出端以輸出一差動電壓信號(TXP,TXN)至差動傳輸通道120。 The driving unit 110 has an input terminal for receiving the transmission voltage signal V TX , and two output terminals for outputting a differential voltage signal (TXP, TXN) to the differential transmission channel 120.

接收等化器130,可為一連續時間線性等化器或一決策回饋等化器,具有一正接收端、一負接收端及一輸出端,其中,該正接收端及該負接收端係用以與該差動傳輸通道120耦接以接收一差動輸入電壓信號Vin,且該輸出端係用以提供一輸出電壓信號DRXThe receiving equalizer 130 may be a continuous-time linear equalizer or a decision feedback equalizer, and has a positive receiving end, a negative receiving end, and an output end, wherein the positive receiving end and the negative receiving end are The output terminal is coupled to the differential transmission channel 120 to receive a differential input voltage signal V in , and the output terminal is used to provide an output voltage signal D RX .

自適應補償調節模組140具有一輸入端以接收該輸出電壓信號DRX,及一輸出端以提供一共模電壓控制信號VCMCNTL,且其係用以對該輸出電壓信號DRX進行一偽誤碼率運算以產生該共模電壓控制信號VCMCNTLThe adaptive compensation adjustment module 140 has an input terminal to receive the output voltage signal D RX , and an output terminal to provide a common- mode voltage control signal V CMCNTL , and is used to perform a false error on the output voltage signal D RX . The bit rate is calculated to generate the common-mode voltage control signal V CMCNTL .

共模電壓產生模組150,具有一共模電壓產生單元151及二耦接電阻152、153,係用以依該共模電壓控制信號VCMCNTL產生一共模電壓VCM,並使該共模電壓VCM經二耦接電阻152、153耦接至該差動傳輸通道120之正、負傳輸線。 The common mode voltage generating module 150 has a common mode voltage generating unit 151 and two coupling resistors 152 and 153, which are used to generate a common mode voltage V CM according to the common mode voltage control signal V CMCNTL and make the common mode voltage V CM is coupled to the positive and negative transmission lines of the differential transmission channel 120 through two coupling resistors 152 and 153.

共模電壓檢測模組160具有一輸入端以與該差動傳輸通道120耦接以接收一傳輸共模電壓VTRCM,及一輸出端以提供該回饋信號FB以調整該前饋等化器100之一增益頻率響應分布或一補償電壓,且該共模電壓檢測模組160係用以依一比較器161對該傳輸共模電壓VTRCM與一第一參考電壓VREF1所產生的一比較結果產生該回饋信號FB。 The common mode voltage detection module 160 has an input terminal coupled to the differential transmission channel 120 to receive a transmission common mode voltage V TRCM , and an output terminal to provide the feedback signal FB to adjust the feedforward equalizer 100. A gain frequency response distribution or a compensation voltage, and the common mode voltage detection module 160 is used to compare a transmitted common mode voltage V TRCM with a first reference voltage V REF1 according to a comparator 161 This feedback signal FB is generated.

在一可能的實施例中,如圖1所示,自適應補償調節模組140具有一第一比較器141、一第二比較器142、一互斥或運算單元143、偽誤碼率計算模組144。 In a possible embodiment, as shown in FIG. 1, the adaptive compensation adjustment module 140 has a first comparator 141, a second comparator 142, a mutually exclusive OR operation unit 143, and a pseudo error rate calculation module. Group 144.

第一比較器141具有一第一正輸入端、一第一負輸入端、一第一控制端及一第一輸出端,該第一正輸入端係與接收等化器130之所述輸出端耦接,該第一負輸入端係與一第二參考電壓VREF2耦接,該第一控制端係與一資料時鐘信號CLK_DATA耦接。 The first comparator 141 has a first positive input terminal, a first negative input terminal, a first control terminal, and a first output terminal. The first positive input terminal is connected to the output terminal of the receiving equalizer 130. Coupling, the first negative input terminal is coupled to a second reference voltage V REF2 , and the first control terminal is coupled to a data clock signal CLK_DATA.

第二比較器142具有一第二正輸入端、一第二負輸入端、一第二控制端及一第二輸出端,該第二正輸入端係與接收等化器130之所述輸出端耦接,該第二負輸入端係與該第二參考電壓VREF2耦接,該第二控制端係與一輔助時鐘信號CLK_AUX耦接,該輔助時鐘信號CLK_AUX和該資料時鐘信號CLK_DATA之間具有一相位差。 The second comparator 142 has a second positive input terminal, a second negative input terminal, a second control terminal, and a second output terminal. The second positive input terminal is connected to the output terminal of the receiving equalizer 130. Coupled, the second negative input terminal is coupled to the second reference voltage V REF2 , the second control terminal is coupled to an auxiliary clock signal CLK_AUX, and the auxiliary clock signal CLK_AUX and the data clock signal CLK_DATA have A phase difference.

互斥或運算單元143具有一第一輸入端、一第二輸入端及一第三輸出端,該第一輸入端係與第一比較器141之所述第一輸出端耦接,該第二輸入端係與第二比較器142之所述第二輸出端耦接。 The mutex OR operation unit 143 has a first input terminal, a second input terminal, and a third output terminal. The first input terminal is coupled to the first output terminal of the first comparator 141, and the second The input terminal is coupled to the second output terminal of the second comparator 142.

偽誤碼率計算模組144具有一位元資料輸入端、一第三控制端及一回饋輸出端,該位元資料輸入端係與互斥或運算單元143之所述第三輸出端耦接,該第三控制端係與一系統時鐘信號CLK_SYS耦接,所述回饋輸出端係用以輸出所述共模電壓控制信號VCMCNTL,其中,該偽誤碼率計算模組144係用以依該系統時鐘信號CLK_SYS的控制對由該位元資料輸入端所接收的一互斥或輸出信號進行一偽誤碼率計算之後而產生所述共模電壓控制信號VCMCNTL。在一可能的實施例中,該偽誤碼率計算可為對該互斥或輸出信號進行一脈衝數目統計作業。 The pseudo bit error rate calculation module 144 has a bit data input terminal, a third control terminal, and a feedback output terminal. The bit data input terminal is coupled to the third output terminal of the mutually exclusive OR operation unit 143. The third control terminal is coupled to a system clock signal CLK_SYS, and the feedback output terminal is used to output the common mode voltage control signal V CMCNTL , wherein the pseudo bit error rate calculation module 144 is used to The control of the system clock signal CLK_SYS performs a pseudo bit error rate calculation on a mutually exclusive or output signal received by the bit data input terminal to generate the common-mode voltage control signal V CMCNTL . In a possible embodiment, the calculation of the pseudo bit error rate may be a pulse number counting operation on the mutually exclusive or output signal.

另外,請參照圖2,其為利用一輔助時鐘產生電路170以依資料時鐘信號CLK_DATA產生輔助時鐘信號CLK_AUX的方塊圖,其中,該輔助時鐘產生電路170可由一相位內插器、一延遲鎖相迴路或一延遲電路實現,以使資料時鐘信號CLK_DATA和輔助時鐘信號CLK_AUX之間具有一適當的固定相位差以使自適應補償調節模組140提供一精確的補償功能。 In addition, please refer to FIG. 2, which is a block diagram of using an auxiliary clock generating circuit 170 to generate the auxiliary clock signal CLK_AUX according to the data clock signal CLK_DATA. The auxiliary clock generating circuit 170 may be implemented by a phase interpolator, a delay phase lock A loop or a delay circuit is implemented so that the data clock signal CLK_DATA and the auxiliary clock signal CLK_AUX have an appropriate fixed phase difference so that the adaptive compensation adjustment module 140 provides an accurate compensation function.

另外,請參照圖3a及圖3b,其分別為經一傳統等化器處理過的資料信號所產生的眼圖及經本發明的技術方案處理過的資料信號所產生的眼圖。由圖3a及圖3b可看出,經傳統等化器處理過的資料信號所產生的眼圖的「眼睛」部份較小,而經本發明的技術方案處理過的資料信號所產生的眼圖的「眼睛」部份較大。由於符碼間干擾會使眼圖的「眼睛」部份變小,因此,從圖3a及圖3b可看出本發明的技術方案確實可有效消除資料信號在經通信通道傳輸後所產生的符碼間干擾問題。 In addition, please refer to FIG. 3a and FIG. 3b, which are respectively an eye diagram generated by a data signal processed by a conventional equalizer and an eye diagram generated by a data signal processed by the technical solution of the present invention. It can be seen from FIG. 3a and FIG. 3b that the “eye” part of the eye diagram generated by the data signal processed by the conventional equalizer is smaller, and the eye diagram generated by the data signal processed by the technical solution of the present invention The "eyes" part is larger. Because the inter-symbol interference will make the "eye" part of the eye diagram smaller, it can be seen from Figures 3a and 3b that the technical solution of the present invention can effectively eliminate the symbol generated by the data signal after being transmitted through the communication channel. Inter-symbol interference problem.

另外,依本發明所能獲致的技術效果,本發明的自適應發送端等化器調節電路乃可應用於V-by-one(一種平板顯示器的信號傳輸接口標準)高速串列資料通信、HDMI(high definition multimedia interface;高畫質多媒體介面)資料通信、EDP(embedded display port;嵌入式顯示埠)資料通信、PCIE(peripheral component interconnect-express快速型周邊部件互連)資料通信及USB(universal serial bus;通用序列匯流排)資料通信。 In addition, according to the technical effects that can be achieved by the present invention, the adaptive sender equalizer adjustment circuit of the present invention can be applied to V-by-one (a flat panel display signal transmission interface standard) high-speed serial data communication, HDMI (high definition multimedia interface) data communication, EDP (embedded display port) data communication, PCIE (peripheral component interconnect-express) and USB (universal serial bus; universal serial bus) data communication.

藉由前述所揭露的設計,本發明乃可提供以下優點: With the design disclosed above, the present invention can provide the following advantages:

1.本發明之具有自適應發送端等化器調節功能的傳輸電路可利用位於接收端的一自適應補償調節模組調整一發送端等化器的補償參數,從而快速又準確的補償一通道衰減效應。 1. The transmission circuit with the adaptive equalizer adjustment function of the present invention can use an adaptive compensation adjustment module located at the receiving end to adjust the compensation parameters of the equalizer at the transmitting end, thereby quickly and accurately compensating the attenuation of a channel effect.

2.本發明之具有自適應發送端等化器調節功能的傳輸電路,其可利用位於接收端的一自適應補償調節模組調整一差動傳輸共模電壓以調整一發送端等化器的補償參數,從而快速又準確的消除資料信號的符號間干擾現象。 2. The transmission circuit with an adaptive equalizer adjustment function of the present invention can adjust a differential transmission common-mode voltage to adjust the compensation of an equalizer at the transmitting end by using an adaptive compensation adjustment module located at the receiving end. Parameters, thereby quickly and accurately eliminating the phenomenon of intersymbol interference of data signals.

3.本發明之具有自適應發送端等化器調節功能的傳輸電路,其可利用位於接收端的一自適應補償調節模組調整一發送端等化器的補償參數,從而快速又準確的修正電路參數因工藝偏差所造成的影響。 3. The transmission circuit with the adaptive equalizer adjustment function of the present invention can use an adaptive compensation adjustment module located at the receiving end to adjust the compensation parameters of the equalizer at the transmitting end, thereby quickly and accurately correcting the circuit. Influence of parameters due to process deviation.

4.本發明之具有自適應發送端等化器調節功能的傳輸電路可在一次補償調節結束後關閉一自適應補償調節模組以節省功耗。 4. The transmission circuit with the adaptive equalizer adjustment function of the present invention can turn off an adaptive compensation adjustment module after one compensation adjustment is completed to save power consumption.

本案所揭示者,乃較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。 What is disclosed in this case is a preferred embodiment. For example, those who have partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those skilled in the art, do not depart from the scope of patent rights in this case.

綜上所陳,本案無論就目的、手段與功效,在在顯示其迥異於習知之技術特徵,且其首先發明合於實用,亦在在符合發明之專利要件,懇請 貴審查委員明察,並祈早日賜予專利,俾嘉惠社會,實感德便。 To sum up, regardless of the purpose, method and effect, this case is showing its technical characteristics that are quite different from the conventional ones, and its first invention is practical, and it is also in line with the patent requirements of the invention. Granting patents at an early date will benefit society and feel good.

Claims (10)

一種具有自適應發送端等化器調節功能的傳輸電路,其具有:一前饋等化器,具有一信號輸入端以接收一傳送資料信號,一回饋輸入端以接收一回饋信號,以及一信號輸出端以提供一傳送電壓信號,所述回饋信號係用以調整該前饋等化器之一增益頻率響應分布或一補償電壓;一驅動單元,具有一輸入端以接收該傳送電壓信號,及二輸出端以輸出一差動電壓信號至一差動傳輸通道;一接收等化器,具有一正接收端、一負接收端及一輸出端,其中,該正接收端及該負接收端係用以與該差動傳輸通道耦接以接收一差動輸入電壓信號,且該輸出端係用以提供一輸出電壓信號;一自適應補償調節模組,具有一輸入端以接收該輸出電壓信號,及一輸出端以提供一共模電壓控制信號,且其係用以對該輸出電壓信號進行一偽誤碼率運算以產生該共模電壓控制信號;一共模電壓產生模組,用以依該共模電壓控制信號產生一共模電壓,並將該共模電壓耦接至該差動傳輸通道;以及一共模電壓檢測模組,具有一輸入端以與該差動傳輸通道耦接以接收一傳輸共模電壓,及一輸出端以提供該回饋信號,且其係用以依該傳輸共模電壓與一第一參考電壓的一比較結果產生該回饋信號。A transmission circuit with an adaptive equalizer adjustment function at a transmitting end includes: a feedforward equalizer, a signal input terminal to receive a transmission data signal, a feedback input terminal to receive a feedback signal, and a signal An output terminal for providing a transmission voltage signal, the feedback signal is used to adjust a gain frequency response distribution or a compensation voltage of the feedforward equalizer; a driving unit having an input terminal for receiving the transmission voltage signal, and The two output terminals output a differential voltage signal to a differential transmission channel; a receiving equalizer has a positive receiving terminal, a negative receiving terminal and an output terminal, wherein the positive receiving terminal and the negative receiving terminal are It is used for coupling with the differential transmission channel to receive a differential input voltage signal, and the output end is used to provide an output voltage signal; an adaptive compensation adjustment module has an input end to receive the output voltage signal And an output terminal for providing a common-mode voltage control signal, which is used to perform a pseudo bit error rate operation on the output voltage signal to generate the common-mode voltage control signal; A common-mode voltage generating module is configured to generate a common-mode voltage according to the common-mode voltage control signal, and couple the common-mode voltage to the differential transmission channel; and a common-mode voltage detection module having an input terminal to communicate with The differential transmission channel is coupled to receive a transmission common-mode voltage, and an output terminal is provided to provide the feedback signal, and the differential transmission channel is used to generate the feedback signal according to a comparison result between the transmission common-mode voltage and a first reference voltage. . 如申請專利範圍第1項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該自適應補償調節模組具有:一第一比較器,具有一第一正輸入端、一第一負輸入端、一第一控制端及一第一輸出端,該第一正輸入端係與該輸出端耦接,該第一負輸入端係與一第二參考電壓耦接,該第一控制端係與一資料時鐘信號耦接;一第二比較器,具有一第二正輸入端、一第二負輸入端、一第二控制端及一第二輸出端,該第二正輸入端係與該輸出端耦接,該第二負輸入端係與該第二參考電壓耦接,該第二控制端係與一輔助時鐘信號耦接,該輔助時鐘信號和該資料時鐘信號之間具有一相位差;一互斥或運算單元,具有一第一輸入端、一第二輸入端及一第三輸出端,該第一輸入端係與該第一輸出端耦接,該第二輸入端係與該第二輸出端耦接;以及一偽誤碼率計算模組,具有一位元資料輸入端、一第三控制端及一回饋輸出端,該位元資料輸入端係與該第三輸出端耦接,該第三控制端係與一系統時鐘信號耦接,所述回饋輸出端係用以輸出所述共模電壓控制信號,其中,該偽誤碼率計算模組係用以依該系統時鐘信號的控制對由該位元資料輸入端所接收的一互斥或輸出信號進行一偽誤碼率計算以產生一共模電壓控制信號。The transmission circuit with an adaptive equalizer adjustment function as described in item 1 of the scope of the patent application, wherein the adaptive compensation adjustment module has: a first comparator having a first positive input terminal, a first A negative input terminal, a first control terminal and a first output terminal, the first positive input terminal is coupled to the output terminal, the first negative input terminal is coupled to a second reference voltage, the first The control terminal is coupled to a data clock signal. A second comparator has a second positive input terminal, a second negative input terminal, a second control terminal and a second output terminal. The second positive input terminal Is coupled to the output terminal, the second negative input terminal is coupled to the second reference voltage, the second control terminal is coupled to an auxiliary clock signal, and the auxiliary clock signal and the data clock signal have A phase difference; a mutually exclusive OR operation unit having a first input terminal, a second input terminal and a third output terminal, the first input terminal is coupled to the first output terminal, and the second input terminal Is coupled to the second output terminal; and a pseudo bit error rate calculation module Has a bit data input terminal, a third control terminal and a feedback output terminal, the bit data input terminal is coupled to the third output terminal, and the third control terminal is coupled to a system clock signal, The feedback output terminal is used to output the common-mode voltage control signal, wherein the pseudo bit error rate calculation module is used to control an interaction received by the bit data input terminal according to the control of the system clock signal. Reject or output the signal to perform a pseudo bit error rate calculation to generate a common-mode voltage control signal. 如申請專利範圍第1項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該前饋等化器及該接收等化器均係一連續時間線性等化器或一決策回饋等化器。The transmission circuit with an adaptive equalizer adjustment function as described in item 1 of the scope of patent application, wherein the feedforward equalizer and the receive equalizer are both a continuous time linear equalizer or a decision feedback Equalizer. 如申請專利範圍第2項所述之具有自適應發送端等化器調節功能的傳輸電路,其進一步包含一輔助時鐘產生電路,該輔助時鐘產生電路係用以依該資料時鐘信號產生該輔助時鐘信號。The transmission circuit with an adaptive equalizer adjustment function according to item 2 of the scope of the patent application, further comprising an auxiliary clock generating circuit, which is used to generate the auxiliary clock according to the data clock signal. signal. 如申請專利範圍第4項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該輔助時鐘產生電路包括一相位內插器。The transmission circuit with an adaptive equalizer adjustment function as described in item 4 of the patent application scope, wherein the auxiliary clock generating circuit includes a phase interpolator. 如申請專利範圍第4項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該輔助時鐘產生電路包括一延遲鎖相迴路。The transmission circuit with an adaptive equalizer adjustment function as described in item 4 of the patent application scope, wherein the auxiliary clock generating circuit includes a delay phase locked loop. 如申請專利範圍第4項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該輔助時鐘產生電路包括一延遲電路。The transmission circuit with an adaptive equalizer adjustment function as described in item 4 of the scope of the patent application, wherein the auxiliary clock generating circuit includes a delay circuit. 如申請專利範圍第2項所述之具有自適應發送端等化器調節功能的傳輸電路,其中該偽誤碼率計算係對該互斥或輸出信號進行一脈衝數目統計作業。The transmission circuit with an adaptive equalizer adjustment function as described in item 2 of the scope of the patent application, wherein the pseudo bit error rate calculation is performed on the number of pulses of the mutually exclusive or output signal. 一種具有自適應發送端等化器調節功能的傳輸電路,其在一差動傳輸通道的一發送端及一接收端分別具有一前饋等化器及一接收等化器,其特徵在於,具有:一自適應補償調節模組,具有一輸入端以接收該接收等化器之一輸出電壓信號,及一輸出端以提供一共模電壓控制信號,且其係用以對該輸出電壓信號進行一偽誤碼率運算以產生該共模電壓控制信號;一共模電壓產生模組,用以依該共模電壓控制信號產生一共模電壓,並將該共模電壓耦接至該差動傳輸通道;以及一共模電壓檢測模組,具有一輸入端以與該差動傳輸通道耦接以接收一傳輸共模電壓,及一輸出端以提供一回饋信號至該前饋等化器以調整該前饋等化器之一增益頻率響應分布或一補償電壓,且該共模電壓檢測模組係用以依該傳輸共模電壓與一參考電壓的一比較結果產生該回饋信號。A transmission circuit with an adaptive equalizer adjustment function at a transmitting end, which has a feedforward equalizer and a receive equalizer at a transmitting end and a receiving end of a differential transmission channel, respectively. : An adaptive compensation adjustment module having an input terminal for receiving an output voltage signal from one of the receiving equalizers, and an output terminal for providing a common-mode voltage control signal, which is used to perform a A pseudo bit error rate operation to generate the common mode voltage control signal; a common mode voltage generating module for generating a common mode voltage according to the common mode voltage control signal, and coupling the common mode voltage to the differential transmission channel; And a common-mode voltage detection module having an input terminal coupled to the differential transmission channel to receive a transmission common-mode voltage, and an output terminal to provide a feedback signal to the feed-forward equalizer to adjust the feed-forward One of the equalizers has a gain frequency response distribution or a compensation voltage, and the common mode voltage detection module is configured to generate the feedback signal according to a comparison result of the transmitted common mode voltage and a reference voltage. 一種通信裝置,其具有如申請專利範圍第1至9項中任一項所述之具有自適應發送端等化器調節功能的傳輸電路。A communication device has a transmission circuit with an adaptive equalizer adjustment function at the transmitting end as described in any one of claims 1 to 9.
TW106137620A 2017-10-31 2017-10-31 Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same TWI669918B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW106137620A TWI669918B (en) 2017-10-31 2017-10-31 Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106137620A TWI669918B (en) 2017-10-31 2017-10-31 Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same

Publications (2)

Publication Number Publication Date
TW201919349A TW201919349A (en) 2019-05-16
TWI669918B true TWI669918B (en) 2019-08-21

Family

ID=67347855

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106137620A TWI669918B (en) 2017-10-31 2017-10-31 Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same

Country Status (1)

Country Link
TW (1) TWI669918B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3979579B1 (en) 2020-09-30 2023-11-15 MediaTek Singapore Pte. Ltd. Low power receiver with equalization circuit, communication unit and method therefor
CN112910605B (en) * 2021-02-18 2023-03-24 联想(北京)有限公司 Signal adjusting method and device and electronic equipment
TWI763459B (en) * 2021-04-23 2022-05-01 瑞昱半導體股份有限公司 Switch device and signal adjusting method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85103949A (en) * 1985-05-22 1986-11-19 富士通株式会社 Multilevel signal monitor circuit
CN1503463A (en) * 2002-11-25 2004-06-09 扬智科技股份有限公司 Digital receiver of modulated signal capable of processing various kinds of data rate
US20060109896A1 (en) * 2004-11-23 2006-05-25 Gunter Steinbach Characterizing eye diagrams
TW200807922A (en) * 2006-07-18 2008-02-01 Sunplus Technology Co Ltd Adaptive equalizer apparatus with digital eye-opening monitor unit and method thereof
CN101184071A (en) * 2007-12-20 2008-05-21 清华大学 Blind SNR estimating method based on pseudo-error rate statistics
CN101283560A (en) * 2005-09-19 2008-10-08 Nxp股份有限公司 Data communication circuit with equalization control
CN1965497B (en) * 2004-06-16 2012-05-23 国际商业机器公司 Automatic adaptive equalization method and system for high-speed serial transmission link

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85103949A (en) * 1985-05-22 1986-11-19 富士通株式会社 Multilevel signal monitor circuit
CN1503463A (en) * 2002-11-25 2004-06-09 扬智科技股份有限公司 Digital receiver of modulated signal capable of processing various kinds of data rate
CN1965497B (en) * 2004-06-16 2012-05-23 国际商业机器公司 Automatic adaptive equalization method and system for high-speed serial transmission link
US20060109896A1 (en) * 2004-11-23 2006-05-25 Gunter Steinbach Characterizing eye diagrams
CN101283560A (en) * 2005-09-19 2008-10-08 Nxp股份有限公司 Data communication circuit with equalization control
TW200807922A (en) * 2006-07-18 2008-02-01 Sunplus Technology Co Ltd Adaptive equalizer apparatus with digital eye-opening monitor unit and method thereof
TWI322588B (en) * 2006-07-18 2010-03-21 Sunplus Technology Co Ltd Adaptive equalizer apparatus with digital eye-opening monitor unit and method thereof
CN101184071A (en) * 2007-12-20 2008-05-21 清华大学 Blind SNR estimating method based on pseudo-error rate statistics

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
B.W. Sprinkle,"Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniques", Proceedings. International Test Conference 1990,10-14 Sept. 1990
B.W. Sprinkle,"Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniques", Proceedings. International Test Conference 1990,10-14 Sept. 1990 Sung-Man Kim, "An Algorithm for Bit Error Rate Monitoring and Adaptive Decision Threshold Optimization Based on Pseudo-error Counting Scheme", Journal of the Optical Society of Korea Vol. 14, No. 1, March 2010, pp. 22-27 *
Sung-Man Kim, "An Algorithm for Bit Error Rate Monitoring and Adaptive Decision Threshold Optimization Based on Pseudo-error Counting Scheme", Journal of the Optical Society of Korea Vol. 14, No. 1, March 2010, pp. 22-27。

Also Published As

Publication number Publication date
TW201919349A (en) 2019-05-16

Similar Documents

Publication Publication Date Title
US9705708B1 (en) Integrated circuit with continuously adaptive equalization circuitry
US10498562B2 (en) Electric signal transmission device
Schrader et al. Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-/spl mu/m CMOS
TWI669918B (en) Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same
KR102430572B1 (en) Electronic device including equalizer operating based on coefficient adjusted in training operation
US20120207204A1 (en) Clock Recovery Circuit for Receiver Using Decision Feedback Equalizer
JP5834984B2 (en) System and method for adaptive phase equalization
CN111131101B (en) Feedback equalization circuit
Hidaka et al. A 4-channel 10.3 Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel
Su et al. A 5 Gb/s voltage-mode transmitter using adaptive time-based de-emphasis
US8432960B2 (en) Digital adaptive channel equalizer
US20180191530A1 (en) Backchannel transmission adaptation
EP2487848B1 (en) Analog continuous-time phase equalizer for data transmission
Roshan-Zamir et al. A 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65nm CMOS
KR101148596B1 (en) Voltage-mode driver with capacitive coupling equalizer and pre-emphasis method in the voltage-mode drivers
TWI663840B (en) Adjusting circuit of adaptive receiving equalizer and communication device using same
US20090323794A1 (en) Transmitter Equalization Method and System
Lee et al. 0.37-pJ/b/dB PAM-4 transmitter and adaptive receiver with fixed data and threshold levels for 12-m automotive camera link
US10721102B2 (en) Communication apparatus and communication method
Kye et al. A 22-Gb/s 0.95-pJ/b energy-efficient voltage-mode transmitter with time-based feedforward equalization in a 28-nm CMOS
US9998303B1 (en) Method of adaptively controlling a low frequency equalizer
JP2008124670A (en) Data reception device
WO2017037836A1 (en) Signal transmission apparatus and signal transmission system
TWI575893B (en) Transceiver and operation method thereof
US10581646B1 (en) Asynchronous data correction filter