TWI664727B - Semiconductor devices and methods for fabricating the same - Google Patents

Abstract

A semiconductor device includes a compound semiconductor layer provided on a substrate and a protective layer provided on the compound semiconductor layer. The source electrode, the drain electrode, and the gate electrode pass through the protective layer and are disposed on the compound semiconductor layer. The semiconductor device further includes a gate field plate, which is connected to the gate electrode and is disposed on a portion of the protective layer between the gate electrode and the drain electrode. The gate field plate has an extension that extends into the protective layer.

Description

Semiconductor device and manufacturing method thereof

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a field plate and a manufacturing method thereof.

GaN-based semiconductor materials have many excellent material properties, such as high thermal resistance, wide band-gap, and high electron saturation rate. Therefore, gallium nitride-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, gallium nitride-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterogeneous interface structures. ).

The field plate is usually disposed in a high electric field region of a semiconductor device, and is used to reduce the peak electric field in the high electric field region. One of the field plates is a field plate electrically connected to a gate (ie, a gate field plate). It reduces the electric field strength of the gate on the drain side. Therefore, the gate field plate can increase the breakdown voltage of the semiconductor device to allow the semiconductor device to be applied to high-voltage operation.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, the processing conditions of semiconductor devices with gallium nitride-based semiconductor materials also face many new challenges.

Some embodiments of the present invention provide a semiconductor device in which a compound semiconductor layer is disposed on a substrate, a protective layer is disposed on the compound semiconductor layer, and a source electrode, a drain electrode, and a gate electrode pass through the protective layer and are disposed. On the compound semiconductor layer. The semiconductor device further includes a gate field plate, which is connected to the gate electrode and is disposed on a portion of the protective layer between the gate electrode and the drain electrode. The gate field plate has an extension that extends into the protective layer.

Some embodiments of the present invention provide a method for manufacturing a semiconductor device. The method includes forming a compound semiconductor layer on a substrate, forming a first protective layer on the compound semiconductor layer, forming a source electrode, a drain electrode, and A gate electrode is formed on the compound semiconductor layer, and a gate field plate is formed on a portion of the protective layer between the gate electrode and the drain electrode to connect the gate electrode, wherein the gate field plate has an extension to the protection. Extensions in layers.

100, 200‧‧‧ semiconductor devices

102‧‧‧ substrate

104‧‧‧Buffer layer

106‧‧‧GaN semiconductor layer

108‧‧‧AlGaN semiconductor layer

109‧‧‧ doped compound semiconductor block

110‧‧‧first protective layer

112‧‧‧Second protective layer

114‧‧‧Source electrode

116‧‧‧Drain electrode

118‧‧‧The first depression

120‧‧‧Second depression

122‧‧‧ Third depression

124‧‧‧Gate electrode

126‧‧‧Gate field plate

128‧‧‧ Connection Department

130‧‧‧First extension

132‧‧‧second extension

134‧‧‧Interlayer dielectric layer

136‧‧‧Source contact

138‧‧‧ Drain contact

140‧‧‧Gate contact

150‧‧‧ the first patterned mask layer

152‧‧‧First opening

160‧‧‧Second patterned mask layer

162‧‧‧Second opening

164‧‧‧Third opening

170‧‧‧ the third patterned mask layer

172‧‧‧ Fourth opening

174‧‧‧Fifth opening

176‧‧‧ sixth opening

Through the following detailed description and examples in conjunction with the accompanying drawings, the embodiments of the present invention can be better understood. In order to make the drawings clear, the different elements in the drawings may not be drawn to scale, where:

1A to 1H are schematic cross-sectional views illustrating various steps of forming a semiconductor device according to some embodiments of the present invention.

2A to 2H are schematic cross-sectional views illustrating various steps of forming a semiconductor device according to other embodiments of the present invention.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of components and their configurations The description is as follows to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment where the first and second elements are in direct contact, or it may include an additional element formed between the first and second elements. So that they are not in direct contact with the embodiment. In addition, embodiments of the present invention may repeat reference numbers and / or letters in different examples. This repetition is for brevity and clarity and is not intended to represent the relationship between the different embodiments discussed.

Some variations of the embodiments are described below. In different illustrated and illustrated embodiments, similar component symbols are used to identify similar components. It can be understood that additional steps can be provided before, during, and after the method, and some of the described steps can be replaced or deleted for other embodiments of the method.

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, and are particularly suitable for a high electron mobility transistor (HEMT). Due to the high electric field strength between the gate electrode and the drain electrode, a material layer located near the drain side of the gate electrode may be punched through. In order to slow down the electric field gradient of the gate electrode near the side of the drain electrode, the embodiment of the present invention utilizes the formation of a gate field plate with an extension extending into the protective layer, which can slow the gate electrode on the side close to the drain electrode. The electric field gradient at the edge can increase the breakdown voltage of the semiconductor device, thereby improving the performance of the semiconductor device.

1A to 1H are schematic cross-sectional views illustrating various steps of forming the semiconductor device 100 shown in FIG. 1H according to some embodiments of the present invention. Referring to FIG. 1A, a substrate 102 is provided. Next, a buffer layer 104 is formed on the substrate 102, a gallium nitride (GaN) semiconductor layer 106 is formed on the buffer layer 104, and an aluminum gallium nitride (Al _x Ga _1-x N) is formed on the gallium nitride semiconductor layer 106. , Where 0 <x <1) of the semiconductor layer 108. In some embodiments, a seed layer (not shown) may be formed between the substrate 102 and the buffer layer 104.

In some embodiments, the substrate 102 may be a doped (eg, doped with a p-type or n-type dopant) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like Semiconductor substrate. In some embodiments, the substrate 102 may be a substrate on which a semiconductor is located on an insulator, such as a silicon on insulator (SOI) substrate. In some embodiments, the substrate 102 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire substrate.

The material of the seed layer may be formed of aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al), or a combination thereof, and the crystal The seed layer may be a single or multilayer structure. The seed layer can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods.

The buffer layer 104 can slow down the strain of the gallium nitride semiconductor layer 106 formed subsequently on the buffer layer 104 to prevent defects from being formed in the gallium nitride semiconductor layer 106 above. The mismatch between the substrates 102 is caused. In some embodiments, the material of the buffer layer 104 may be AlN, GaN, Al _x Ga _1-x N (where 0 <x <1), a combination of the foregoing, or similar materials. The buffer layer 104 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method. Although in the embodiment shown in FIG. 1A, the buffer layer 104 has a single-layer structure, the buffer layer 104 may have a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 104 is determined by the material of the seed layer and the gas introduced during the epitaxial process.

A two-dimensional electron gas (2DEG) (not shown) is formed on the hetero interface between the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108. The semiconductor device 100 shown in FIG. 1H is a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108 are free of dopants. In some other embodiments, the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108 may have a dopant, such as an n-type dopant or a p-type dopant. The gallium nitride semiconductor layer 104 and the gallium aluminum nitride semiconductor layer 106 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) ), A combination of the foregoing, or similar methods.

With continued reference to FIG. 1A, a first protection layer 110 is formed on the gallium aluminum nitride semiconductor layer 108. A second protective layer 112 is formed on the first protective layer 110. In some embodiments, the material of the first protective layer 110 and the second protective layer 112 may be an insulating material or a dielectric material, such as silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), Alumina (Al ₂ O ₃ ), aluminum nitride (AlN), magnesium oxide (MgO), magnesium nitride (Mg ₃ N ₂ ), zinc oxide (ZnO), titanium oxide (TiO ₂ ), or a combination thereof. The first protective layer 110 and the second protective layer 112 are used to prevent a leakage current from the underlying GaN aluminum semiconductor layer 108 to the source electrode 114, the drain electrode 116, and the gate electrode 124 (shown in FIG. ). The first protective layer 110 and the second protective layer 112 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. .

In some embodiments, the material of the second protective layer 112 is different from the material of the first protective layer 110. For example, a high-quality oxide film, such as a silicon oxide film, can be used for the first protective layer 110 below, and a high etch selectivity relative to the first protective layer 110 can be used for the second protective layer 112 above. Dielectric materials, such as silicon nitride.

Although in the embodiment shown in FIG. 1A, two protective layers 110 and 112 are formed on the aluminum gallium nitride semiconductor layer 108, in other embodiments, one or more protective layers may be formed. Over the gallium aluminum nitride semiconductor layer 108.

Referring to FIG. 1B, a source electrode 114 and a drain electrode 116 are formed on the gallium nitride semiconductor layer 108. The source electrode 114 and the drain electrode 116 pass through the second protective layer 112 and the first protective layer 110. To contact the gallium aluminum nitride semiconductor layer 108. In some embodiments, the material of the source electrode 114 and the drain electrode 116 may be a conductive material, such as a metal material or a semiconductor material. The metal material can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a similar material, a combination of the foregoing, or a plurality of the foregoing. The semiconductor material may be doped polycrystalline silicon, polycrystalline germanium, or a similar material. The step of forming the source electrode 114 and the drain electrode 116 may include forming openings (not shown) for the source electrode 114 and the drain electrode 116 through an etching process, and the openings pass through the second protective layer 112 and the first protective layer. 110, and the upper surface of the gallium aluminum nitride semiconductor layer 108 is exposed, a conductive material layer (not shown) is deposited on the second protective layer 112 and filled in these openings, and a patterning process is performed on the conductive material layer to shape As a source electrode 114 and a drain electrode 116. The deposition process for forming the source electrode 114 and the drain electrode 116 may be an atomic layer deposition (ALD), a chemical vapor deposition (CVD), a physical vapor deposition (PVD), sputtering, or a similar process.

Referring to FIG. 1C, a first patterned masking layer 150 is formed on the second protective layer 112. The first patterned masking layer 150 has a first opening 152, and the first opening 152 exposes a region on the upper surface of the second protective layer 112 where the gate electrode 124 (shown in FIG. 1G) is formed. In some embodiments, the first patterned mask layer 150 may be a patterned photoresist layer or a patterned hard mask layer.

Then, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the first opening 152 of the first patterned mask layer 150. As shown in FIG. 1D, after the etching process, a first recess 118 is formed in the second protective layer 112 and the first protective layer 110. The first recess 118 passes through the second protective layer 112 and the first protective layer 110 to expose the upper surface of the gallium aluminum nitride semiconductor layer 108. In some embodiments, the etching process may be a dry etching process, a wet etching process, or a combination thereof. The dry etching process may be, for example, reactive ion etch (RIE), electron cyclotron resonance (ERC) etching, inductively-coupled plasma (ICP) etching, or similar dry etching Process. The etching process may select a suitable etchant for the materials of the second protective layer 112 and the first protective layer 110. For example, in an embodiment in which the second protection layer 112 is silicon nitride and the first protection layer 110 is silicon oxide, a portion of the second protection layer 112 exposed by the opening 152 may be removed with phosphoric acid first. Until the upper surface of the first protective layer 110 is exposed, and The released hydrofluoric acid (dHf) removes the part of the first protective layer 110 exposed by the opening 152.

Then, the first patterned masking layer 150 on the second protective layer 112 is removed. In some embodiments, the first patterned masking layer 150 may be removed using an ash process or a lift-off process.

Referring to FIG. 1E, a second patterned masking layer 160 is formed on the second protective layer 112. The second patterned masking layer 160 has second openings 162 and third openings 164 that expose areas on the upper surface of the second protective layer 112. These areas are intended to form extensions 130 and 132 of the gate field plate 126 (shown in FIG. Figure 1G). In some embodiments, the second patterned mask layer 160 may be a patterned photoresist layer or a patterned hard mask layer.

Then, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the second opening 162 and the third opening 164 of the second patterned mask layer 160. As shown in FIG. 1F, after the etching process, a second depression 120 and a third depression 122 are formed in the second protection layer 112 and the first protection layer 110. The second recess 120 and the third recess 122 pass through the second protective layer 112 and extend into the first protective layer 110. The second recess 120 and the third recess 122 do not pass through the first protection layer 110, so the portions of the first protection layer 110 directly under the second recess 120 and the third recess 122 remain on the gallium nitride semiconductor layer 108. . In some embodiments, the etching process may include a main etching step for the second protective layer 112 to form a second recess 120 and a third recess 122 in the second protective layer 112, and include an over-etching step to convert the second The recess 120 and the third recess 122 extend into the first protective layer 110. For example, after the main etching of the second protective layer 112 is ended, the substrate 102 may not be removed from the etching equipment, and the over-etching of the first protective layer may be continuously performed for a period of time, for example, about 10% to About 30%. In some embodiments, the etching process for forming the second recess 120 and the third recess 122 may be a dry etching process, a dry etching process, or a combination thereof, and may be the same, similar, or different from the aforementioned etching process for forming the first recess 118. .

Then, the second patterned masking layer 160 on the second protective layer 112 is removed. In some embodiments, the second patterned masking layer 160 may be removed using an ash process or a lift-off process.

Referring to FIG. 1G, a gate electrode 124 and a gate field plate 126 connected to the gate electrode 124 are formed on the second protection layer 112. The gate electrode 124 is filled in the first recess 118 and contacts the gallium aluminum nitride semiconductor layer 108. The gate field plate 126 has a connection portion 128 to which the gate electrode 124 is connected, and a first extension portion 130 and a second extension portion 132 which are respectively filled in the second depression 120 and the third depression 122. The connection portion 128 is located on a region on the upper surface of the second protective layer 112 between the gate electrode 124 and the drain electrode 116.

In some embodiments, the steps of forming the gate electrode 124 and the gate field plate 126 may include depositing a conductive material layer (not shown) on the second protective layer 112 and filling the first recess 118 and the second recess 120. And a third recess 122, and patterning the conductive material layer. The patterning of the conductive material layer may include forming a patterned mask layer (not shown) on the conductive material layer through a photolithography process, and performing an etching process such as dry etching or wet etching on the conductive material layer to remove the conductive material layer. The portion covered by the patterned masking layer is then removed from the remaining portion of the conductive material layer. The conductive material layer may be a metal or a semiconductor material. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), similar materials, a combination of the foregoing, or the foregoing Of multiple layers. The semiconductor material may be doped polycrystalline silicon, polycrystalline germanium, or a similar material. The conductive material layer may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or similar processes.

Referring to FIG. 1H, an inter-layer dielectric layer (ILD layer) 134 is formed on the second protective layer 112. The inter-layer dielectric layer 134 covers the gate electrode 124, the gate field plate 126, and the source electrode. 114 and drain electrode 116. Next, a source contact 136 connected to the source electrode 114, a drain contact 138 connected to the drain electrode 116, and a gate contact 140 connected to the gate electrode 124 are formed in the interlayer dielectric layer 134. After forming an interconnect structure including the interlayer dielectric layer 134, the source contact 136, the drain contact 138, and the gate contact 140, the semiconductor device 100 is formed.

In some embodiments, the material of the interlayer dielectric layer 134 may be silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, a similar material, a combination of the foregoing, or a plurality of the foregoing. The interlayer dielectric layer 134 may be formed by chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like.

In some embodiments, the material of the source contact 136, the drain contact 138, and the gate contact 140 may be a metal material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd) , Iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing or a plurality of the foregoing. The step of forming the source contact 136, the drain contact 138, and the gate contact 140 may include forming openings (not shown) corresponding to the source electrode 114, the drain electrode 116, and the gate electrode 124 through a patterning process. It passes through the interlayer dielectric layer 134 and exposes the source electrode 114, the drain electrode 116, and the gate electrode 124, respectively, and a metal material (not shown) is deposited on the layer The interlayer dielectric layer 134 is filled with openings, and a planarization process such as chemical mechanical polishing (CMP) is performed to remove a portion of the metal material above the interlayer dielectric layer 130.

In the embodiment shown in FIG. 1H, the semiconductor device 100 includes a substrate 102 and a buffer layer 104, a gallium nitride semiconductor layer 106, and a gallium aluminum nitride semiconductor layer 108 sequentially stacked on the substrate 102. The semiconductor device 100 further includes a first protection layer 110 disposed on the gallium aluminum semiconductor layer 108, a second protection layer 112 disposed on the first protection layer 110, and a source electrode 114, a drain electrode 116, and a gate electrode. The electrode 124 passes through the second protective layer 112 and the first protective layer 110 and contacts the gallium aluminum nitride semiconductor layer 108.

The semiconductor device 100 further includes a gate field plate 126 connected to the gate electrode 124. The gate field plate 126 has a connection portion 128 connected to the gate electrode 124, and the first extension portion 130 and the second extension portion 132 extend to the second protective layer. 112 and the first protective layer 110. The connection portion 128 is located on the second protection layer 112 and extends from the gate electrode 124 toward the drain electrode 116. The first extension 130 and the second extension 132 are interposed between the gate electrode 124 and the drain electrode 116, and the upper surfaces of the first extension 130 and the second extension 132 and the gallium aluminum semiconductor layer 108 are A protective layer 110 is separated.

In general, when an operating voltage is applied to the gate electrode and the drain electrode, the material layer located near the drain side of the gate electrode may be broken due to the high electric field strength between the gate electrode and the drain electrode. (punch through), especially at the corner of the gate electrode. It is worth noting that, in the embodiment of the present invention, the gate electrode 124 and the drain electrode 116 have a gate field plate 126 connected to the gate electrode 124, which can slow the gate electrode 124 close to the drain electrode 116. side The electric field gradient of the edge. Furthermore, since the gate field plate 126 has a first extension portion 130 and a second extension portion 132 extending into the second protection layer 112 and the first protection layer 110, the electric field distribution under the connection portion 128 is concentrated to the extension portion. 130 and 132, which can further reduce the electric field gradient of the gate electrode 124 on the side close to the drain electrode 116. Therefore, in the embodiment of the present invention, a gate field plate is used, which has an extension portion extending into the protective layer, so as to improve the breakdown voltage of the semiconductor device, thereby improving the efficiency of the semiconductor device 100.

Although in the embodiment shown in FIG. 1H, the gate field plate 126 has two extensions 130 and 132 between the gate electrode 124 and the drain electrode 116, however, in other embodiments, the gate field The plate 126 may have one or more extensions between the gate electrode 124 and the drain electrode 116 to reduce the electric field gradient of the gate electrode 124 near the side of the drain electrode 116. In addition, the widths of the first extending portion 130 and the second extending portion 132 and the distance between the first extending portion 130 and the second extending portion 132 may depend on design requirements, and are not limited to the embodiment in FIG. 1H.

In addition, since the first extension portion 130 and the second extension portion 132 of the gate field plate 126 pass through the second protective layer 112 and extend into the first protective layer 110, they are close to the first extension of the gallium aluminum nitride semiconductor layer 108. The portion 130 and the second extension portion 132 help the semiconductor device 100 to conduct thermal energy generated during operation, so as to improve the performance of the semiconductor device 100.

2A-2H are schematic cross-sectional views of the semiconductor device 200 shown in FIG. 2H at various stages according to other embodiments of the present invention. The same components as those in the embodiment shown in FIGS. 1A-1H are used. And their descriptions are omitted. The embodiment shown in Figs. 2A-2H is the same as the embodiment shown in Figs. 1A-1H. The difference between the embodiments is that the semiconductor device 200 in FIGS. 2A-2H further includes a doped compound semiconductor block 109 interposed between the gallium nitride green semiconductor layer 108 and the gate electrode 124.

Referring to FIG. 2A, a substrate 102 is provided. Next, a buffer layer 104, a gallium nitride semiconductor layer 106, and a gallium aluminum nitride semiconductor layer 108 are sequentially formed on the substrate 102. Next, a doped compound semiconductor block 109 is formed on the gallium aluminum nitride semiconductor layer 108. The doped compound semiconductor block 109 may be rectangular as shown in the figure, or other shapes, such as trapezoidal. In addition, the upper surface of the doped compound semiconductor block 109 may not be flat.

In a subsequent process, a gate electrode 124 (shown in FIG. 2G) will be formed on the doped compound semiconductor block 109. By setting the doped compound semiconductor block 109 between the gate electrode 124 and the gallium aluminum semiconductor layer 108, the generation of two-dimensional electron gas (2DEG) under the gate electrode 124 can be suppressed to achieve the normally off of the semiconductor device. status. In some embodiments, the material of the doped compound semiconductor block 109 may be GaN doped with p-type or n-type. The step of forming the doped compound semiconductor block 109 may include depositing a doped compound semiconductor layer (not shown) on the gallium aluminum semiconductor layer 108 through an epitaxial growth process, and performing a patterning process on the doped compound semiconductor layer. To form the doped compound semiconductor block 109 corresponds to a position where the gate electrode 124 is to be formed.

With continued reference to FIG. 2A, a first protective layer 110 is formed on the gallium aluminum nitride semiconductor layer 108. The first protective layer 110 conformally extends on the sidewall and the upper surface of the doped compound semiconductor block 109. Next, a second protective layer 112 is formed on the first protective layer 110. The first protective layer 110 and the second protective layer 112 conform to the sidewall and top surface shapes of the doped compound semiconductor block 109. So that the first protective layer 110 and the second protective layer 112 each have a horizontal portion directly above the doped compound semiconductor block 109. In some embodiments, the material of the second protective layer 112 is different from the material of the first protective layer 110.

Referring to FIG. 2B, a source electrode 114 and a drain electrode 116 are formed on the gallium nitride semiconductor layer 108. The source electrode 114 and the drain electrode 116 pass through the second protective layer 112 and the first protective layer 110. To contact the gallium aluminum nitride semiconductor layer 108.

Next, a planarization process is performed on the second protective layer 112, such as chemical mechanical polishing (CMP). As shown in FIG. 2C, after the planarization process, the horizontal portion of the second protective layer 112 directly above the doped compound semiconductor block 109 is removed. A horizontal portion of the first protective layer 110 directly above the doped compound semiconductor block 109 is exposed from the second protective layer 112, and an upper surface of the exposed horizontal portion of the first protective layer 110 and the second protective layer 112 are exposed. The upper surfaces are coplanar.

Referring to FIG. 2D, a third patterned masking layer 170 is formed on the second protective layer 112 and the exposed horizontal portions of the first protective layer. The third patterned masking layer 170 has a third opening 172, a fourth opening 174, and a fifth opening 176. The third opening 172 corresponds to an exposed horizontal portion of the first protective layer 110. The fourth opening 174 and the fifth opening 176 expose areas on the upper surface of the second protective layer 112, which are intended to form the extensions 130 and 132 of the gate field plate 126 (shown in FIG. 2G). In some embodiments, the material and forming method of the third patterned masking layer 170 may be the same as or similar to the first patterned masking layer 150 in FIG. 1C described above.

Next, through the third opening 172 of the third patterned masking layer 170 An etching process is performed on the first protective layer 110. In detail, in this embodiment, the etching process may use an etchant, which has a higher etching rate for the first protective layer 110 than the second protective layer 112. Since the second protective layer 112 has a high etching selectivity with respect to the first protective layer 110, the etchant hardly etches the fourth opening 174 and the fifth opening 176 of the second protective layer 112 from the third patterned masking layer 170. Exposed part.

As shown in FIG. 2E, after the etching process, a first recess 118 is formed in the first protective layer 110, and the first recess 118 exposes the upper surface of the doped compound semiconductor block 109. Since the third opening 172 of the third patterned masking layer 170 corresponds to the horizontal portion of the first protective layer 110, the first recess 118 passes only through the first protective layer 110 and does not pass through the second protective layer 112.

Next, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the fourth opening 174 and the fifth opening 176 of the third patterned mask layer 170. In detail, in this embodiment, the doped compound semiconductor block 109 has high etch selectivity with respect to the second protective layer 112 and the first protective layer 110, so the etchant hardly etches the doped compound semiconductor region. The portion of the block 109 exposed from the third opening 172 of the third patterned masking layer 170. Furthermore, in this embodiment, the etching process may include a main etching step for the second protective layer 112 and an over-etching step for the first protective layer 110.

As shown in FIG. 2F, after the etching process, a second depression 120 and a third depression 122 are formed in the second protection layer 112 and the first protection layer 110. The second recess 120 and the third recess 122 pass through the second protective layer 112 and extend into the first protective layer 110. The second recess 120 and the third recess 122 do not pass through the first protection layer 110, so the first protection layer 110 is directly below the second recess 120 and the third recess 122 The portion remains on the GaN aluminum semiconductor layer 108.

Next, the third patterned masking layer 170 on the first protective layer 110 and the second protective layer 112 is removed.

Referring to FIG. 2G, a gate electrode 124 and a gate field plate 126 connected to the gate electrode 124 are formed on the first protection layer 110 and the second protection layer 112. The gate electrode 124 is filled in the first recess 118 and contacts the doped compound semiconductor block 109. The gate field plate 126 has a connection portion 128 to which the gate electrode 124 is connected, and a first extension portion 130 and a second extension portion 132 which are respectively filled in the second depression 120 and the third depression 122. The connection portion 128 is located on a region on the upper surface of the second protective layer 112 between the gate electrode 124 and the drain electrode 116.

Referring to FIG. 2H, an interlayer dielectric layer 134 is formed on the first protection layer 110 and the second protection layer 112. The interlayer dielectric layer 134 covers the gate electrode 124, the gate field plate 126, the source electrode 114, and the drain electrode.极 electrode 116. Next, a source contact 136 connected to the source electrode 114, a drain contact 138 connected to the drain electrode 116, and a gate contact 140 connected to the gate electrode 124 are formed in the interlayer dielectric layer 134. After forming an interconnect structure including the interlayer dielectric layer 134, the source contact 136, the drain contact 138, and the gate contact 140, a semiconductor device 200 is formed.

In the embodiment shown in FIG. 2H, the semiconductor device 200 includes a substrate 102 and a buffer layer 104, a gallium nitride semiconductor layer 106, a gallium nitride semiconductor layer 108, and a doped compound sequentially stacked on the substrate 102. Semiconductor block 109. The semiconductor device 200 further includes a first protection layer 110 disposed on the gallium aluminum nitride semiconductor layer 108 and surrounding a sidewall of the doped compound semiconductor block 109, and a second protection layer 112 disposed on the first protection layer 110. Wherein the second protective layer 112 It is not directly above the doped compound semiconductor block 109. The semiconductor device 200 further includes a source electrode 114 and a drain electrode 116 passing through the second protective layer 112 and the first protective layer 110 and contacting the gallium nitride semiconductor layer 108.

The semiconductor device 200 further includes a gate electrode 124 passing through the first protective layer 110 and contacting the doped compound semiconductor block 109, and a gate field plate 126 connected to the gate electrode 124. The gate field plate 126 has a connection portion 128 connected to the gate electrode 124, and the first extension portion 130 and the second extension portion 132 extend into the second protection layer 112 and the first protection layer 110. The connection portion 128 is located on the second protection layer 112 and extends from the gate electrode 124 toward the drain electrode 116. The first extension 130 and the second extension 132 are interposed between the gate electrode 124 and the drain electrode 116, and the upper surfaces of the first extension 130 and the second extension 132 and the gallium aluminum semiconductor layer 108 are A protective layer 110 is separated.

In the embodiment shown in FIGS. 2A-2H, the first recess 118, the second recess 120, and the third recess 122 for forming the gate electrode 124 and the gate field plate 126 are formed by the same patterned mask layer. 170 is formed, so a patterning process for forming a depression can be saved, so that the manufacturing efficiency of the semiconductor device can be improved.

In summary, in the embodiment of the present invention, the gate field plate has an extension portion extending into the protective layer, which can reduce the electric field gradient of the gate electrode near the side of the drain electrode to increase the breakdown voltage of the semiconductor device ( breakdown voltage), thereby improving the performance of the semiconductor device.

The foregoing summarizes several embodiments so that those having ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same results as described herein. This embodiment has the same purpose and / or advantages. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

Claims (19)

A semiconductor device includes: a compound semiconductor layer disposed on a substrate; a protective layer disposed on the compound semiconductor layer; a source electrode, a drain electrode, and a gate electrode passing through the protection; And a gate field plate connected to the gate electrode and disposed on a portion of the protective layer between the gate electrode and the drain electrode, wherein the gate The polar field plate has an extension portion extending into the protection layer, wherein the extension portion and the gate electrode are separated by the protection layer. The semiconductor device according to item 1 of the scope of patent application, wherein the extension of the gate field plate is separated from the compound semiconductor layer. The semiconductor device according to item 1 of the scope of patent application, wherein the protective layer comprises: a first protective layer provided on the compound semiconductor layer; and a second protective layer provided on the first protective layer, the The material of the first protective layer is different from that of the second protective layer. The semiconductor device according to item 3 of the scope of patent application, wherein the extension of the gate field plate passes through the first protective layer and extends into the second protective layer. The semiconductor device according to item 1 of the patent application scope further includes: a doped compound semiconductor block disposed between the compound semiconductor layer and the gate electrode. The semiconductor device according to item 5 of the patent application scope, wherein the protective layer includes: a first protective layer surrounding a sidewall of the doped compound semiconductor block; and a second protective layer disposed on the first protective layer On the layer, the second protective layer is not directly above the doped compound semiconductor block, and the material of the first protective layer is different from that of the second protective layer. The semiconductor device according to item 6 of the scope of patent application, wherein the first protective layer has a horizontal portion above the doped compound semiconductor block, and an upper surface of the horizontal portion of the first protective layer and a second portion The upper surface of the protective layer is coplanar. The semiconductor device according to item 1 of the scope of patent application, wherein the semiconductor device is a high electron mobility transistor (HEMT). The semiconductor device according to item 1 of the scope of patent application, wherein the gate field plate has another extension portion between the extension portion and the drain electrode and extends into the protective layer. A method for manufacturing a semiconductor device includes: forming a compound semiconductor layer on a substrate; forming a protective layer on the compound semiconductor layer; forming a source electrode, a drain electrode, and a gate through the protective layer; A gate electrode is formed on the compound semiconductor layer; and a gate field plate is formed on a portion of the protective layer between the gate electrode and the drain electrode to connect the gate electrode, wherein the gate electrode The field plate has an extension portion extending into the protection layer, wherein the extension portion and the gate electrode are separated by the protection layer. The method for manufacturing a semiconductor device according to item 10 of the application, wherein the step of forming the gate electrode and the gate field plate comprises: forming a first recess and a second recess in the protective layer, wherein the A second recess is interposed between the first recess and the drain electrode; forming a conductive material layer on the protective layer to fill the first recess and the second recess; and patterning the conductive material layer to form The gate electrode fills the first recess and the gate field plate connects the gate electrode and fills the second recess. The method for manufacturing a semiconductor device according to item 11 of the application, wherein the compound semiconductor layer is exposed by the first depression, and the compound semiconductor layer is not exposed by the second depression. The method for manufacturing a semiconductor device according to item 12 of the application, wherein the forming of the protective layer includes: depositing a first protective layer on the compound semiconductor layer; and depositing a second protective layer on the first protective layer. Layer, wherein the material of the first protective layer is different from the material of the second protective layer. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, wherein the step of forming the first recess and the second recess includes: forming a first patterned masking layer on the protective layer; A first opening of a patterned masking layer etches the protection layer to form the first recess to expose the compound semiconductor layer; remove the first patterned masking layer; and form a second layer on the protection layer Patterning the mask layer; etching the protective layer through a second opening of the second patterned mask layer to form the second recess in the protective layer without exposing the compound semiconductor layer; and removing the compound semiconductor layer; and A second patterned masking layer. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising: after forming the compound semiconductor layer and before forming the protective layer, forming a doped compound semiconductor block, wherein the gate electrode Formed on the doped compound semiconductor block. The method for manufacturing a semiconductor device according to item 15 of the scope of patent application, wherein the forming of the protective layer includes: depositing a first protective layer on the compound semiconductor layer to conformably cover the doped compound semiconductor block. A sidewall and an upper surface; and depositing a second protective layer on the first protective layer, wherein a material of the first protective layer is different from a material of the second protective layer. The method for manufacturing a semiconductor device according to item 16 of the scope of patent application, further comprising: after forming the second protective layer, performing a planarization process to remove the second protective layer located in the doped compound semiconductor block A portion directly above, so that a horizontal portion of the first protective layer directly above the doped compound semiconductor block is exposed. The method for manufacturing a semiconductor device according to item 17 of the patent application, wherein the step of forming the first recess and the second recess includes: after the planarization process, after the first protective layer and the second protective layer A third patterned masking layer is formed thereon; the horizontal portion of the first protective layer is etched through a third opening of the third patterned masking layer to form the first recess to expose the doped compound Semiconductor block; etching the second protective layer and the first protective layer through a fourth opening of the third patterned masking layer to form the second recess in the first protective layer and the second protective layer And the compound semiconductor layer is not exposed; and the third patterned mask layer is removed. The method for manufacturing a semiconductor device according to item 11 of the application, wherein the step of forming the first recess and the second recess further includes forming a third recess between the second recess and the drain electrode; wherein The conductive material layer further fills the third depression; after the conductive material layer is etched, the gate field plate has another extension to fill the third depression.