TWI657656B - Motor driving circuit - Google Patents

Abstract

A motor driving circuit includes a driving stage circuit, a system control circuit, a control signal generating circuit and a plurality of current zero point detectors. The driver stage circuit includes a plurality of inverters. The system control circuit provides a duty cycle signal. The control signal generating circuit generates a pulse width modulation signal according to the duty cycle signal to control the on and off of the upper arm transistor and the lower arm transistor in each inverter to provide a driving current to drive the motor. The current zero point detector detects a current flowing through a node between the upper arm transistor and the lower arm transistor in each inverter, and generates a current detection signal. The control signal generating circuit adjusts the pulse width modulation signal according to the current detection signal to avoid shortening the equivalent duty cycle of the driving stage circuit, so as to maintain the integrity of the driving current waveform and prevent the waveform of the driving current from being distorted.

Description

Motor drive circuit

The present invention relates to a motor driving circuit, in particular to a motor driving circuit capable of compensating for a dead time (or dead time; Dead Time).

Generally, in a motor drive circuit, a system control circuit generates a duty cycle signal PWM (usually a pulse width modulation signal), and then a control signal generation circuit generates a control signal based on the pulse width modulation signal (usually also (Pulse width modulation signal) to control the on and off of the upper and lower arm transistors in each inverter in the driver stage circuit.

Please refer to FIG. 1. FIG. 1 can be regarded as two inverters in a driving stage circuit of a single-phase motor and two inverters in a driving stage circuit of a three-phase motor. Considering that the transistor will have a transition time from on to off or from off to on, in order to avoid the upper current transistor U, X and V, Y in each inverter in Figure 1 from being turned on at the same time, the circuit will be burned by high current. In the case that the control signal generating circuit generates the pulse width modulation signals for controlling the transistors U, X and V, Y, it will cause the pulse width modulation of the U, V and X, Y pulses to be provided to the upper and lower arm transistors. The change signal is a complementary signal, and the transition edge of the pulse width modulation signal of the upper and lower arm transistors U, V and X, Y is delayed for a period of time. Generally speaking, this delay time is called dead time (or dead time; Dead Time).

Please refer to FIG. 2A and FIG. 2B. FIG. 2A and FIG. 2B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in FIG. 1 when the motor is driven. In FIGS. 2A and 2B, the pulse width modulation signals u and x are the pulse width modulation signals provided to the upper arm transistor U and the lower arm transistor X, respectively.

As shown in FIG. 2A and FIG. 2B, the pulse width modulation signals u and x provided to the upper arm transistor U and the lower arm transistor X are delayed by a dwell time Td at their upper edges, and the upper arm transistors U and X are turned on in turn. Lower arm transistor X. When the motor is driven, the voltage VUO of the node UO during the current flowing from the node UO to the coil is shown in FIG. 2A, and the voltage VUO of the node UO during the current flowing from the coil to the node UO is shown in FIG. 2B . It should be noted that, in FIG. 2A, Vd is the on-state voltage of the body diode of the lower arm transistor X, and in FIG. 2B, Vd is the on-state voltage of the body diode of the upper arm transistor U, and in FIG. 2A As shown in FIG. 2B, VDD is the supply voltage of the inverters, which is not described here.

Assume that the duty cycle signal PWM generated by the system control circuit has a period T and its on time is Ton. From the voltage VUO of the node UO in FIG. 2A, it can be known that when the motor is driven, the current flows from the node UO to the coil. The equivalent duty cycle of the driver stage circuit is (Ton-Td) / T. In addition, it can be seen from the voltage VUO of the node UO in FIG. 2B that when the motor is driven, during the period when the current flows from the coil to the node UO, the driver stage circuit The equivalent liability period is (Ton + Td) / T.

For example, in Figure 1, suppose current flows from the node UO to the coil, and flows into the node VO through the coil, and the duty cycle of the node UO is D1%, and the duty cycle of the node VO is D2%, then the coil current is based on Equivalent liability period (D1-D2)%. In this case, if the equivalent duty cycle caused by the dead time Td is Td%, when the motor is driven, the equivalent duty cycle of the coil current generated by the drive stage circuit is (D1% -Td%)-[D2 % + Td%], which is [(D1-D2) -2Td]%.

According to this, it can be known that the method of delaying the transition edge of the pulse width modulation signal of the upper and lower arm transistors for a period of dwell time prevents the situation that the upper and lower arm transistors in the inverters are turned on at the same time, but it will cause the driver stage circuit. Due to the stagnation time of this period, the equivalent duty cycle of the inverter differs from the design value, which causes distortion of the driving current waveform.

In order to prevent the upper and lower arm transistors in the driver stage circuit from being turned on at the same time, and to maintain the integrity of the waveform of the drive current, so that the waveform of the drive current will not be distorted, the invention provides an equivalent duty cycle of the driver stage circuit. Motor drive circuit shortened due to dead time.

The motor driving circuit provided by the present invention is used to provide a driving current to drive a motor. The motor driving circuit includes a driving stage circuit, a system control circuit, a control signal generating circuit and a plurality of current zero point detectors. The driving stage circuit includes a plurality of inverters connected in parallel, and the inverters respectively include an upper arm transistor and a lower arm transistor. The system control circuit is used to provide the duty cycle signal. The control signal generating circuit is connected between the system control circuit and the driver stage circuit, and is used to generate a plurality of pulse width modulation signals according to the duty cycle signal to control the on and off of the upper arm transistor and the lower arm transistor in each inverter. To provide drive current to drive the motor. A plurality of current zero detectors are respectively connected between the driving stage circuit and the control signal generating circuit, and are used to detect the current flowing through a node between the upper arm transistor and the lower arm transistor in each inverter, and according to To generate a current detection signal.

In an embodiment of the motor driving circuit provided by the present invention, if the current detection signal generated by one of the current zero point detectors is indicated in the inverter corresponding to the current zero point detector, the current flows out of its upper arm. The node between the transistor and the lower arm transistor, the control signal generation circuit will provide the upper edge of the pulse width modulation signal of the upper arm transistor in the inverter and the lower edge of the pulse width modulation signal of the lower arm transistor. The fate advances by a time period. On the other hand, if the current detection signal generated by one of the current zero detectors indicates that the current in the inverter corresponding to the current zero detector flows into the node between the upper arm transistor and the lower arm transistor , The control signal generating circuit advances the lower edge of the pulse width modulation signal of the upper arm transistor and the upper edge of the pulse width modulation signal of the lower arm transistor by one time period in each of the inverters.

In general, the main feature of the motor driving circuit provided by the present invention is that the control signal generating circuit adjusts the pulse width modulation signals generated by the control signal generating circuit according to the current detection signals, so that the driving stage circuit The equivalent liability period will not be The stagnation time of the motor driving circuit is shortened to maintain the integrity of the waveform of the driving current so that the waveform of the driving current will not be distorted.

12‧‧‧Driver circuit

14‧‧‧system control circuit

16‧‧‧Control signal generating circuit

18a, 18b‧‧‧Current zero point detector

x, y, u, v‧‧‧ pulse width modulation signal

U, V‧‧‧ Upper Arm Transistor

X, Y‧‧‧ lower arm transistor

INV1, INV2‧‧‧ inverter

U0, V0‧‧‧node

Iu, Iv‧‧‧ current detection signal

IU0, IV0‧‧‧ current

VUO‧‧‧Voltage

PWM‧‧‧Responsibility cycle signal

T‧‧‧cycle

Ton‧‧‧on time

Td‧‧‧Stagnation time

Vd‧‧‧on voltage

VDD‧‧‧ supply voltage

Tri‧‧‧ Preset Triangle Wave

TriL, TriH‧‧‧ Adjusted preset triangle wave

FIG. 1 is a schematic diagram of a driving stage circuit of a general motor driving circuit.

2A and 2B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the driving stage circuit of FIG. 1 when the motor is driven.

FIG. 3 is a block diagram of a motor driving circuit according to an exemplary embodiment of the present invention.

4A and 4B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the motor driving circuit of FIG. 3 when the motor is driven.

5A and 5B show how the control signal generating circuit in the motor driving circuit of FIG. 3 adjusts the upper and lower edges of the pulse width modulation signal generated by the control signal generating circuit according to the current detection signal.

FIG. 6 is a waveform diagram of the motor driving circuit during operation according to an exemplary embodiment of the present invention.

FIG. 7A is a simulation result of a current IUO and a current detection signal Iu during operation according to a general motor driving circuit, and FIG. 7B is a current IUO and a current detection signal Iu during operation of a motor driving circuit according to an exemplary embodiment of the present invention Simulation results.

Generally speaking, the motor driving circuit provided by the present invention is characterized in that the use of dead time (or dead time; Dead Time) to avoid the upper and lower arm transistors in the driving stage circuit at the same time, the equivalent of the driving stage circuit The duty cycle will not be shortened because of the dead time, in order to maintain the integrity of the driving current waveform, so that the driving current waveform will not be distorted.

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, the inventive concept may It is embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, similar numbers always indicate similar elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first element or component discussed below can be referred to as the second element or component without departing from the teachings of the present invention.

Please refer to FIG. 3, which is a block diagram of a motor driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the motor driving circuit provided in this embodiment includes a driving stage circuit 12, a system control circuit 14, a control signal generating circuit 16 and a plurality of current zero point detectors 18a and 18b. The driving stage circuit 12 includes a plurality of inverters INV1 and INV2 connected in parallel. The inverter INV1 is composed of an upper arm transistor U and a lower arm transistor X, and the inverter INV2 is composed of an upper arm transistor V and a lower arm transistor Y. composition. The system control circuit 14 is used to provide a duty cycle signal PWM. The control signal generating circuit 16 is connected between the system control circuit 14 and the driving stage circuit 12 for generating a plurality of pulse width modulation signals u, x, v, and y to control the upper arm of the inverter INV1 according to the duty cycle signal PWM. The transistor U and the lower arm transistor X are turned on and off, and the upper arm transistor V and the lower arm transistor Y are turned on and off in the inverter INV2, thereby providing a driving current to the coil to drive the motor.

It should be noted that the motor driving circuit provided in this embodiment may be a single-phase motor or a three-phase motor. Therefore, although the driving stage circuit 12 in FIG. 3 only shows two inverters INV1 and INV2, the present invention is not limited to be applied to a single-phase motor. To facilitate understanding, in this embodiment, the motor driven by the motor driving circuit is a single-phase motor as an example. Therefore, the control signal generating circuit 16 generates four pulse width modulation signals u, x, v, and y to control two Inverters INV1 and INV2. In other embodiments, the motor is driven The motor driven by the circuit can also be a three-phase motor. In this case, the control signal generating circuit 16 will generate six PWM signals to control three inverters.

The working principle of the motor driving circuit provided in this embodiment is roughly as follows.

Current zero detectors 18a and 18b are respectively connected between the driving stage circuit 12 and the control signal generating circuit 16 to detect the upper arm transistors U, V and the lower arm transistors in the inverters INV1 and INV2, respectively. The currents IUO and IVO at a node between X and Y are used to generate current detection signals Iu and Iv. In the case of inverter INV1, when the current IUO detected by the current zero detector 18a is a positive value, it means that the current IUO flows out of the node in the inverter INV1 corresponding to the current zero detector 18a. UO, so the current zero detector 18a will generate a low-level current detection signal Iu. Conversely, when the current IUO detected by the current zero detector 18a is negative, it means that the current IUO in the inverter INV1 corresponding to the current zero detector 18a flows into the node UO at this time, and the current zero The detector 18a will generate a high-potential current detection signal Iu.

Then, the control signal generating circuit 16 adjusts the pulse width modulation signals u and x generated by the current detection signal Iu. The purpose of the control signal generating circuit 16 is to adjust the pulse width modulation signals u and x generated by the current detection signal Iu in order to prevent the equivalent duty cycle of the driving stage circuit 12 from being shortened by the dead time. Maintain the integrity of the waveform of the driving current so that the waveform of the driving current will not be distorted.

In the following description, in the motor driving circuit provided in this embodiment, it will be further explained how the control signal generating circuit 16 adjusts the pulse width modulation signal generated by the control signal generating circuit 16 according to the current detection signal, so that the driving stage circuit The equivalent liability period of 12 will not be shortened by the dead time. For ease of description, in the following description, only the inverter INV1 will be described. Those with ordinary knowledge in the field to which the present invention pertains should be able to infer the operation of other inverters during the operation of the motor.

4A and 4B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the motor driving circuit of FIG. 3 when the motor is driven.

Please refer to FIG. 2A and FIG. 4A at the same time. In this embodiment, when the current zero point detector 18a generates a low-level current detection signal Iu, it means that it is in the inverter INV1 at this time. The current IUO flows out of the node UO. At this time, in order to improve the equivalent duty cycle of the driver stage circuit in FIG. 2A to (Ton-Td) / T, as shown in FIG. 4A, the control signal generating circuit 16 will provide the reverse phase The upper edge of the pulse width modulation signal u of the upper arm transistor U and the lower edge of the pulse width modulation signal x of the lower arm transistor X in the inverter INV1 are advanced by a period of time each (ie, compared to FIG. 2A, FIG. 4A The upper edge of the pulse width modulation signal u of the upper middle transistor U and the lower edge of the pulse width modulation signal x of the lower arm transistor X are advanced by a time period). In this way, the time period when the node UO is at a high potential will be equal to the on-time Ton of the duty cycle signal PWM. Therefore, the equivalent duty cycle of the driver stage circuit 12 will be equal to Ton / T instead of (Ton-Td ) / T.

On the other hand, when the current zero detector 18a generates a high-potential current detection signal Iu, it means that the current IUO in the inverter INV1 flows into the node UO at this time. When the duty cycle is (Ton + Td) / T, as shown in FIG. 4B, the control signal generating circuit 16 will provide the lower edge of the pulse width modulation signal u of the upper arm transistor U in the inverter INV1. And the upper edge of the pulse width modulation signal x of the lower arm transistor X is advanced by a time period (ie, compared to FIG. 2B, the lower edge of the pulse width modulation signal u of the upper arm transistor U and the lower arm in FIG. 4B The upper edge of the pulse width modulation signal x of the transistor X is advanced by a time period). In this way, the time period when the node UO is at a high potential will be equal to the on-time Ton of the duty cycle signal PWM, so the equivalent duty cycle of the driver stage circuit 12 will be equal to Ton / T instead of (Ton + Td ) / T.

In other words, through the aforementioned adjustment of the pulse width modulation signals u and x, for the motor driving circuit provided in this embodiment, the equivalent duty cycle of the driving stage circuit 12 has no relationship with the dead time Td of the motor driving circuit. The equivalent duty cycle of the driving stage circuit 12 will not be shortened by the existence of the dead time Td.

It is worth noting that, in this embodiment, when the current zero detector 18a generates a low-potential current detection signal Iu, the upper edge of the pulse width modulation signal u of the upper arm transistor U in the inverter INV1 and The period in which the lower edge of the pulse width modulation signal x of the lower arm transistor X is advanced is designed to be equal to the dead time Td of the motor drive circuit. In addition, when the current zero point detector 18a generates a high-level current detection signal Iu, The time period between the lower edge of the pulse width modulation signal u of the arm transistor U and the upper edge of the pulse width modulation signal x of the lower arm transistor X is designed to be equal to the dead time Td of the motor drive circuit. In this way, the influence of the dead time Td on the equivalent duty cycle of the driving stage circuit 12 can be effectively eliminated.

Next, how the control signal generating circuit 16 in the motor driving circuit provided in this embodiment adjusts the upper and lower edges of the PWM signal generated by the current detection signal will be described.

In this embodiment, the PWM signal provided to the inverters by the control signal generating circuit 16 is generated based on the duty cycle signal PWM provided by the system control circuit 14 and using a preset triangle wave.

Please refer to FIG. 5A. When the current detection signal Iu generated by the current zero detector 18a indicates the current flowing out of the node UO in the inverter INV1, in order to provide the pulse width of the upper arm transistor U in the inverter INV1 The upper edge of the modulation signal u and the lower edge of the pulse width modulation signal x of the lower arm transistor X are each advanced by a dead time Td, and the control signal generating circuit 16 will adjust the preset triangular wave Tri downward to a preset level. To generate an adjusted preset triangle wave TriL. In FIG. 5A, the pulse width modulation signal u generated by the duty cycle signal PWM and the preset triangle wave Tri is the pulse width modulation signal u shown in FIG. 4A, and according to the duty cycle signal PWM and the adjusted prediction signal u, It is assumed that the pulse width modulation signal x generated by the triangular wave TriL is the pulse width modulation signal x shown in FIG. 4A. In this way, it is possible to advance the upper edge of the pulse width modulation signal u of the upper arm transistor U and the lower edge of the pulse width modulation signal x of the lower arm transistor X to the inverter INV1 by a dead time. Td, so that the equivalent duty cycle of the driving stage circuit 12 is equal to Ton / T, but not equal to (Ton-Td) / T.

On the other hand, please refer to FIG. 5B. When the current detection signal Iu generated by the current zero detector 18a indicates that the current flows into the node UO in the inverter INV1, in order to provide the upper arm transistor in the inverter INV1 The lower edge of the pulse width modulation signal u of U and the upper edge of the pulse width modulation signal x of the lower arm transistor X are each advanced by a dead time Td, and the control signal generating circuit 16 will adjust the preset triangular wave Tri upward by a predetermined time. Set the level to produce An adjusted preset triangle wave TriH. In FIG. 5B, the pulse width modulation signal x generated by the duty cycle signal PWM and the preset triangle wave Tri is the pulse width modulation signal x shown in FIG. 4B, and according to the duty cycle signal PWM and the adjusted prediction signal, Let the pulse width modulation signal u generated by the triangular wave TriH be the pulse width modulation signal u shown in FIG. 4B. In this way, it is possible to advance the lower edge of the pulse width modulation signal u of the upper arm transistor U and the upper edge of the pulse width modulation signal x of the lower arm transistor X to the inverter INV1 by a dead time. Td, so that the equivalent duty cycle of the driving stage circuit 12 is equal to Ton / T, but not equal to (Ton + Td) / T.

It should be noted that in the aforementioned adjustment mechanism for the preset triangle wave, the preset level is related to the dead time Td of the motor drive circuit. In this way, the equivalent of the dead time Td to the drive stage circuit 12 can be effectively eliminated. Impact of the duty cycle.

In general, the operation mechanism of the motor driving circuit provided in this embodiment can be referred to FIG. 6. FIG. 6 is a waveform diagram of the motor driving circuit during operation according to an exemplary embodiment of the present invention. It can be concluded from FIG. 6 that when the current IUO detected by the current zero detector 18a is a positive value, the control signal generating circuit 16 will adjust the preset triangular wave Tri downward to a preset level to obtain an adjusted value. The preset triangle wave TriL. Then, according to the duty cycle signal PWM, the preset triangle wave Tri and the adjusted preset triangle wave TriL, the pulse width modulation signals u and x provided to the upper arm transistor U and the lower arm transistor X of the inverter INV1 are generated, respectively. . On the other hand, when the current IUO detected by the current zero point detector 18a is negative, the control signal generating circuit 16 will adjust the preset triangular wave Tri up to a preset level to obtain the adjusted preset triangular wave. TriH. Then, according to the duty cycle signal PWM, the preset triangle wave Tri and the adjusted preset triangle wave TriH, the pulse width modulation signals u and x provided to the upper arm transistor U and the lower arm transistor X of the inverter INV1 are generated, respectively. .

[Possible effect of the embodiment]

According to the foregoing description, in the motor driving circuit provided by the present invention, the control signal generating circuit adjusts the pulse width modulation signals that it is to provide to the driving stage circuit according to the current detection signal to avoid the driving stage circuit 12 The equivalent liability period is stopped The lag time is shortened. In this way, the integrity of the waveform of the driving current can be maintained, so that the waveform of the driving current will not be distorted.

Because in the present invention, the equivalent duty cycle of the driving stage circuit 12 will not be shortened by the dead time, the waveform of the driving current (such as the current IUO) provided to the coil will not be distorted.

Please refer to FIG. 7A and FIG. 7B at the same time. FIG. 7A is a simulation result of the current IUO and the current detection signal Iu when the general motor driving circuit is operating, and FIG. 7B is the operation of the motor driving circuit according to an exemplary embodiment of the present invention. Simulation results of current IUO and current detection signal Iu. As shown in FIG. 7B, since the motor driving circuit provided by the present invention has a mechanism for adjusting the pulse width modulation signals that it is to provide to the driving stage circuit according to the current detection signal, when the present invention provides When the motor driving circuit is operating, at the zero crossing point of the current IUO (that is, when the current detection signal changes from a positive value to a negative value or from a negative value to a positive value), the waveform integrity of the current IUO can be maintained. In comparison, as shown in FIG. 7A, since a general motor driving circuit does not have a mechanism for adjusting the pulse width modulation signals it needs to provide to the driving stage circuit according to the current detection signal, when it is operating, At the zero crossing point of the current IUO (that is, when the current detection signal changes from a positive value to a negative value or from a negative value to a positive value), the waveform integrity of the current IUO cannot be achieved.

Finally, it must be noted that, in the foregoing description, although the concept of the technology of the present invention has been specifically shown and described with a number of exemplary embodiments, those having ordinary knowledge in the field of this technology will understand that Various changes in form and detail may be made without departing from the scope of the concept of the technology of the present invention as defined by the following patent application scope.

Claims (9)

A motor driving circuit for providing a driving current to drive a motor includes: a driving stage circuit including a plurality of inverters connected in parallel, wherein the inverters respectively include an upper arm transistor and a lower arm transistor; A system control circuit for providing a duty cycle signal; a control signal generating circuit connected between the system control circuit and the driver stage circuit for generating a plurality of pulse widths according to the duty cycle signal and a preset triangle wave Modulating signals to control the on and off of the upper arm transistor and the lower arm transistor in each of the inverters to provide the driving current to drive the motor; and a plurality of current zero detectors connected to the driver respectively A stage circuit and the control signal generating circuit, respectively, for detecting a current flowing through a node between the upper arm transistor and the lower arm transistor in each inverter, and generating a current detection signal; The control signal generating circuit adjusts the pulse width modulation signals generated by the control signal generating circuit according to the current detection signals, so as to make the equivalent responsibility of the driving stage circuit. Dead time period is not related to the motor driving circuit, thereby preventing the waveform distortion of the driving current. The motor driving circuit according to claim 1, wherein if the current detection signal generated by one of the current zero point detectors indicates that the current flows out of the inverter corresponding to the current zero point detectors Node, the control signal generating circuit advances the upper edge of the PWM signal of the upper arm transistor and the lower edge of the PWM signal of the lower arm transistor by one Time period, and the time period is equal to the dead time of the motor driving circuit. The motor driving circuit according to claim 1, wherein if the current detection signal generated by one of the current zero point detectors indicates that the current flows into the inverter corresponding to the current zero point detector Node, the control signal generating circuit advances the lower edge of the PWM signal of the upper arm transistor and the upper edge of the PWM signal of the lower arm transistor by one each. Time period, and the time period is equal to the dead time of the motor driving circuit. The motor driving circuit according to claim 1, wherein when the current detection signal generated by one of the current zero point detectors indicates that the current flows out of the inverter corresponding to the current zero point detectors At the node, the control signal generating circuit adjusts the preset triangle wave downward to a preset level, and generates the pulse width modulation signal according to the duty cycle signal and the adjusted preset triangle wave. The motor driving circuit according to claim 1, wherein when the current detection signal generated by one of the current zero point detectors indicates that the current flows into the inverter corresponding to the current zero point detectors At the node, the control signal generating circuit adjusts the preset triangle wave upward by a preset level, and generates the pulse width modulation signal according to the duty cycle signal and the adjusted preset triangle wave. The motor driving circuit according to claim 4 or 5, wherein the preset level is related to a dead time of the motor driving circuit. The motor driving circuit according to claim 1, wherein the motor driven by the motor driving circuit is a single-phase motor or a three-phase motor. The motor driving circuit according to claim 4, wherein when the motor driven by the motor driving circuit is a single-phase motor, the control signal generating circuit generates four PWM signals to control two inverters. The motor driving circuit according to claim 4, wherein when the motor driven by the motor driving circuit is a three-phase motor, the control signal generating circuit generates six pulse width modulation signals to control three inverters.