TWI651764B - Devices and methods for forming cross coupled contacts - Google Patents

Devices and methods for forming cross coupled contacts Download PDF

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TWI651764B
TWI651764B TW106112178A TW106112178A TWI651764B TW I651764 B TWI651764 B TW I651764B TW 106112178 A TW106112178 A TW 106112178A TW 106112178 A TW106112178 A TW 106112178A TW I651764 B TWI651764 B TW I651764B
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layer
via opening
semiconductor device
hard mask
opening
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TW106112178A
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TW201802880A (en
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古拉梅 伯奇
傑森 伊葛尼 史蒂芬
尼歐 特尼 古哈
孫鍇
戴茲 伊莉莎白 希瓦依
大衛 查爾斯 普理查
安迪 韋
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格羅方德半導體公司
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Abstract

本發明揭示通過針對交叉耦接拾取(pick-up)圖案化而具有交叉耦接接觸之半導體裝置以及製造該半導體裝置之方法。一種方法包括例如：獲得中間半導體裝置；執行第一光刻，以圖案化第一形狀；執行第二光刻，以圖案化與該第一形狀的部分重疊的第二形狀；處理該第一形狀及該第二形狀，以在該重疊處形成隔離區；以及形成由該隔離區分離的四個區域。本發明還揭露一種中間半導體裝置。 A semiconductor device having a cross-coupled contact for cross-coupled pick-up patterning and a method of fabricating the same are disclosed. A method includes, for example: obtaining an intermediate semiconductor device; performing a first photolithography to pattern a first shape; performing a second photolithography to pattern a second shape that overlaps a portion of the first shape; processing the first shape And the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. The present invention also discloses an intermediate semiconductor device.

Description

用以形成交叉耦接接觸之裝置及方法 Apparatus and method for forming a cross-coupled contact

本發明關於半導體裝置、製造半導體裝置的方法，以及通過有限數目的光刻曝光步驟圖案化鄰近形狀的方法，尤其關於針對交叉耦接拾取進行源汲圖案化的方法及裝置。 The present invention relates to semiconductor devices, methods of fabricating semiconductor devices, and methods of patterning adjacent shapes by a limited number of lithographic exposure steps, particularly with respect to methods and apparatus for source 汲 patterning for cross-coupled pick-up.

隨著半導體裝置不斷縮小尺寸，該些裝置的尺寸持續縮小。對於較小的裝置，組件需要縮小尺寸且被設置得彼此更加靠近。為了將接觸設置得彼此更加靠近，通過多個遮罩執行多重圖案化。由於多重圖案化及多個遮罩，製造半導體裝置的成本大大增加。另外，在多重圖案化製程期間，所得接觸可能最終沒有被充分電性分離，從而導致短路及缺陷增加。因此，需要新的裝置及方法以降低執行多重圖案化的成本，同時保持接觸之間的電性分離。 As semiconductor devices continue to shrink in size, the size of such devices continues to shrink. For smaller devices, the components need to be downsized and placed closer to each other. In order to bring the contacts closer to each other, multiple patterning is performed by a plurality of masks. The cost of manufacturing a semiconductor device is greatly increased due to multiple patterning and multiple masks. Additionally, during the multiple patterning process, the resulting contacts may ultimately not be sufficiently electrically separated, resulting in short circuits and increased defects. Therefore, new devices and methods are needed to reduce the cost of performing multiple patterning while maintaining electrical separation between contacts.

為克服現有技術的缺點並提供額外的優點，在一個態樣中提供一種方法，該方法包括例如：獲得中間半導體裝置；執行第一光刻，以圖案化第一形狀；執行第 二光刻，以圖案化與該第一形狀的部分重疊的第二形狀；處理該第一形狀及該第二形狀，以在該重疊處形成隔離區；以及形成由該隔離區分離的四個區域。 To overcome the disadvantages of the prior art and to provide additional advantages, a method is provided in one aspect, the method comprising, for example, obtaining an intermediate semiconductor device; performing a first lithography to pattern the first shape; Photolithography to pattern a second shape overlapping the portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four separated by the isolation region region.

在另一個態樣中，一種方法包括例如：獲得中間半導體裝置；通過使用第一遮罩執行第一光刻，以形成至少一個第一過孔開口；通過使用第二遮罩執行第二光刻，以形成至少一個第二過孔開口，其中，該至少一個第二過孔開口與該至少一個第一過孔開口重疊；以及自該至少一個第一過孔開口及該至少一個第二過孔開口形成至少四個接觸。 In another aspect, a method includes, for example, obtaining an intermediate semiconductor device; performing first lithography by using a first mask to form at least one first via opening; performing second lithography by using a second mask Forming at least one second via opening, wherein the at least one second via opening overlaps the at least one first via opening; and from the at least one first via opening and the at least one second via The opening forms at least four contacts.

在又一個態樣中，提供一種中間半導體裝置，其包括例如：基板；層間介電層，沉積於該基板上；硬遮罩雙層，位於該層間介電層上；多晶矽層，位於該硬遮罩雙層上；蝕刻停止層，位於該多晶矽層上；氧化物層，位於該蝕刻停止層上；至少一個第一開口，自該中間半導體裝置的頂部表面延伸穿過該氧化物層；至少一個第二開口，自該中間半導體裝置的該頂部表面延伸穿過該氧化物層，其中，該至少一個第一開口與該至少一個第二開口重疊；以及自對準區塊，位於該至少一個第一開口與該至少一個第二開口重疊之處。 In still another aspect, an intermediate semiconductor device is provided, including, for example, a substrate; an interlayer dielectric layer deposited on the substrate; a hard mask double layer on the interlayer dielectric layer; and a polysilicon layer on the hard a masking double layer; an etch stop layer on the polysilicon layer; an oxide layer on the etch stop layer; at least one first opening extending through the oxide layer from a top surface of the intermediate semiconductor device; a second opening extending from the top surface of the intermediate semiconductor device through the oxide layer, wherein the at least one first opening overlaps the at least one second opening; and a self-aligned block located in the at least one The first opening overlaps the at least one second opening.

通過本發明的技術實現額外的特徵及優點。本發明的其它實施例及態樣在本文中作詳細說明並被視為所請求保護的發明的部分。 Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered as part of the claimed invention.

10~50‧‧‧步驟 10~50‧‧‧Steps

100~126‧‧‧步驟 100~126‧‧‧Steps

200‧‧‧中間半導體裝置、半導體裝置、裝置 200‧‧‧Intermediate semiconductor devices, semiconductor devices, devices

202‧‧‧基板 202‧‧‧Substrate

204‧‧‧層間介電層、ILD層 204‧‧‧Interlayer dielectric layer, ILD layer

206‧‧‧硬遮罩雙層、第一硬遮罩層 206‧‧‧Hard mask double layer, first hard mask layer

208‧‧‧硬遮罩雙層、第二硬遮罩層 208‧‧‧Hard mask double layer, second hard mask layer

210‧‧‧多晶矽層 210‧‧‧Polysilicon layer

212‧‧‧蝕刻停止層 212‧‧‧etch stop layer

214‧‧‧氧化物層 214‧‧‧Oxide layer

216‧‧‧第一光刻堆疊 216‧‧‧First lithography stack

218‧‧‧第一源/汲過孔圖案 218‧‧‧First source/汲 via pattern

220‧‧‧第一源/汲過孔開口、第一過孔開口、過孔開口 220‧‧‧First source/汲 via opening, first via opening, via opening

222‧‧‧第二光刻堆疊 222‧‧‧Second lithography stack

224‧‧‧第二源/汲過孔圖案 224‧‧‧Second source/汲 via pattern

226‧‧‧區域、重疊區 226‧‧‧Regional and overlapping areas

227‧‧‧凹槽 227‧‧‧ Groove

228‧‧‧第二源/汲過孔開口、過孔開口 228‧‧‧Second source/汲 via opening, via opening

230‧‧‧重疊區 230‧‧‧ overlap zone

232‧‧‧硬遮罩層 232‧‧‧hard mask layer

234‧‧‧過孔開口 234‧‧‧through opening

236‧‧‧過孔開口 236‧‧‧through opening

238‧‧‧間隙壁層、側間隙壁 238‧‧‧ clearance layer, side spacer

240‧‧‧過孔開口、第一過孔開口 240‧‧‧through opening, first through opening

242‧‧‧過孔開口、第二過孔開口 242‧‧‧via opening, second via opening

244‧‧‧自對準多晶矽區塊 244‧‧‧Self-aligned polysilicon block

246‧‧‧第一過孔開口 246‧‧‧First via opening

248‧‧‧第二過孔開口 248‧‧‧Second via opening

250‧‧‧第一源/汲接觸溝槽 250‧‧‧First source/汲 contact trench

252‧‧‧第二源/汲接觸溝槽 252‧‧‧Second source/汲 contact trench

254‧‧‧第一源/汲接觸溝槽、接觸溝槽 254‧‧‧First source/汲 contact trench, contact trench

256‧‧‧第一源/汲接觸溝槽、接觸溝槽 256‧‧‧First source/汲 contact trench, contact trench

258‧‧‧第二源/汲接觸溝槽、接觸溝槽 258‧‧‧Second source/汲 contact trench, contact trench

260‧‧‧第二源/汲接觸溝槽、接觸溝槽 260‧‧‧Second source/汲 contact trench, contact trench

262‧‧‧阻擋層 262‧‧‧Block

264‧‧‧金屬層 264‧‧‧metal layer

266‧‧‧第一源/汲接觸、接觸 266‧‧‧First source/汲 contact, contact

268‧‧‧第二源/汲接觸、接觸 268‧‧‧Second source/汲 contact, contact

270‧‧‧第一源/汲接觸、接觸 270‧‧‧First source/汲 contact, contact

272‧‧‧第二源/汲接觸、接觸 272‧‧‧Second source/汲 contact, contact

274‧‧‧自對準區塊 274‧‧‧Self-aligned block

本發明的一個或多個態樣被特別指出並在說明書的結束處的聲明中被明確稱為示例。從下面結合圖式所作的詳細說明可清楚本發明的上述及其它目的、特徵以及優點，這些圖式中：第1A圖顯示依據本發明的一個或多個態樣在半導體製程期間可使用的圖案化製程的方法的一個實施例；第1B圖顯示依據本發明的一個或多個態樣用於交叉耦接拾取的源汲圖案化的方法的一個實施例；第2圖顯示依據本發明的一個或多個態樣在中間半導體裝置上方具有至少一個光刻堆疊的積體電路的一個實施例的剖切立視圖；第3圖顯示依據本發明的一個或多個態樣在執行光刻以圖案化至少一個第一源/汲過孔以後的第2圖的半導體裝置的剖切立視圖；第4圖顯示依據本發明的一個或多個態樣在蝕刻中間半導體裝置的氧化物層以後的第3圖的半導體裝置的剖切立視圖；第5圖顯示依據本發明的一個或多個態樣在剝離第一光刻堆疊以後的第4圖的半導體裝置的三維視圖；第6圖顯示依據本發明的一個或多個態樣的第5圖的半導體裝置的剖切立視圖；第7圖顯示依據本發明的一個或多個態樣在 沉積第二光刻堆疊以後的第6圖的半導體裝置的剖切立視圖；第8圖顯示依據本發明的一個或多個態樣在執行光刻以圖案化至少一個第二源/汲過孔以後的第7圖的半導體裝置的三維視圖；第9圖顯示依據本發明的一個或多個態樣的第8圖的半導體裝置的剖切立視圖；第10圖顯示依據本發明的一個或多個態樣在執行氮化物反應離子蝕刻以後的第9圖的半導體裝置的三維視圖；第11圖顯示依據本發明的一個或多個態樣在執行氮化物濕式蝕刻以擴大該第一與第二過孔開口之間的分離以後沿線11--11的第10圖的半導體裝置的三維視圖；第12圖顯示依據本發明的一個或多個態樣在蝕刻氧化物層以後的第10圖的半導體裝置的剖切立視圖；第13圖顯示依據本發明的一個或多個態樣的第12圖的半導體裝置的三維視圖；第14圖顯示依據本發明的一個或多個態樣在剝離該第二光刻堆疊以後沿第16圖中的線14--14所作的第12圖的半導體裝置的剖切立視圖；第15圖顯示依據本發明的一個或多個態樣的第14圖的半導體裝置的三維視圖； 第16圖顯示依據本發明的一個或多個態樣在氧化矽以後的第15圖的半導體裝置的三維視圖；第17圖顯示依據本發明的一個或多個態樣沿第16圖中的線17--17所作的該半導體裝置的剖切立視圖；第18圖顯示依據本發明的一個或多個態樣在蝕刻氮化物層以後的第16圖的半導體裝置的三維視圖；第19圖顯示依據本發明的一個或多個態樣在蝕刻多晶矽層以後的第18圖的半導體裝置的剖切立視圖；第20圖顯示依據本發明的一個或多個態樣的第19圖的半導體裝置的三維視圖；第21圖顯示依據本發明的一個或多個態樣在沉積氧化物間隙壁層以後的第19圖的半導體裝置的剖切立視圖；第22圖顯示依據本發明的一個或多個態樣的第21圖的半導體裝置的三維視圖；第23圖顯示依據本發明的一個或多個態樣在該間隙壁層的受控反應離子蝕刻以後的第21圖的半導體裝置的剖切立視圖；第24圖顯示依據本發明的一個或多個態樣的第23圖的半導體裝置的三維視圖；第25圖顯示依據本發明的一個或多個態樣在執行另一個反應離子蝕刻以打穿第二硬遮罩層以後的第 23圖的半導體裝置的剖切立視圖；第26圖顯示依據本發明的一個或多個態樣的第25圖的半導體裝置的三維視圖；第27圖顯示依據本發明的一個或多個態樣在執行等向性蝕刻以移除該間隙壁層以後的第25圖的半導體裝置的剖切立視圖；第28圖顯示依據本發明的一個或多個態樣的第27圖的半導體裝置的三維視圖；第29圖顯示依據本發明的一個或多個態樣在執行另一個反應離子蝕刻以打穿阻擋層以後的第28圖的半導體裝置的三維視圖；第30圖顯示依據本發明的一個或多個態樣在蝕刻層間介電層以形成源/汲接觸溝槽以後的第29圖的半導體裝置的三維視圖；第31圖顯示依據本發明的一個或多個態樣的第30圖的半導體裝置的剖切立視圖；第32圖顯示依據本發明的一個或多個態樣在蝕刻以移除多晶矽層以後的第31圖的半導體裝置的剖切立視圖；第33圖顯示依據本發明的一個或多個態樣的第32圖的半導體裝置的三維視圖；第34圖顯示依據本發明的一個或多個態樣在沉積阻擋層並執行金屬填充製程以填充接觸以後的第33圖的半導體裝置的剖切立視圖； 第35圖顯示依據本發明的一個或多個態樣在執行平坦化以移除多餘金屬層、多餘阻擋層以及硬遮罩雙層以形成源/汲接觸以後的第34圖的半導體裝置的剖切立視圖；以及第36圖顯示依據本發明的一個或多個態樣的第35圖的半導體裝置的三維視圖。 One or more aspects of the invention are particularly pointed out and are explicitly referred to as examples in the claims at the end of the description. The above and other objects, features and advantages of the present invention will become apparent from the <RTIgt; </RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; One embodiment of a method of chemical processing; FIG. 1B shows an embodiment of a method for source 汲 patterning for cross-coupling picking in accordance with one or more aspects of the present invention; and FIG. 2 shows an embodiment in accordance with the present invention Or a plurality of aspects having a cutaway elevational view of one embodiment of an integrated circuit of at least one lithographic stack over an intermediate semiconductor device; and FIG. 3 showing lithography for patterning in accordance with one or more aspects of the present invention A cutaway elevational view of the semiconductor device of FIG. 2 after at least one first source/turn via; FIG. 4 shows a third view after etching the oxide layer of the intermediate semiconductor device in accordance with one or more aspects of the present invention A cut-away view of a semiconductor device; FIG. 5 is a three-dimensional view of the semiconductor device of FIG. 4 after stripping the first lithographic stack in accordance with one or more aspects of the present invention; FIG 6 show cut-away elevation view of a semiconductor device according to the present invention, one or more aspects of FIG. 5; FIG. 7 according to the present invention display one or more aspects in A cutaway elevational view of the semiconductor device of FIG. 6 after deposition of the second lithographic stack; and FIG. 8 illustrates after performing lithography to pattern at least one second source/via via in accordance with one or more aspects of the present invention 3D view of the semiconductor device of FIG. 7; FIG. 9 is a cross-sectional elevational view of the semiconductor device of FIG. 8 according to one or more aspects of the present invention; FIG. 10 shows one or more states according to the present invention A three-dimensional view of the semiconductor device of FIG. 9 after performing nitride reactive ion etching; FIG. 11 shows performing wet etching of nitride to expand the first and second passes in accordance with one or more aspects of the present invention. A three-dimensional view of the semiconductor device of FIG. 10 along line 11--11 after separation between the aperture openings; and a semiconductor device of FIG. 10 after etching the oxide layer in accordance with one or more aspects of the present invention FIG. 13 is a three-dimensional view of the semiconductor device of FIG. 12 in accordance with one or more aspects of the present invention; and FIG. 14 is a view showing the second light being stripped in accordance with one or more aspects of the present invention. Engraved Sectional elevation view of the semiconductor device in FIG 16, the trailing edge line 14--14 of FIG. 12 taken; and FIG. 15 show a semiconductor device according to the present invention, one or more aspects of the three-dimensional view of FIG 14; Figure 16 is a three-dimensional view of the semiconductor device of Figure 15 after oxidation of germanium in accordance with one or more aspects of the present invention; and Figure 17 is a view of the line according to Figure 16 in accordance with one or more aspects of the present invention. 17--17 is a cross-sectional elevation view of the semiconductor device; FIG. 18 is a three-dimensional view of the semiconductor device of FIG. 16 after etching the nitride layer in accordance with one or more aspects of the present invention; A cross-sectional elevational view of the semiconductor device of FIG. 18 after etching the polysilicon layer of one or more aspects of the present invention; and FIG. 20 is a three-dimensional view of the semiconductor device of FIG. 19 in accordance with one or more aspects of the present invention. 21 is a cut-away elevational view of the semiconductor device of FIG. 19 after depositing an oxide spacer layer in accordance with one or more aspects of the present invention; and FIG. 22 is a view showing one or more aspects in accordance with the present invention. 3D view of the semiconductor device of FIG. 21; FIG. 23 is a cross-sectional elevational view of the semiconductor device of FIG. 21 after controlled reactive ion etching of the spacer layer in accordance with one or more aspects of the present invention; The figure shows a three-dimensional view of the semiconductor device of Figure 23 in accordance with one or more aspects of the present invention; and Figure 25 shows another reactive ion etch performed to penetrate the second hard in accordance with one or more aspects of the present invention. After the mask layer 23 is a cutaway elevational view of the semiconductor device; FIG. 26 is a perspective view showing the semiconductor device of FIG. 25 in accordance with one or more aspects of the present invention; and FIG. 27 is a view showing one or more aspects in accordance with the present invention. A cross-sectional elevational view of the semiconductor device of FIG. 25 after the isotropic etching is performed to remove the spacer layer; and FIG. 28 is a three-dimensional view of the semiconductor device of FIG. 27 in accordance with one or more aspects of the present invention; Figure 29 is a three-dimensional view of the semiconductor device of Figure 28 after performing another reactive ion etching to break through the barrier layer in accordance with one or more aspects of the present invention; Figure 30 shows one or more in accordance with the present invention. 3D view of the semiconductor device of FIG. 29 after etching the interlayer dielectric layer to form the source/germanium contact trench; FIG. 31 is a view showing the semiconductor device of FIG. 30 according to one or more aspects of the present invention. Cutaway elevational view; Fig. 32 is a cross-sectional elevational view of the semiconductor device of Fig. 31 after etching to remove the polysilicon layer in accordance with one or more aspects of the present invention; and Fig. 33 shows a view in accordance with the present invention. A three-dimensional view of a semiconductor device of a plurality of aspects of FIG. 32; FIG. 34 shows a semiconductor device of FIG. 33 after depositing a barrier layer and performing a metal filling process to fill the contact in accordance with one or more aspects of the present invention Cutaway view; Figure 35 is a cross-sectional view of the semiconductor device of Figure 34 after performing planarization to remove excess metal layers, excess barrier layers, and hard mask bilayers to form source/germanium contacts in accordance with one or more aspects of the present invention. A cutaway view; and a 36th view showing a three dimensional view of the semiconductor device of Fig. 35 in accordance with one or more aspects of the present invention.

下面通過參照圖式中所示的非限制性例子來更加充分地解釋本發明的態樣及其特定的特徵、優點以及細節。省略對已知材料、製造工具、製程技術等的說明，以免在細節上不必要地模糊本發明。不過，應當理解，當說明本發明的實施例時，詳細說明及具體例子僅作為示例，而非限制。所屬技術領域中具有通常知識者將會從本揭露中瞭解在基礎的發明概念的精神和/或範圍內的各種替代、修改、添加和/或佈局。還要注意，下面參照圖式，為方便理解，該些圖式並非按比例繪製，其中，不同圖式中所使用的相同元件符號表示相同或類似的組件。 The aspects of the present invention, as well as the specific features, advantages and details thereof, are more fully explained by the non-limiting example illustrated in the drawings. Descriptions of known materials, manufacturing tools, process techniques, and the like are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the description of the embodiments of the present invention Various alternatives, modifications, additions and/or arrangements within the spirit and/or scope of the basic inventive concept will be apparent to those skilled in the art from this disclosure. It is also to be noted that the following drawings are not drawn to scale, and the same element symbols used in the different drawings represent the same or similar components.

一般來說，本文揭露特定半導體裝置，例如場效應電晶體(field-effect transistor；FET)，其提供相對上述的現有半導體裝置及製程的優點。有利地，本文中所揭露的半導體裝置製程提供通過使用較少的遮罩所形成的裝置以及具有較大關鍵尺寸且疊置鬆弛的裝置。 In general, certain semiconductor devices, such as field-effect transistors (FETs), are disclosed herein that provide advantages over the prior art semiconductor devices and processes described above. Advantageously, the semiconductor device process disclosed herein provides a device formed by using fewer masks and a device having a larger critical dimension and overlapping relaxation.

在一個態樣中，如第1A圖中所示，顯示在半導體製程期間可使用的圖案化製程。依據本發明的一個或 多個態樣的該圖案化製程可包括例如：獲得具有基板的半導體裝置10；執行第一光刻以圖案化第一形狀20；執行第二光刻以圖案化與第一形狀的部分重疊的第二形狀30；處理該第一形狀及該第二形狀以在該重疊處形成隔離區40；以及形成由該隔離區分離的四個區域50。該圖案化製程可為例如布林運算。該布林運算影響分別由獨立的光刻製程印刷的兩個相交的形狀。該兩個相交形狀可經處理以形成四個形狀或分支，各形狀或分支與其它形狀或分支隔離。各形狀或分支可經形成而為電性獨立。該兩個形狀之間的交點將導致沒有圖案電性分離各該形狀或分支。 In one aspect, as shown in FIG. 1A, a patterning process that can be used during semiconductor fabrication is shown. One or according to the present invention The patterning process of the plurality of aspects may include, for example, obtaining a semiconductor device 10 having a substrate; performing a first lithography to pattern the first shape 20; performing a second lithography to pattern a partial overlap with the first shape a second shape 30; processing the first shape and the second shape to form an isolation region 40 at the overlap; and forming four regions 50 separated by the isolation region. The patterning process can be, for example, a Boolean operation. The Boolean operation affects the two intersecting shapes printed by separate lithography processes. The two intersecting shapes can be processed to form four shapes or branches, each shape or branch being isolated from other shapes or branches. Each shape or branch can be formed to be electrically independent. The intersection between the two shapes will result in the absence of a pattern to electrically separate each of the shapes or branches.

在另一個態樣中，在如第1B圖中所示的一個實施例中，依據本發明的一個或多個態樣的半導體裝置形成製程可包括例如：獲得具有形成於基板上方的第一光刻堆疊的半導體裝置100；執行光刻以圖案化第一源/汲過孔開口102；沉積第二光阻堆疊104；執行另一個光刻以圖案化第二源/汲過孔開口106；執行反應離子蝕刻108；執行濕式蝕刻110；執行蝕刻以移除氧化物及第二光阻堆疊112；執行氧化114；執行至少一個蝕刻116；形成間隙壁118；執行蝕刻停止層打穿及等向性蝕刻120；執行阻擋層打穿122；蝕刻以形成源/汲接觸溝槽124；以及執行源/汲接觸金屬化126。 In another aspect, in one embodiment as shown in FIG. 1B, a semiconductor device forming process in accordance with one or more aspects of the present invention can include, for example, obtaining a first light having a formation over a substrate Engraving the stacked semiconductor device 100; performing photolithography to pattern the first source/via via opening 102; depositing the second photoresist stack 104; performing another photolithography to pattern the second source/via via opening 106; performing Reactive ion etching 108; performing wet etching 110; performing etching to remove oxide and second photoresist stack 112; performing oxidation 114; performing at least one etching 116; forming spacers 118; performing etch stop layer puncture and isotropic Etching 120; performing a barrier puncture 122; etching to form source/germanium contact trenches 124; and performing source/germanium contact metallization 126.

第2至36圖顯示(僅示例)依據本發明的一個或多個態樣的第1A至1B圖的半導體裝置形成製程及中間半導體裝置200的部分的詳細實施例。再次注意，這些 圖式並非按比例繪製，以促進理解本發明，且不同圖式中所使用的相同元件符號表示相同或類似的元件。 FIGS. 2 through 36 show, by way of example only, detailed embodiments of portions of the semiconductor device forming process and intermediate semiconductor device 200 of FIGS. 1A through 1B in accordance with one or more aspects of the present invention. Note again, these The drawings are not to scale, the embodiments of the present invention

第1A至1B圖的該半導體裝置形成製程的部分的一個詳細實施例顯示(僅示例)於第2至36圖中。第2圖顯示通過該製程所獲得的半導體裝置200的部分。裝置200可包括例如基板202。在一些實施例中，基板202可具有或為基本結晶基板材料(也就是塊體矽)，而在其它實施例中，基板202可基於絕緣體上矽(silicon-on-insulator；SOI)架構或任意已知基板例如玻璃、氮化鎵(GaN)、砷化鎵(AsGa)、碳化矽(SiC)或類似物形成。 A detailed embodiment of the portion of the semiconductor device forming process of Figures 1A through 1B is shown (only examples) in Figures 2 through 36. Fig. 2 shows a portion of the semiconductor device 200 obtained by this process. Device 200 can include, for example, substrate 202. In some embodiments, substrate 202 can have or be a substantially crystalline substrate material (ie, bulk germanium), while in other embodiments, substrate 202 can be based on a silicon-on-insulator (SOI) architecture or any A substrate such as glass, gallium nitride (GaN), gallium arsenide (AsGa), tantalum carbide (SiC) or the like is known.

可依據所製造裝置200的設計通過初始製程步驟處理裝置200。例如，裝置200可包括沉積於基板202上的層間介電(interlayer dielectric；ILD)層204。ILD層204可為例如碳摻雜氧化物介電質，例如SiCOH及類似物，或這些常用介電材料的組合。裝置200也可包括硬遮罩雙層206、208，其可包括第一硬遮罩層206及第二硬遮罩層208。第一硬遮罩層206可為例如氮化矽(SiN)、氮氧化矽(SiON)、二氧化鈦(TiO2)、氮化鋁(AlN)、氮化鈦(TiN)、非晶矽(Si)層或類似物。第二硬遮罩層208可為例如TiN、SiN、SiON、TiO2、AlN層或類似物。裝置200也可包括多晶矽層210，例如非晶矽層。裝置200還可包括蝕刻停止層212，例如SiN或AlN層。在蝕刻停止層212上方可沉積氧化物層214。氧化物層214可為例如二氧 化矽(SiO2)層。最後，在氧化物層214上方可沉積第一光刻堆疊216。第一光刻堆疊216可為任意已知的光刻堆疊，例如，第一光刻堆疊216可包括旋塗硬遮罩、介電層、底部抗反射塗(bottom anti-reflection coating；BARC)層以及光阻層。該旋塗硬遮罩可為例如非晶碳膜。該介電層可為例如SiON膜。 Device 200 can be processed by an initial process step depending on the design of device 200 being fabricated. For example, device 200 can include an interlayer dielectric (ILD) layer 204 deposited on substrate 202. The ILD layer 204 can be, for example, a carbon doped oxide dielectric such as SiCOH and the like, or a combination of these commonly used dielectric materials. Device 200 can also include a hard mask bilayer 206, 208 that can include a first hard mask layer 206 and a second hard mask layer 208. The first hard mask layer 206 may be, for example, tantalum nitride (SiN), hafnium oxynitride (SiON), titanium dioxide (TiO 2 ), aluminum nitride (AlN), titanium nitride (TiN), amorphous germanium (Si). Layer or the like. The second hard mask layer 208 can be, for example, a TiN, SiN, SiON, TiO 2 , AlN layer, or the like. Device 200 can also include a polysilicon layer 210, such as an amorphous germanium layer. Device 200 may also include an etch stop layer 212, such as a SiN or AlN layer. An oxide layer 214 can be deposited over the etch stop layer 212. The oxide layer 214 can be, for example, a layer of cerium oxide (SiO 2 ). Finally, a first lithographic stack 216 can be deposited over the oxide layer 214. The first lithographic stack 216 can be any known lithographic stack. For example, the first lithographic stack 216 can include a spin-on hard mask, a dielectric layer, and a bottom anti-reflection coating (BARC) layer. And a photoresist layer. The spin-on hard mask can be, for example, an amorphous carbon film. The dielectric layer can be, for example, a SiON film.

接著，如第3圖中所示，通過使用第一遮罩可執行光刻，以圖案化第一光刻堆疊216，從而形成至少一個第一源/汲過孔圖案218。接著，可對裝置200執行蝕刻，以蝕刻至少一個第一源/汲過孔圖案218下方的氧化物層214，從而形成至少一個第一源/汲過孔開口220，如第4圖中所示。該蝕刻一旦完成，即可剝離第一光刻堆疊216，如第5及6圖中所示。接著，如第7圖中所示，在裝置200上方可沉積第二光刻堆疊222。第二光刻堆疊222可為任意已知的光刻堆疊，例如，第二光刻堆疊222可包括間隙填充及自平坦化旋塗硬遮罩、介電層、底部抗反射塗(BARC)層以及光阻層。第二光刻堆疊222的該第一層可填充至少一個第一過孔開口220。 Next, as shown in FIG. 3, the first lithographic stack 216 may be patterned by performing photolithography using the first mask, thereby forming at least one first source/turn via pattern 218. Next, an etch may be performed on the device 200 to etch the oxide layer 214 under the at least one first source/turn via pattern 218 to form at least one first source/turn via opening 220, as shown in FIG. . Once the etch is complete, the first lithographic stack 216 can be stripped as shown in Figures 5 and 6. Next, as shown in FIG. 7, a second lithographic stack 222 can be deposited over the device 200. The second lithographic stack 222 can be any known lithographic stack. For example, the second lithographic stack 222 can include a gap fill and self-flattening spin-on hard mask, a dielectric layer, and a bottom anti-reflective coating (BARC) layer. And a photoresist layer. The first layer of the second lithographic stack 222 can fill at least one first via opening 220.

接著，通過使用第二遮罩可執行光刻，以圖案化第二光刻堆疊222，從而形成至少一個第二源/汲過孔圖案224，如第8及9圖中所示。該光刻製程還可包括顯影製程以暴露區域226，該區域形成於至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224重疊之處，如第8圖中所示。重疊區226可被處理成自對準塊區， 如下面更詳細所述。區域226暴露蝕刻停止層212的部分。接著，可對裝置200執行蝕刻，以暴露重疊區226中的多晶矽層210，如第10圖中所示。該蝕刻可為例如氮化物反應離子蝕刻，其對氧化物具有選擇性，且多晶矽層210可為例如非晶矽。接著，可執行濕式蝕刻以擴大至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224之間的該分離，如第11圖中所示。該濕式蝕刻可為例如熱磷氮化物濕式蝕刻，其可蝕刻該蝕刻停止層212以形成凹槽227。該些凹槽227可擴大至少一個第一源/汲過孔開口220與至少一個第二源/汲過孔圖案224之間的該分離，以防止在由至少一個第一源/汲過孔開口220及至少一個第二源/汲過孔圖案224形成的最終源/汲接觸中的短路。接著，通過使用至少一個第二源/汲過孔圖案224可執行另一個蝕刻，以蝕刻進入氧化物層214，停止於蝕刻停止層212上並形成至少一個第二源/汲過孔開口228，如第12及13圖中所示。該濕式蝕刻及氧化物蝕刻可形成較大的重疊區230，如第13圖中所示。接著，可自裝置200剝離第二光刻堆疊222，如第14及15圖中所示。 Next, photolithography may be performed using the second mask to pattern the second lithographic stack 222 to form at least one second source/germanium via pattern 224, as shown in FIGS. 8 and 9. The lithography process can also include a development process to expose regions 226 that are formed where the at least one first source/turn via opening 220 overlaps the at least one second source/turn via pattern 224, as in FIG. Shown. The overlap region 226 can be processed into a self-aligned block region, As described in more detail below. Region 226 exposes portions of etch stop layer 212. Next, an etch may be performed on device 200 to expose polysilicon layer 210 in overlap region 226, as shown in FIG. The etch can be, for example, a nitride reactive ion etch that is selective to the oxide, and the polysilicon layer 210 can be, for example, an amorphous germanium. Next, a wet etch may be performed to expand the separation between the at least one first source/turn via opening 220 and the at least one second source/turn via pattern 224, as shown in FIG. The wet etch can be, for example, a thermal phosphoritride wet etch that can etch the etch stop layer 212 to form the recess 227. The recesses 227 may expand the separation between the at least one first source/turn via opening 220 and the at least one second source/turn via pattern 224 to prevent opening in the at least one first source/turn via A short circuit in the final source/deuterium contact formed by 220 and at least one second source/turn via pattern 224. Next, another etch can be performed by using at least one second source/germanium via pattern 224 to etch into the oxide layer 214, stop on the etch stop layer 212 and form at least one second source/via via opening 228, As shown in Figures 12 and 13. The wet etch and oxide etch can form a larger overlap region 230, as shown in FIG. Next, the second lithographic stack 222 can be stripped from the device 200, as shown in Figures 14 and 15.

或者，在執行該氮化物反應離子蝕刻以移除蝕刻停止層212的該未覆蓋部分以後，可執行另一個蝕刻，以向下移除氧化物214的部分至蝕刻停止層212，從而形成至少一個第二源/汲過孔開口228。接著，可自裝置200剝離第二光刻堆疊222。在剝離第二光刻堆疊222以後，可執行濕式蝕刻，以擴大過孔開口220、228之間的該 分離。該濕式蝕刻可為例如熱磷氮化物濕式蝕刻，其蝕刻該蝕刻停止層212，以形成凹槽227。 Alternatively, after performing the nitride reactive ion etching to remove the uncovered portion of the etch stop layer 212, another etch may be performed to remove portions of the oxide 214 down to the etch stop layer 212 to form at least one A second source/turn via opening 228. Next, the second lithographic stack 222 can be stripped from the device 200. After stripping the second lithographic stack 222, a wet etch may be performed to enlarge the between the via openings 220, 228 Separation. The wet etch can be, for example, a thermal phosphoritride wet etch that etches the etch stop layer 212 to form the recess 227.

現在請參照第14、16及17圖，可對裝置200執行氧化。該氧化可為例如矽選擇性氧化，以在重疊區230上方形成硬遮罩層232，從而形成非晶矽自對準區塊，如第17圖中所示。硬遮罩層232可為例如氧化物層。也考慮硬遮罩層232可通過使用矽化、磊晶或間隙壁插塞形成，如所屬技術領域中具有通常知識者所已知。接著，可執行另一個蝕刻，以自過孔開口220、228移除蝕刻停止層212，從而暴露多晶矽層210，如第18圖中所示。 Referring now to Figures 14, 16 and 17, oxidation of device 200 can be performed. The oxidation can be, for example, ruthenium selective oxidation to form a hard mask layer 232 over the overlap region 230 to form an amorphous germanium self-aligned block, as shown in FIG. Hard mask layer 232 can be, for example, an oxide layer. It is also contemplated that the hard mask layer 232 can be formed by using deuterated, epitaxial or interstitial plugs, as is known to those of ordinary skill in the art. Next, another etch may be performed to remove the etch stop layer 212 from the via openings 220, 228 to expose the polysilicon layer 210, as shown in FIG.

如第19及20圖中所示，可對裝置200執行另一個蝕刻，以移除過孔開口220、228中的多晶矽層210的部分，從而形成較深的過孔開口234、236，該些過孔開口向下延伸穿過氧化物層214、蝕刻停止層212及多晶矽層210至第二硬遮罩層208。接著，在裝置200上方可沉積間隙壁層238，包括沉積進入至少一個第一過孔開口234及至少一個第二過孔開口236中，如第21及22圖中所示。間隙壁層238可通過例如原子層沉積(atomic layer deposition；ALD)來沉積且可為例如二氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、二氧化鈦(TiO2)、非晶矽，或類似物。接著，可執行蝕刻，以移除間隙壁層238的水平部分，從而形成側間隙壁238，如第23及24圖中所示。該蝕刻可為例如反應離子蝕刻(RIE)，如受控RIE。 As shown in FIGS. 19 and 20, another etch may be performed on device 200 to remove portions of polysilicon layer 210 in via openings 220, 228 to form deep via openings 234, 236, The via opening extends downward through the oxide layer 214, the etch stop layer 212, and the polysilicon layer 210 to the second hard mask layer 208. Next, a spacer layer 238 can be deposited over the device 200, including deposition into the at least one first via opening 234 and the at least one second via opening 236, as shown in Figures 21 and 22. The spacer layer 238 may be deposited by, for example, atomic layer deposition (ALD) and may be, for example, hafnium oxide (SiO 2 ), tantalum nitride (SiN), hafnium oxynitride (SiON), or titanium dioxide (TiO 2 ). , amorphous germanium, or the like. Next, an etch may be performed to remove the horizontal portion of the spacer layer 238 to form the side spacers 238 as shown in FIGS. 23 and 24. The etch can be, for example, reactive ion etching (RIE), such as controlled RIE.

在形成側間隙壁238以後，可執行硬遮罩開 口製程，如第25至29圖中所示。首先，如第25及26圖中所示，可執行乾式蝕刻和/或短蝕刻，以打穿或移除至少一個第一過孔開口234及至少一個第二過孔開口236中的第二硬遮罩層208。接著，可執行等向性蝕刻，以移除側間隙壁238並形成過孔開口240、242，如第27及28圖中所示。該等向性蝕刻可為例如二氧化矽(SiO2)蝕刻或SiCoNiTM蝕刻。該等向性蝕刻也可蝕刻至少一個第一過孔開口240及至少一個第二過孔開口242中的氧化物層214的部分。另外，該等向性蝕刻可移除硬遮罩層232，以暴露自對準多晶矽區塊244。接著，可執行乾式蝕刻或RIE短蝕刻或打穿，以打穿第一硬遮罩層206並形成至少一個第一過孔開口246及至少一個第二過孔開口248，如第29圖中所示。該RIE短蝕刻可為例如氮化物蝕刻，其相對氧化物具有選擇性。 After the side spacers 238 are formed, a hard mask opening process can be performed as shown in FIGS. 25-29. First, as shown in FIGS. 25 and 26, dry etching and/or short etching may be performed to penetrate or remove at least one of the first via openings 234 and the second of the at least one second via openings 236. Mask layer 208. Next, an isotropic etch can be performed to remove the side spacers 238 and form via openings 240, 242 as shown in Figures 27 and 28. The isotropic etch can be, for example, a cerium oxide (SiO 2 ) etch or a SiCoNi TM etch. The isotropic etch can also etch portions of the oxide layer 214 in the at least one first via opening 240 and the at least one second via opening 242. Additionally, the isotropic etch can remove the hard mask layer 232 to expose the self-aligned polysilicon block 244. Next, dry etching or RIE short etching or puncture may be performed to penetrate the first hard mask layer 206 and form at least one first via opening 246 and at least one second via opening 248, as shown in FIG. Show. The RIE short etch can be, for example, a nitride etch that is selective to the oxide.

接著，可執行至少一個蝕刻，以形成源/汲接觸溝槽，如第30至33圖中所示。現在請參照第30及31圖，可執行蝕刻，以移除至少一個第一過孔開口246及至少一個第二過孔開口248中的ILD層204，從而形成至少一個第一源/汲接觸溝槽250及至少一個第二源/汲接觸溝槽252。該蝕刻可為例如對非晶矽具有選擇性的蝕刻。接著，如第32及33圖中所示，可執行另一個蝕刻以移除多晶矽層210，從而形成至少一個第一源/汲接觸溝槽254、256及至少一個第二源/汲接觸溝槽258、260，各接觸溝槽254、256、258、260由自對準區塊274分離。 Next, at least one etch may be performed to form source/germanium contact trenches as shown in FIGS. 30 to 33. Referring now to FIGS. 30 and 31, an etch may be performed to remove at least one first via opening 246 and at least one second via opening 248 in the ILD layer 204 to form at least one first source/germanium contact trench The slot 250 and the at least one second source/turn contact trench 252. The etch can be, for example, an etch that is selective for amorphous germanium. Next, as shown in FIGS. 32 and 33, another etch may be performed to remove the polysilicon layer 210 to form at least one first source/germanium contact trench 254, 256 and at least one second source/germanium contact trench. 258, 260, each contact trench 254, 256, 258, 260 is separated by a self-aligned block 274.

最後，可執行金屬化製程，以形成源/汲接觸，如第34至36圖中所示。該金屬化製程可包括例如在裝置200上方及接觸溝槽254、256、258、260中沉積阻擋層262，如第34圖中所示。請繼續參照第34圖，該金屬化製程也可包括例如在裝置200上方執行金屬填充，以用金屬層264填充接觸溝槽254、256、258、260。接著，如第35及36圖中所示，可執行平坦化製程，以移除多餘金屬層264、多餘阻擋層262、第二硬遮罩層208及第一硬遮罩層206，從而形成至少一個第一源/汲接觸266、270以及至少一個第二源/汲接觸268、272。該平坦化可為例如使用過蝕刻的化學機械拋光(chemical mechanical planarization；CMP)。如第36圖中所示，各接觸266、268、270、272可隔開，在各接觸266、268、270、272之間提供電性隔離。 Finally, a metallization process can be performed to form source/germanium contacts as shown in Figures 34-36. The metallization process can include depositing a barrier layer 262, for example, over device 200 and in contact trenches 254, 256, 258, 260, as shown in FIG. With continued reference to FIG. 34, the metallization process can also include performing metal fill, for example, over device 200 to fill contact trenches 254, 256, 258, 260 with metal layer 264. Next, as shown in FIGS. 35 and 36, a planarization process may be performed to remove the excess metal layer 264, the excess barrier layer 262, the second hard mask layer 208, and the first hard mask layer 206 to form at least A first source/deuterium contact 266, 270 and at least one second source/deuterium contact 268, 272. The planarization can be, for example, chemical mechanical planarization (CMP) using overetching. As shown in FIG. 36, each of the contacts 266, 268, 270, 272 can be spaced apart to provide electrical isolation between the contacts 266, 268, 270, 272.

本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制本發明。除非上下文中明確指出，否則本文中所使用的單數形式“一個”以及“該”也意圖包括複數形式。還應當理解，術語“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是開放式連接動詞。因此，“包括”、“具有”或“包含”一個或多個步驟或元件的方法或裝置具有那些一個或多個步驟或元件，但並不限於僅僅具有那些一個或多個步驟或元件。類似地，“包括”、“具有”或“包含”一個或多個特徵的一種方法的步驟或一種 裝置的元件具有那些一個或多個特徵，但並不限於僅僅具有那些一個或多個特徵。而且，以特定方式配置的裝置或結構至少以那種方式配置，但也可以未列出的方式配置。 The terminology used herein is for the purpose of describing particular embodiments, and is not intended to limit the invention. The singular forms "a" and "the" It should also be understood that the terms "comprise" (and "including", "the", "the", "the", "the", "the", "include" Thus, a method or device that "comprises", "comprising" or "comprising" one or more steps or elements has one or more steps or elements, but is not limited to having only those one or more steps or elements. Similarly, a step or a method of "including", "having" or "containing" one or more features The elements of the device have one or more of those features, but are not limited to having only those one or more features. Moreover, the devices or structures configured in a particular manner are configured at least in that manner, but may also be configured in ways that are not listed.

所述的申請專利範圍中的所有手段或步驟加功能元件的相應結構、材料、動作及均等物(如果有的話)意圖包括結合具體請求保護的其它請求保護的元件執行該功能的任意結構、材料或動作。本發明的說明用於示例及說明目的，而非意圖詳盡無遺或限於所揭露形式的發明。許多修改及變更將對於所屬技術領域中具有通常知識者顯而易見，而不背離本發明的範圍及精神。這些實施例經選擇及說明以最佳解釋本發明的一個或多個態樣的原理以及實際應用，並使本領域的其他普通技術人員能夠理解針對各種實施例具有適合所考慮的特定應用的各種變更的本發明的一個或多個態樣。 All of the means or steps, and the corresponding structures, materials, acts, and equivalents of the functional elements, if any, are intended to include any structure that performs the function in conjunction with other claimed elements specifically claimed. Material or action. The illustrations of the present invention are intended to be illustrative and illustrative, and not intended to be exhaustive or limited to the invention disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles and embodiments of the embodiments of the invention, One or more aspects of the invention that are modified.

Claims (20)

一種製造半導體裝置之方法，包括：獲得中間半導體裝置；執行第一光刻，以圖案化第一形狀而形成至少一個第一過孔開口；執行第二光刻，以圖案化第二形狀而形成至少一個第二過孔開口，其中，該第二形狀的部分與該第一形狀的部分重疊；處理該第一形狀及該第二形狀，以在該重疊處形成隔離區，該隔離區使該至少一個第一過孔開口與該至少一個第二過孔開口分離；以及在該至少一個第一過孔開口與該至少一個第二過孔開口中形成四個導電區域。 A method of fabricating a semiconductor device, comprising: obtaining an intermediate semiconductor device; performing a first photolithography to pattern a first shape to form at least one first via opening; performing a second photolithography to pattern the second shape to form At least one second via opening, wherein the portion of the second shape overlaps with the portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap, the isolation region At least one first via opening is separated from the at least one second via opening; and four conductive regions are formed in the at least one first via opening and the at least one second via opening. 如申請專利範圍第1項所述之方法，其中，該中間半導體裝置包括：基板；層間介電層，位於該基板上；硬遮罩雙層，位於該層間介電層上；多晶矽層，位於該硬遮罩雙層上；蝕刻停止層，位於該多晶矽層上；氧化物層，位於該蝕刻停止層上；以及第一光刻堆疊，位於該氧化物層上。 The method of claim 1, wherein the intermediate semiconductor device comprises: a substrate; an interlayer dielectric layer on the substrate; a hard mask double layer on the interlayer dielectric layer; and a polysilicon layer located at The hard mask is on the double layer; an etch stop layer is on the polysilicon layer; an oxide layer is on the etch stop layer; and a first lithographic stack is on the oxide layer. 如申請專利範圍第2項所述之方法，其中，執行該第一光刻以圖案化該第一形狀包括： 使用第一遮罩以形成該至少一個第一過孔開口，其中，使用該第一遮罩以形成該至少一個第一過孔開口包括：曝光該第一遮罩，以在該第一光刻堆疊中形成至少一個第一過孔圖案；蝕刻該氧化物層以形成該至少一個第一過孔開口；以及自該中間半導體裝置剝離該第一光刻堆疊。 The method of claim 2, wherein performing the first lithography to pattern the first shape comprises: Using the first mask to form the at least one first via opening, wherein using the first mask to form the at least one first via opening comprises: exposing the first mask to the first photolithography Forming at least one first via pattern in the stack; etching the oxide layer to form the at least one first via opening; and stripping the first lithographic stack from the intermediate semiconductor device. 如申請專利範圍第1項所述之方法，其中，該中間半導體裝置包括：基板；層間介電層，位於該基板上；硬遮罩雙層，位於該層間介電層上；多晶矽層，位於該硬遮罩雙層上；蝕刻停止層，位於該多晶矽層上；氧化物層，位於該蝕刻停止層上；以及第二光刻堆疊，位於該氧化物層上。 The method of claim 1, wherein the intermediate semiconductor device comprises: a substrate; an interlayer dielectric layer on the substrate; a hard mask double layer on the interlayer dielectric layer; and a polysilicon layer located at The hard mask is on the double layer; an etch stop layer is on the polysilicon layer; an oxide layer is on the etch stop layer; and a second lithography stack is on the oxide layer. 如申請專利範圍第4項所述之方法，其中，執行第二光刻以圖案化與該第一形狀的部分重疊的第二形狀包括：通過使用第二遮罩執行第二光刻，以形成該至少一個第二過孔開口，其中，該至少一個第二過孔開口與至少一個第一過孔開口重疊，其中，通過使用該第二遮罩執行該第二光刻以形成該至少一個第二過孔開口包括：曝光該第二遮罩以在該第二光刻堆疊中形成 至少一個第二過孔圖案；蝕刻該氧化物層以形成該至少一個第二過孔開口；以及自該中間半導體裝置剝離該第二光刻堆疊。 The method of claim 4, wherein performing the second lithography to pattern the second shape overlapping the portion of the first shape comprises: performing second lithography by using the second mask to form The at least one second via opening, wherein the at least one second via opening overlaps the at least one first via opening, wherein the second photolithography is performed by using the second mask to form the at least one The two via openings include: exposing the second mask to form in the second lithographic stack At least one second via pattern; etching the oxide layer to form the at least one second via opening; and stripping the second lithographic stack from the intermediate semiconductor device. 如申請專利範圍第5項所述之方法，其中，通過使用該第二遮罩執行該第二光刻以形成該至少一個第二過孔開口還包括：執行顯影製程，以暴露自對準區塊，在該自對準區塊處，該至少一個第一過孔開口與該至少一個第二過孔圖案重疊；蝕刻該中間半導體裝置，以暴露該自對準區塊的該多晶矽層；以及執行濕式蝕刻，以擴大該至少一個第一過孔開口與該至少一個第二過孔圖案之間的該分離，從而在該蝕刻停止層中形成凹槽。 The method of claim 5, wherein performing the second lithography by using the second mask to form the at least one second via opening further comprises: performing a developing process to expose the self-aligned region a block, at the first self-aligned block, the at least one first via opening overlapping the at least one second via pattern; etching the intermediate semiconductor device to expose the polysilicon layer of the self-aligned block; A wet etch is performed to expand the separation between the at least one first via opening and the at least one second via pattern to form a recess in the etch stop layer. 如申請專利範圍第6項所述之方法，其中，用以形成該凹槽的該濕式蝕刻為熱磷氮化物濕式蝕刻。 The method of claim 6, wherein the wet etching to form the recess is a thermal phosphorus nitride wet etch. 如申請專利範圍第7項所述之方法，其中，形成由該隔離區分離的四個導電區域包括：自該至少一個第一過孔開口及該至少一個第二過孔開口形成至少四個接觸，其中，形成該至少四個接觸包括：執行氧化，以在該自對準區塊上形成硬遮罩層； 執行第一蝕刻，以移除該蝕刻停止層的部分並暴露該至少一個第一過孔開口及該至少一個第二過孔開口中的該多晶矽層的部分；以及執行第二蝕刻，以移除該多晶矽層的部分並暴露該硬遮罩雙層的部分。 The method of claim 7, wherein forming the four conductive regions separated by the isolation region comprises: forming at least four contacts from the at least one first via opening and the at least one second via opening Forming the at least four contacts includes: performing oxidation to form a hard mask layer on the self-aligned block; Performing a first etch to remove portions of the etch stop layer and exposing portions of the at least one first via opening and the polysilicon layer in the at least one second via opening; and performing a second etch to remove A portion of the polysilicon layer and exposing portions of the hard mask bilayer. 如申請專利範圍第8項所述之方法，其中，自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括：在該中間半導體裝置上方沉積間隙壁層；以及蝕刻該間隙壁層，以在該至少一個第一過孔開口及該至少一個第二過孔開口中形成側間隙壁。 The method of claim 8, wherein the forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises depositing a spacer over the intermediate semiconductor device a layer; and etching the spacer layer to form a side spacer in the at least one first via opening and the at least one second via opening. 如申請專利範圍第9項所述之方法，其中，自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括：執行乾式蝕刻，以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該硬遮罩雙層的第二硬遮罩層的部分；執行等向性蝕刻，以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該側間隙壁並移除該自對準區塊上的該硬遮罩層，從而暴露自對準多晶矽區塊；以及執行蝕刻，以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該硬遮罩雙層的該第一硬遮罩層的部分。 The method of claim 9, wherein the forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises: performing a dry etch to remove the at least a first via opening and a portion of the second hard mask layer of the hard mask double layer in the at least one second via opening; performing an isotropic etching to remove the at least one first via opening And the side spacer in the at least one second via opening and removing the hard mask layer on the self-aligned block to expose the self-aligned polysilicon block; and performing etching to remove the at least a first via opening and a portion of the first hard mask layer of the hard mask double layer in the at least one second via opening. 如申請專利範圍第10項所述之方法，其中，自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括：執行蝕刻，以移除該至少一個第一過孔開口及該至少一個第二過孔開口中的該層間介電層的部分，以形成至少一個第一接觸溝槽及至少一個第二接觸溝槽；以及執行蝕刻，以自該中間半導體裝置移除該多晶矽層。 The method of claim 10, wherein the forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises: performing etching to remove the at least one a first via opening and a portion of the interlayer dielectric layer in the at least one second via opening to form at least one first contact trench and at least one second contact trench; and performing etching from the middle The semiconductor device removes the polysilicon layer. 如申請專利範圍第11項所述之方法，其中，自該至少一個第一過孔開口及該至少一個第二過孔開口形成該至少四個接觸還包括：在該中間半導體裝置上方以及該至少一個第一接觸溝槽及至少一個第二接觸溝槽中沉積阻擋層；執行金屬填充製程，以在該中間半導體裝置上以及該至少一個第一接觸溝槽及至少一個第二接觸溝槽中沉積金屬層；以及執行平坦化，以移除多餘金屬層、多餘阻擋層以及該硬遮罩雙層，從而形成至少兩個第一接觸及至少兩個第二接觸。 The method of claim 11, wherein forming the at least four contacts from the at least one first via opening and the at least one second via opening further comprises: over the intermediate semiconductor device and the at least Depositing a barrier layer in the first contact trench and the at least one second contact trench; performing a metal filling process to deposit on the intermediate semiconductor device and the at least one first contact trench and the at least one second contact trench a metal layer; and performing planarization to remove excess metal layers, excess barrier layers, and the hard mask bilayer to form at least two first contacts and at least two second contacts. 一種中間半導體裝置，包括：基板；層間介電層，沉積於該基板上；硬遮罩雙層，位於該層間介電層上；多晶矽層，位於該硬遮罩雙層上； 蝕刻停止層，位於該多晶矽層上；氧化物層，位於該蝕刻停止層上；以及至少一個第一開口，自該中間半導體裝置的頂部表面延伸穿過該氧化物層；至少一個第二開口，自該中間半導體裝置的該頂部表面延伸穿過該氧化物層，其中，該至少一個第一開口與該至少一個第二開口重疊；以及自對準區塊，位於該至少一個第一開口與該至少一個第二開口重疊之處。 An intermediate semiconductor device comprising: a substrate; an interlayer dielectric layer deposited on the substrate; a hard mask double layer on the interlayer dielectric layer; and a polysilicon layer on the double layer of the hard mask; An etch stop layer on the polysilicon layer; an oxide layer on the etch stop layer; and at least one first opening extending through the oxide layer from a top surface of the intermediate semiconductor device; at least one second opening, Extending from the top surface of the intermediate semiconductor device through the oxide layer, wherein the at least one first opening overlaps the at least one second opening; and the self-aligned block is located at the at least one first opening At least one of the second openings overlaps. 如申請專利範圍第13項所述之中間半導體裝置，其中，該自對準區塊包括：該多晶矽層的部分；以及硬遮罩層，位於該多晶矽層的該部分上。 The intermediate semiconductor device of claim 13, wherein the self-aligned block comprises: a portion of the polysilicon layer; and a hard mask layer on the portion of the polysilicon layer. 如申請專利範圍第14項所述之中間半導體裝置，其中，該蝕刻停止層凹入該至少一個第一開口及該至少一個第二開口內的該氧化物層下方。 The intermediate semiconductor device of claim 14, wherein the etch stop layer is recessed below the oxide layer in the at least one first opening and the at least one second opening. 如申請專利範圍第13項所述之中間半導體裝置，其中，該至少一個第一開口及該至少一個第二開口進一步延伸穿過該蝕刻停止層、該多晶矽層以及該硬遮罩雙層的第二硬遮罩層。 The intermediate semiconductor device of claim 13, wherein the at least one first opening and the at least one second opening further extend through the etch stop layer, the polysilicon layer, and the hard mask double layer Two hard mask layers. 如申請專利範圍第16項所述之中間半導體裝置，其中，該自對準區塊包括：該硬遮罩雙層的該第二硬遮罩層的部分；以及該硬遮罩雙層的該第二硬遮罩層的該部分上的該 多晶矽層的部分。 The intermediate semiconductor device of claim 16, wherein the self-aligned block comprises: a portion of the second hard mask layer of the hard mask double layer; and the hard mask double layer The portion of the second hard mask layer on the portion Part of the polycrystalline layer. 如申請專利範圍第13項所述之中間半導體裝置，其中，該至少一個第一開口及該至少一個第二開口進一步延伸穿過該蝕刻停止層、該多晶矽層以及該硬遮罩雙層。 The intermediate semiconductor device of claim 13, wherein the at least one first opening and the at least one second opening further extend through the etch stop layer, the polysilicon layer, and the hard mask double layer. 如申請專利範圍第18項所述之中間半導體裝置，其中，該自對準區塊包括：該硬遮罩雙層的部分；以及該硬遮罩雙層的該部分上的該多晶矽層的部分。 The intermediate semiconductor device of claim 18, wherein the self-aligned block comprises: a portion of the hard mask double layer; and a portion of the polysilicon layer on the portion of the hard mask double layer . 如申請專利範圍第13項所述之中間半導體裝置，其中，該至少一個第一開口形成延伸穿過該層間介電層的至少兩個第一接觸；其中，該至少一個第二開口形成延伸穿過該層間介電層的至少兩個第二接觸；以及其中，該自對準區塊電性分離各該至少兩個第一接觸與該至少兩個第二接觸。 The intermediate semiconductor device of claim 13, wherein the at least one first opening forms at least two first contacts extending through the interlayer dielectric layer; wherein the at least one second opening forms an extension through Passing at least two second contacts of the interlayer dielectric layer; and wherein the self-aligned block electrically separates each of the at least two first contacts from the at least two second contacts.
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11177132B2 (en) * 2019-07-03 2021-11-16 International Business Machines Corporation Self aligned block masks for implantation control
KR20220143382A (en) 2021-04-16 2022-10-25 삼성전자주식회사 Integrated circuit chip comprising a gate electrode with an oblique cut surface, and manufacturing method of the same
CN116207039B (en) * 2023-04-28 2023-07-21 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor structure and semiconductor structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110076845A1 (en) * 2009-09-29 2011-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method Of Forming An Interconnect Of A Semiconductor Device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US9230910B2 (en) * 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
KR20130096953A (en) 2012-02-23 2013-09-02 삼성전자주식회사 Method for manufacturing semiconductor device
KR101926418B1 (en) * 2012-05-16 2018-12-10 삼성전자주식회사 method for manufacturing a semiconductor device
US8987128B2 (en) * 2012-07-30 2015-03-24 Globalfoundries Inc. Cross-coupling based design using diffusion contact structures
CN103811338B (en) * 2012-11-08 2016-12-21 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor device and preparation method thereof
US8969207B2 (en) * 2013-03-13 2015-03-03 Globalfoundries Inc. Methods of forming a masking layer for patterning underlying structures
US9053279B2 (en) * 2013-03-14 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Pattern modification with a preferred position function
US9601367B2 (en) 2013-03-25 2017-03-21 International Business Machines Corporation Interconnect level structures for confining stitch-induced via structures
US9520502B2 (en) 2013-10-15 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having epitaxial capping layer on fin and methods for forming the same
US8969199B1 (en) * 2013-10-15 2015-03-03 Globalfoundries Inc. Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process
US9454631B2 (en) 2014-05-23 2016-09-27 International Business Machines Corporation Stitch-derived via structures and methods of generating the same
US9634125B2 (en) 2014-09-18 2017-04-25 United Microelectronics Corporation Fin field effect transistor device and fabrication method thereof
US9704862B2 (en) * 2014-09-18 2017-07-11 Samsung Electronics Co., Ltd. Semiconductor devices and methods for manufacturing the same
US9640533B2 (en) 2015-03-12 2017-05-02 Globalfoundries Inc. Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
US9530689B2 (en) 2015-04-13 2016-12-27 GlobalFoundries, Inc. Methods for fabricating integrated circuits using multi-patterning processes
CN106684032B (en) * 2015-11-05 2019-07-02 中芯国际集成电路制造(北京)有限公司 The forming method of interconnection structure and exposure are to Barebone

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110076845A1 (en) * 2009-09-29 2011-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method Of Forming An Interconnect Of A Semiconductor Device

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