TWI617008B - Memory structure, method of operating the same, and method of manufacturing the same - Google Patents

Abstract

A memory structure includes a plurality of stacked layers, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stacks each include a set of alternating strips and strips that alternate with one another. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed on at least a portion of the channel layer on the first side of the stack and a channel layer on a plurality of portions of the second side of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. A first wire disposed on a first side of the stack is isolated from a first wire disposed on a second side of the same stack and is isolated from a first wire disposed on a second side of the adjacent stack.

Description

Memory structure, method of operation thereof, and method of manufacturing same

The present disclosure relates to a semiconductor structure, a method of operating the same, and a method of fabricating the same. The present disclosure relates in particular to a memory structure, method of operation thereof, and method of making the same.

Researchers and engineers have tried their best to increase the density of semiconductor devices in order to reduce volume, reduce weight, increase power density, and improve portability. One such method is to replace the traditional 2D structure with a 3D structure. Another approach is to reduce the size of the components and spaces in the device. Both of these methods have their technical bottlenecks that need to be broken.

The present disclosure relates to a memory structure, and a method of operation and a method of fabricating the same, by which a memory device having a physically two-dimensional memory structure can be provided.

In accordance with some embodiments, a memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stack is placed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and plurals alternating with each other Insulation strips. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed at least on the plurality of portions of the channel layer on the first sides of the stack and the channel layer on a plurality of portions of the second sides of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires disposed on the first sides of the stacks and a second set of first wires disposed on the second sides of the stacks, disposed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires disposed on the second side of the same stack, and is disposed at One of the stacks of one of the second sets of first conductors adjacent to the second side of the stack is isolated.

According to some embodiments, a method of operating a memory structure, such as the memory structure described above, includes selecting by selecting one or two of a string selection line, a corresponding one of the bit lines, and a corresponding one of the word lines. A memory cell.

According to some embodiments, a method of fabricating a memory structure includes the following steps. A substrate is provided. A plurality of stacked layers are formed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. A plurality of memory layers are formed to conform to the stack. A plurality of channel layers are formed to conform to the memory layer. Forming a plurality of dielectric layers at a plurality of portions of the first side of the stack and channel layers at least at the channel level on a plurality of portions of the second sides of the stack. A plurality of first wires are formed along the sidewalls of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires formed on the first sides of the stacks and a second set of first wires formed on the second sides of the stacks, formed in the stacks One of the first wires of the first set of first wires stacked on the first side, and formed in One of the first set of first conductors of the second side of the same stack is isolated and one of the first set of first conductors formed on the second side of the stack adjacent one of the stacks Wire isolated.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100,200‧‧‧ memory structure

102‧‧‧Substrate

104, 204‧‧‧ buried layer

106‧‧‧Source line

108‧‧‧Stacking

110,110(S)‧‧‧ Conductive strip

112‧‧‧Insulation strip

114‧‧‧Superstructure

116‧‧‧First insulation

118‧‧‧Second insulation

120, 220‧‧‧ memory layer

122, 222‧‧‧ channel layer

124‧‧‧Insulation materials

126‧‧‧ air gap

128‧‧‧ dielectric layer

130‧‧‧First wire

132, 132 (S) ‧ ‧ first wire

134, 134 (S) ‧ ‧ first wire

136‧‧‧Interlayer dielectric materials

138, 138 (S) ‧ ‧ second wire

140, 240‧‧‧Contact elements

142, 142 (S) ‧ ‧ memory cells

308‧‧‧Initial stacking

310‧‧‧ Conductive layer

312‧‧‧Insulation

316‧‧‧Insulation

318‧‧‧Insulation

320‧‧‧ initial memory layer

321‧‧‧channel lining

322‧‧‧ initial channel layer

323‧‧‧First insulation material

325‧‧‧Second insulation material

352‧‧‧First hole

354‧‧‧Second hole

356‧‧‧ Third insulating material

358‧‧‧Insulation materials

360‧‧‧ cutting road

S1‧‧‧ first side

S2‧‧‧ second side

FIG. 1 illustrates a memory structure in accordance with an embodiment.

Figure 2 illustrates the operation of the memory structure.

FIG. 3 illustrates another memory structure in accordance with an embodiment.

Figure 4 illustrates the operation of the other memory structure.

5A-19C illustrate a method of fabricating a memory structure in accordance with an embodiment.

Various embodiments will be described in more detail below in conjunction with the drawings. The drawings are for illustrative purposes only and are not intended to be limiting. For the sake of clarity, some elements may be exaggerated in some of the figures. For example, in a set of drawings, an element may only be exaggerated in one of the drawings. In addition, some elements and/or component symbols may be omitted from the drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated in another embodiment without further elaboration.

A memory structure according to an embodiment includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stack is placed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed at least on the plurality of portions of the channel layer on the first sides of the stack and the channel layer on a plurality of portions of the second sides of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires disposed on the first sides of the stacks and a second set of first wires disposed on the second sides of the stacks, disposed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires disposed on the second side of the same stack, and is disposed at One of the stacks of one of the second sets of first conductors adjacent to the second side of the stack is isolated.

Please refer to FIG. 1 , which illustrates a memory structure 100 in accordance with an embodiment. Memory structure 100 is depicted as a three-dimensional (3D) vertical channel inverse (NAND) memory structure having memory cells configured in an I-shaped array.

The memory structure 100 includes a substrate 102. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. The memory structure 100 can optionally include a buried layer 104 disposed on the substrate 102. For example, in some embodiments in which the substrate 102 provides a hole erasing function, the memory structure 100 can include a thin buried layer 104, or even no buried layer. The memory structure 100 can include a source line 106 disposed on the buried layer 104. In some embodiments, source line 106 provides an inter-band thermal hole erase function.

Memory structure 100 includes a plurality of stacks 108 disposed on substrate 102. As shown in FIG. 1, in a 3D vertical channel NAND memory structure having memory cells configured in an I-shaped string, the stack 108 can be disposed on the source line 106. Stacking 108 and its constituent elements (e.g., conductive strips 110) extend in a first direction, such as an X direction. The stacks 108 each have a first side S1 and a second side S2. The stacks 108 each include a plurality of alternating conductive strips 110 and a plurality of insulating strips 112 that alternate with one another. The stacks 108 can each further include an upper structure 114 disposed on the set of conductive strips 110 and the insulating strips 112. According to some embodiments, the upper structure 114 may include a first insulating layer 116 and a second insulating layer 118. The first insulating layer 116 is disposed on the set of conductive strips 110 and the insulating strips 112. The second insulating layer 118 is disposed on the first insulating layer 116.

The memory structure 100 includes a plurality of memory layers 120 that are conformally disposed on the stack 108. According to some embodiments, the memory layer 120 can have a barrier layer-capture layer-tunnel layer structure with the barrier layer closest to the stack 108 and the tunneling layer being the furthest away from the stack 108. The memory structure 100 includes a plurality of channel layers 122 that are conformally disposed on the memory layer 120. In the X direction, more than one channel layer 122 may be disposed on each of the stacks 108. In a Y direction, the channel layers 122 disposed on adjacent stacks 108 can be connected to each other, as shown in FIG.

The memory structure 100 can include an insulating material 124 disposed between the stacks 108, corresponding to the set of conductive strips 110 and the insulating strips 112. In some embodiments, an air gap 126 is present in the insulating material 124. The air gap 126 facilitates reducing the coupling rate of the two adjacent channel layers 122.

Memory structure 100 includes a plurality of dielectric layers 128 disposed at least in a plurality of portions of channel layer 122 at a first side S1 of stack 108 and channel layer 122 at a plurality of portions of second side S2 of stack 108. In the memory structure 100, as shown in FIG. 1, the portions of the first side S1 of the stack 108 and the portions of the channel layer 122 at the second side S2 of the stack 108 correspond to the upper portion of the stack 108. Structure 114. In some embodiments, dielectric layer 128 includes an oxide material. In some embodiments, dielectric layer 128 comprises a high dielectric constant material.

The memory structure 100 includes a plurality of first wires 130 disposed along sidewalls of the stack 108. That is, the first wire 130 may extend substantially in the first direction (X direction). The first wire 130 is isolated from the channel layer 122 by a dielectric layer 128. As shown in FIG. 1, dielectric layer 128 and first lead 130 may be positioned on insulating material 124. Since the insulating material 124 can be disposed corresponding to the set of conductive strips 110 and the insulating strips 112, the first conductive lines 130 can be disposed at a height higher than the set of the conductive strips 110 and the insulating strips 112. The first wire 130 includes a first set of first wires (132) disposed on a first side S1 of the stack 108 and a second set of first wires (134) disposed on a second side S2 of the stack 108. In the embodiment described herein, one of the first set of first conductors 132 of the first side S1 of the stack 108 is disposed, and the second of the second side S2 of the same stack 108 is disposed. One of the first wires of the set of first wires is isolated and isolated from one of the first wires 134 of the second set of first wires disposed on the second side S2 of the adjacent stack 108. As shown in FIG. 1, the first wires 130 may have a plurality of L-shaped cross sections. In addition, the L-shaped sections of the first set of first wires (132) and the L-shaped sections of the second set of first wires (134) may be mirror symmetrical. In some embodiments, the first wire 130 comprises a polysilicon based material, such as a doped polysilicon material. In some embodiments, the first wire 130 comprises a metallic material.

The memory structure 100 can include a plurality of second wires 138 disposed over the first wires 130. More specifically, memory structure 100 can include an interlevel dielectric material 136 that covers the elements described above. The interlayer dielectric material 136 forms a layer that provides a flat upper surface on which the second wire 138 is disposed. The second wire 138 extends in a second direction different from the first direction, such as the Y square to. The memory structure 100 can include a plurality of contact elements 140 that connect the second wire 138 to the channel layer 122.

Please refer to FIG. 2, which illustrates an operation method of the memory structure 100. A method for operating a memory structure includes selecting one or two of a string selection line, a corresponding one of the bit lines, and a corresponding one of the word lines in the string selection line. Select one of the memory cells in the memory cell. According to some embodiments, in the memory structure 100, the first wire 130 is a string selection line, the second wire 138 is a bit line, and the conductive strip 110 is a word line. In addition, a plurality of memory cells 142 can be defined at the intersection of the conductive strip 110 (word line) and the channel layer 122. In the operation of the memory structure 100, such as programming, reading, or erasing, etc., a memory cell 142(S) to be operated is selected by selecting a corresponding string selection line (first wire 132(S)), Corresponding bit lines (second wire 138(S)), and corresponding word lines (conductive strips 110(S)) are selected. In such a case, the selected string select line (132(S)) is turned on so that current can pass from the bit line (138(S)) through the corresponding channel layer 122 to the underlying source line. 106. In Fig. 2, the second wire 132(S) is a corresponding string selection line. In some other embodiments, however, a second wire 134 can be a corresponding string selection line.

Please refer to FIG. 3, which illustrates a memory structure 200 in accordance with another embodiment. The memory structure 200 is depicted as a 3D vertical channel NAND memory structure having memory cells configured in a U-shaped array. Unlike the memory structure 100, the stack 108 in the memory structure 200 can be disposed directly on the buried layer 204, while the series of memory cells 142 are connected to the source lines (not shown) by contact elements 240. As shown in FIG. 2, in the Y direction, the channel layers 222 disposed on the adjacent stacks 108 are connected to each other. In some embodiments, in the Y direction, the memory layer 220 disposed on the adjacent stack 108 can be This connection.

Please refer to FIG. 4, which illustrates an operation method of the memory structure 200. Similar to the foregoing, in the memory structure 200, the first wire 130 can be a string selection line, the second wire 138 can be a bit line, and the conductive strip 110 can be a word line. In addition, a plurality of memory cells 142 can be defined at the intersection of the conductive strip 110 (word line) and the channel layer 122. Among the operations of the memory structure 200, a memory cell 142(S) to be operated is selected by selecting corresponding serial string selection lines (first wires 132(S) and 134(S)), corresponding bit lines. (138(S)), and the corresponding word line (110(S)) are selected. In such a case, the selected string select lines (132(S) and 134(S)) are turned on so that current can pass from the bit line (138(S)) through the corresponding channel layer 122 to the contact element 240 and Thereby reaching the source line.

A method of fabricating a memory structure in accordance with an embodiment will be described below. Such a method includes the following steps. First, a substrate is provided. A plurality of stacked layers are formed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. A plurality of memory layers are formed to conform to the stack. A plurality of channel layers are formed to conform to the memory layer. Forming a plurality of dielectric layers at a plurality of portions of the first side of the stack and channel layers at least at the channel level on a plurality of portions of the second sides of the stack. A plurality of first wires are formed along the sidewalls of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires formed on the first sides of the stacks and a second set of first wires formed on the second sides of the stacks, formed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires formed on the second side of the same stack, and is formed at One of the stacks adjacent to the stack One of the first wires of the second set of first wires of the second side is isolated.

Please refer to Figures 5A-19C for a method such as this. Here, for ease of understanding, the method is illustrated for forming the memory structure 100. The patterns indicated by "B" and "C" are the cross-sectional views taken from the lines 1-1' and 2-2' in the pattern indicated by "A".

Please refer to FIGS. 5A-5B to provide a substrate 102. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. For example, substrate 102 can include a p-well (not shown) corresponding to the location of stack 108 that will be formed in the next step. In some embodiments, a buried layer 104 is formed on the substrate 102 as shown in FIG. 5B. The buried layer 104 may be formed of an oxide. A source line 106 is formed on the buried layer 104. Source line 106 can be formed from heavily doped n-type polysilicon. An initial stack 308 for forming the stack 108 is formed on the substrate 102. As shown in FIG. 5B, an initial stack 308 can be formed on the source line 106. The initial stack 308 includes a plurality of conductive layers 310 and a plurality of insulating layers 312 that alternate with one another. The initial stack 308 can include another insulating layer 316 formed over the set of alternating conductive layers 310 and insulating layers 312. The initial stack 308 can optionally include an insulating layer 318 formed over the insulating layer 316. The conductive layer 310 may be formed of doped polysilicon. The insulating layer 312 may be formed of an oxide. The insulating layer 316 may be formed of an oxide. The insulating layer 318 may be formed of tantalum nitride (SiN). Such a SiN layer can compensate for film stress and avoid stack collapse or bending with high aspect ratio.

Referring to FIGS. 6A-6B, a plurality of stacks 108 are formed on the substrate 102 by separating the initial stack 308 using a patterning process. The patterning process can stop at the source line 106. Stack 108 and its constituent elements (e.g., conductive strips 110) extend in a first direction, such as an X direction. Stacks 108 each have a first side S1 and a second side S2. The stacks 108 each include a plurality of alternating conductive strips 110 and a plurality of insulating strips 112 that alternate with one another. The stacks 108 can each further include an upper structure 114 formed on the set of conductive strips 110 and the insulating strips 112. The upper structure 114 can include a first insulating layer 116 and a second insulating layer 118. A first insulating layer 116 is formed on the set of conductive strips 110 and the insulating strips 112. The second insulating layer 118 is formed on the first insulating layer 116.

Referring to Figures 7A-7B, an initial memory layer 320 is formed. The initial memory layer 320 conformally covers the stack 108. The initial memory layer 320 can have a barrier layer-capture layer-tunnel layer structure with the barrier layer closest to the stack 108 and the tunneling layer being the furthest away from the stack 108. The initial memory layer 320 may be formed as an ONO (oxide-nitride-oxide) multilayer structure, an ONONO (oxide-nitride-oxide-nitride-oxide) multilayer structure, or ONONONO (oxide-nitride- Oxide-nitride-oxide-nitride-oxide) multilayer structure and the like. A channel liner 321 is formed on the initial memory layer 320. The channel liner 321 conformally covers the initial memory layer 320. The channel liner 321 can be formed of the same material as that used in the channel layer, such as an undoped or lightly doped polysilicon material or a germanium material.

Referring to FIGS. 8A-8B, a portion of the channel liner 321 and the initial memory layer 320 formed on the exposed surface of the source line 106 is removed by an anisotropic etching process. As a result, a plurality of memory layers 120 are formed conformally on the stack 108. Next, a material for the channel layer is conformally formed, for example, by deposition to form an initial channel layer 322. The initial channel layer 322 includes the remainder of the channel liner 321 and the material for the channel layer in this step.

Referring to FIGS. 9A-9B, a first insulating material 323 is formed in a non-conformal manner on the structures of FIGS. 8A-8B. Therefore, the first insulating material 323 Filled into the space between the stacks 108. The first insulating material 323 may be an oxide. An air gap 126 may be present in the first insulating material 323. The air gap 126 in the first insulating material 323 does not extend to the height of the superstructure 114.

Referring to FIGS. 10A-10C, a plurality of first holes 352 are formed in the first insulating material 323, for example, by etching. The elliptical first holes 352 are arranged in a direction different from the direction in which the stack 108 extends, for example along a Y direction. The first hole 352 is surrounded by the first insulating material 323 and penetrates through the first insulating material 323. When the first hole 352 is formed, a portion of the initial channel layer 322 is removed. Therefore, the initial channel layer 322 is not present in the first hole 352. In some embodiments, as shown in FIG. 10C, portions of the memory layer 120 may also be removed. In some other embodiments, memory layer 120 may not be removed by the forming step of first hole 352.

Referring to FIGS. 11A-11C, a second insulating material 325 is formed in a non-conformal manner on the structures of FIGS. 10A-10C. Therefore, the second insulating material 325 is filled into the first hole 352 and forms an elliptical island column along the Y direction. The second insulating material 325 can be an oxide. An air gap 126 may be present in the second insulating material 325. Similar to the foregoing, the air gap 126 in the second insulating material 325 does not extend to the height of the superstructure 114. If desired, a planarization process, such as a chemical-mechanical planarization (CMP) process, can be performed.

Referring to FIGS. 12A-12C, a plurality of second holes 354 are formed, for example, by a lithography patterning process. In this step, a portion of the initial channel layer 322 is removed, which corresponds to the portion of the portion removed by the forming step of the first hole 352. Thus, the initial channel layer 322 extends in the direction of the stack 108 (X direction) The upper layers are separated to form a plurality of channel layers 122 conformally positioned on the memory layer 120. Next, as shown in FIGS. 13A-13C, a third insulating material 356 is filled into the second holes 354. The third insulating material 356 can be tantalum nitride (SiN) or an oxide. If desired, a planarization process, such as a CMP process, can be performed.

Referring to Figures 14A-14C, a selective removal process, such as an etching process with high selectivity for the material of the polysilicon or channel layer, is performed. By this step, both the first insulating material 323 and the second insulating material 325 remain only between the stacks 108. The first insulating material 323 and the second insulating material 325 stack 108 are adjacent to each other in the extending direction (X direction). The combination of the remaining portions of the first insulating material 323 and the second insulating material 325 corresponds to the insulating material 124 formed between the stacks 108 in FIG. 1 and corresponding to the set of conductive strips 110 and the insulating strips 112. The air gap 126 is not exposed by this step.

Referring to FIGS. 15A-15C, a plurality of dielectric layers 128 are formed in at least a plurality of portions of the first side S1 of the stack 108 and at least a plurality of portions of the channel layer 122 at the second side S2 of the stack 108. on. For example, the dielectric layer 128 can comprise an oxide material and is formed by exposing portions of the oxidized via layer 122, or by depositing the oxide material onto the portions. Therefore, the dielectric layer 128 is formed at a higher level than the first insulating material 323 and the second insulating material 325. In some embodiments, the dielectric layer 128 formed by oxidation can be approximately 70 Å thick. In some embodiments, instead of the oxide material, the dielectric layer 128 can comprise a high dielectric constant material.

Referring to FIGS. 16A-16C, a plurality of first wires 130 are formed along sidewalls of the stack 108. For example, a channel of a conductive material for forming the first conductive line 130 exposed by the first insulating material 323 and the second insulating material 325 may be formed. Layer 122 is, for example, in a conformal manner. An insulating material 358 (not shown in Figure 16A) may be filled into the remaining space. Next, a scribe line 360 is formed between the stacks 108, such as by an etch process. As such, the conductive material between the stacks 108 is separated to form the first wires 130. Such a process is a self-aligned process. The first wire 130 formed by these steps is positioned on the first insulating material 323 and the second insulating material 3254. The first wire 130 is isolated from the channel layer 122 by a dielectric layer 128. As shown in FIG. 1, the first wire 130 of the first wire 130 includes a first set of first wires (132) formed on the first side S1 of the stack 108 and a second formed on the second side S2 of the stack 108. a first set of wires (134) formed in one of the first set of first wires of a first side S1 of the stack 108, and a second set formed on a second side S2 of the same stack 108 One of the first wires 134 is isolated and isolated from one of the first wires 134 of the second set of first wires formed on the second side S2 of an adjacent stack 108. If desired, a cutting process can be performed to separate the first wire 132 and the first wire 134 corresponding to the same stack 108 at the end portions of the stack 108.

Referring to Figures 17A-17C, an inter-layer dielectric material 136 is formed on the structure of Figures 16A-16C, for example by deposition. The interlayer dielectric material 136 can be an oxide. In some embodiments, the interlayer dielectric material 136 is the same as the insulating material 358. If desired, a planarization process, such as a CMP process, can be performed.

Referring to FIGS. 18A-18C, a plurality of contact elements 140 are formed through the interlayer dielectric material 136, such as by a lithographic patterning process, such as an etch process. The contact element 140 is used to connect the second wire 138 to be formed in the next step to the channel layer 122. In some embodiments, a contact element (not shown) for the first wire 134 is formed at the end portion of the stack 108, for example by the same This process of forming contact element 140.

Referring to FIGS. 19A-19C, a plurality of second wires 138 are formed over the first wires 130. As shown in FIG. 19B, a second wire 138 can be formed over the interlayer dielectric material 136 and connected to the channel layer 122 by the contact element 140. The second wire 138 extends in a second direction different from the first direction, such as the Y direction.

A memory structure according to an embodiment has a configuration in which two serial select lines (132 and 134) correspond to one word line stack (108). Thus, one channel layer (122) can be divided into two portions that are each controlled by two serial selection lines. Thus, a structure of two bits on an entity is provided. With such a configuration, the density of the bit line (138) can be reduced to half that of the conventional memory structure. Moreover, since the series select lines (130) are not formed in the stack (108), they can be formed of a metallic material accompanied by a gate dielectric layer (128) formed of a high dielectric constant material. Thereby, the resistance of the string selection line can be reduced and the controllability thereof can be improved.

It will be appreciated that while the foregoing embodiments are directed to a 3D vertical channel NAND memory structure having memory cells configured in an I-shaped and U-shaped string, a configuration is provided in which two string select lines correspond to one stack. The type and its operation and manufacturing methods can be applied to other types of memory structures where possible.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. Prevail.

Claims (9)

A memory structure comprising: a substrate; a plurality of stacks disposed on the substrate, wherein the stacks each have a first side and a second side, and the stacks each comprise a plurality of alternating strips alternating with each other And a plurality of insulating strips; the plurality of memory layers are conformally disposed on the stacks; the plurality of channel layers are conformally disposed on the memory layers; and the plurality of dielectric layers are disposed at least at the channel layers a plurality of portions of the first side of the stack and the plurality of portions of the channel layer on the second sides of the stack; and a plurality of first wires along the stacked a sidewall disposed, wherein the first wires are isolated from the channel layers by the dielectric layers; wherein the first wires comprise a first set of first wires and settings disposed on the first sides of the stacks a second set of first wires on the second sides of the stacks, one of the first wires of the first set of the first wires stacked on one of the stacks, and a set The second set of first wires on the second side of the same stack Isolated from one of the first conductor, and the second set is provided with a first conductor adjacent to one side of the second stack in a first one of the plurality of conductors isolated stack. The memory structure of claim 1, wherein the stacks further comprise an upper structure disposed on the alternating set of conductive strips and the insulating strips, the upper structure comprising: a first insulation a layer, the alternating conductive strips and the insulating strips disposed in the group And a second insulating layer disposed on the first insulating layer. The memory structure of claim 1, wherein the dielectric layers comprise at least one of an oxide material and a high-k material, wherein the first wires comprise a polysilicon-based material and At least one of a metallic material. The memory structure of claim 1, wherein the first wires have a plurality of L-shaped profiles, wherein the L-shaped profiles of the first set of first wires and the second set of first wires These L-shaped sections are mirror symmetrical. The memory structure of claim 1, wherein the first wires are disposed above a height of the plurality of alternating conductive strips and the insulating strips. The memory structure of claim 1, further comprising: a plurality of second wires disposed above the first wires; wherein the stacked conductive strips extend in a first direction, The first wire extends substantially in the first direction, and the second wires extend in a second direction different from the first direction. The memory structure of claim 6, wherein the first wires are tandem selection lines, the second wires are bit lines, and the conductive strips are word lines. Such as the memory structure described in claim 7 of the patent scope, wherein a plurality of memory cells are Defined at the intersection of the conductive strips and the channel layers. An operating method for a memory structure according to claim 8, comprising: selecting a corresponding one or two of the series of select lines, and selecting a corresponding one of the bit lines A meta-line, and a corresponding one of the word lines, select one of the memory cells.