TWI607516B - Semiconductor device manufacturing method and manufacturing apparatus - Google Patents

Description

Semiconductor device manufacturing method and manufacturing device

[Related application]

The present application has priority from the application based on Japanese Patent Application No. 2015-176690 (filing date: September 8, 2015). This application contains the entire contents of the basic application by reference to the basic application.

Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a device for manufacturing the same.

A semiconductor device in which a plurality of types of semiconductor wafers are mounted in a package is known. As one of methods for forming a laminated structure including a plurality of types of semiconductor wafers, there is a method in which a first semiconductor wafer placed on a substrate is buried in an adhesive layer, and a second semiconductor wafer is laminated on the subsequent layer. In this method, it is desirable to suppress the bending of the second semiconductor wafer which may occur due to embedding the first semiconductor wafer in the subsequent layer.

Embodiments of the present invention provide a method and apparatus for manufacturing a semiconductor device capable of suppressing warpage of a semiconductor wafer.

According to an embodiment, a method of fabricating a semiconductor device is provided. In the method of manufacturing a semiconductor device, the first semiconductor wafer is placed on a substrate. The second semiconductor wafer to which the adhesive layer is bonded is placed on the substrate in a state where the adhesive layer faces the substrate side. When the second semiconductor wafer is placed on the substrate, the first semiconductor wafer is buried in the adhesion layer in a state where the viscosity of the first portion in the adhesive layer is lower than the viscosity of the second portion. Part 1 is located in the next layer A portion of the range placed on the first semiconductor wafer. The second part is the part of the subsequent layer that is located around the first part. The second semiconductor wafer is attached to the substrate via the spacer layer.

1‧‧‧Semiconductor device

10‧‧‧Substrate

11‧‧‧ Controller chip

12‧‧‧Next layer

13‧‧‧ Sealing members

14‧‧‧Connecting terminal

15‧‧‧Electrode

21‧‧‧NAND chip

22‧‧‧NAND chip

23‧‧‧NAND chip

24‧‧‧NAND chip

25‧‧‧ wire

26‧‧‧Connecting terminal

27‧‧‧Electrode

31‧‧‧NAND chip

32‧‧‧NAND chip

33‧‧‧NAND chip

34‧‧‧NAND chip

35‧‧‧Wire

36‧‧‧Connecting terminal

37‧‧‧Electrode

40‧‧‧ mounting table

41‧‧‧thermal adjustment member

42‧‧‧High thermal conductivity components

43‧‧‧Low thermal conductivity components

44‧‧‧The nozzle keeps the fixture

45‧‧‧Adsorption nozzle

50‧‧‧mounting table

51‧‧‧heater

A‧‧‧ arrow

B‧‧‧ arrow

T‧‧‧temperature

η‧‧‧Visco

Fig. 1 is a first side view schematically showing a configuration of a semiconductor device manufactured by using the manufacturing method of the first embodiment.

2 is a second side view of the semiconductor device shown in FIG. 1.

3 is a top plan view of the semiconductor device shown in FIG. 1.

4(a) to 4(c) are views showing the procedure of a method of manufacturing a semiconductor device according to the first embodiment.

Fig. 5 is a plan view showing the heat conduction adjusting member shown in Fig. 4.

Fig. 6 is a view for explaining the viscosity at the time of melting of the adhesive layer in the manufacturing method of the first embodiment.

Fig. 7 is a view for explaining the procedure of a method of manufacturing the semiconductor device of the second embodiment.

Hereinafter, a method of manufacturing a semiconductor device and a manufacturing apparatus according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the invention is not limited by the embodiments.

(First embodiment)

Fig. 1 is a first side view schematically showing a configuration of a semiconductor device manufactured by the manufacturing method of the first embodiment. 2 is a second side view of the semiconductor device shown in FIG. 1. 3 is a top plan view of the semiconductor device shown in FIG. 1. The semiconductor device 1 is provided with a laminated structure of a semiconductor wafer. The semiconductor device 1 is, for example, a controller-incorporated NAND (Not AND) flash memory.

The first side view shown in Fig. 1 is a side view of the semiconductor device 1 as seen from the direction of the arrow A shown in Fig. 3. The second side view shown in Fig. 2 is a side view when the semiconductor device 1 is viewed from the direction of the arrow B shown in Fig. 3.

The semiconductor device 1 is mixed with a controller wafer 11 and eight NAND wafers 21 on a substrate 10. ~24, 31~34. Further, in FIGS. 1, 2, and 3, the semiconductor device 1 is shown in a state in which the sealing member 13 is seen.

The controller wafer 11 as the first semiconductor wafer is a controller that controls writing and reading of data in the NAND chips 21 to 24 and 31 to 34. The controller wafer 11 is disposed on the substrate 10. The controller wafer 11 has a rectangular planar shape smaller than the NAND wafers 21 to 24 and 31 to 34. The controller wafer 11 is buried in the adhesive layer 12. In FIGS. 1 and 2, the controller wafer 11 located inside the bonding layer 12 is indicated by a broken line.

The NAND chips 21 to 24 and 31 to 34, which are the second semiconductor wafers, are non-volatile memory chips that hold data. The NAND chips 21 to 24 and 31 to 34 are laminated on the subsequent layer 12. The lowermost NAND wafer 21 of the NAND wafers 21 to 24, 31 to 34 is bonded to the substrate 10 via the adhesion layer 12. The NAND chips 21 to 24 and 31 to 34 are bonded to each other via an adhesive layer (not shown).

Each of the NAND chips 21 to 24 and 31 to 34 has a rectangular planar shape. The four NAND wafers 21 to 24 from the bottom to the fourth layer of the NAND wafers 21 to 24 and 31 to 34 are provided with electrodes 27 on the first side of the upper surface. The first side is set to the side of the rectangle on the near side in the direction of the arrow B. A plurality of electrodes 27 are provided along the first side of each of the NAND chips 21 to 24. The electrode 27 is, for example, an aluminum pad.

On the surface of the NAND wafer 21 to 24 or more, the portions on the first side where the electrodes 27 are provided are not overlapped and are stacked with each other. The NAND wafers 21 to 24 are laminated such that the first side portion forms a step. A plurality of connection terminals 26 corresponding to the electrodes 27 are provided on the substrate 10.

The wire 25 electrically connects the electrode 27 of each of the NAND chips 21 to 24 to the connection terminal 26 of the substrate 10. The wire 25 is, for example, gold, copper or silver. The connection between the electrode 27 and the connection terminal 26 by the wire 25 is formed by wire bonding. Each of the NAND wafers 21 to 24 is laminated in a stepped manner, and then the NAND wafers 21 to 24 are bonded to the electrodes 27 by wire bonding. Further, the illustration of the wire 25, the connection terminal 26, and the electrode 27 is omitted in FIG. In the province of Figure 3 The illustration of the wire 25 is omitted.

The NAND wafers 31 of the NAND chips 21 to 24 and 31 to 34 which are the fifth layer from the bottom to the top are vacated from the bottom to the first side of the fourth layer of the NAND wafer 24 and are stacked on the NAND. On the wafer 24.

The NAND wafers 21 to 24 and 31 to 34 are provided with electrodes 37 on the second side of the upper surface from the NAND wafer 31 on the upper side of the four NAND wafers 31 to 34. The second side is set to the side opposite to the first side of the rectangle and is located on the inner side of the arrow B. A plurality of electrodes 37 are provided along the second side of each of the NAND chips 31 to 34. The electrode 37 is, for example, an aluminum pad.

The portions on the second side of the surface of the NAND wafers 31 to 34 in which the electrodes 37 are provided are stacked without being covered. The NAND wafers 31 to 34 are laminated such that a portion on the second side is stepped. A plurality of connection terminals 36 corresponding to the electrodes 37 are provided on the substrate 10.

The wire 35 electrically connects the electrode 37 of each of the NAND wafers 31 to 34 to the connection terminal 36 of the substrate 10. The wire 35 is, for example, gold or copper. The connection between the electrode 37 and the connection terminal 36 by the wire 35 is formed by wire bonding. The NAND wafers 31 to 34 are stacked in a stepped manner, and the NAND wafers 31 to 34 are bonded to the electrodes 37 by wire bonding. Furthermore, the illustration of the wires 35 is omitted in FIG.

A plurality of electrodes 15 are disposed on the upper surface of the controller wafer 11. The electrode 15 is, for example, an aluminum pad. A plurality of electrodes 15 are arranged along each side of the rectangle of the controller wafer 11. A plurality of connection terminals 14 corresponding to the electrodes 15 are provided on the substrate 10. In addition, in FIG. 1 and FIG. 2, illustration of the connection terminal 14 and the electrode 15 is abbreviate|omitted. The electrode 15 and the connection terminal 14 are electrically connected by a wire (not shown). The wires are, for example, gold or copper.

The connection terminals 14, 26, 36 are formed on the upper surface of the substrate 10. The connection terminals 14, 26, 36 are formed, for example, by electroless plating of nickel and gold on copper. An external connection terminal (not shown) is formed on the lower surface of the substrate 10. External connection terminals such as solder balls or solder bumps Piece. A member for electrically connecting the connection terminals 14, 26, and 36 to the external connection terminal, for example, a wiring layer and a via hole, is formed in the substrate 10.

The sealing member 13 is a mold resin that seals the NAND wafers 21 to 24 and 31 to 34 provided on the substrate 10.

The semiconductor device 1 is provided with a controller wafer 11 under a structure in which NAND wafers 21 to 24 and 31 to 34 are laminated. The controller wafer 11 is located substantially at the center of the projection range in the case where the range occupied by the structures of the NAND wafers 21 to 24 and 31 to 34 is projected onto the substrate 10.

By arranging the controller wafer 11 at this position, the semiconductor device 1 can make the lengths of the wirings between the NAND wafers 21 to 24, 31 to 34 and the controller wafer 11 nearly uniform. As a result, the semiconductor device 1 can suppress the unevenness of the signal transmission speed between the controller wafer 11 and the NAND chips 21 to 24 and 31 to 34, and can speed up the operation of the semiconductor device 1. The semiconductor device 1 can obtain nearly equal signal quality in each wiring between the NAND chips 21 to 24, 31 to 34 and the controller wafer 11. Further, the semiconductor device 1 can be made smaller in size than the case where the laminated structure and the controller wafer 11 are arranged side by side on the substrate 10.

Fig. 4 is a view for explaining the procedure of a method of manufacturing the semiconductor device of the first embodiment. The manufacturing apparatus used in the method of manufacturing a semiconductor device includes a mounting table 40 and a heat transfer adjusting member 41. The substrate 10 is placed on the mounting table 40 via the heat transfer adjusting member 41. The mounting table 40 is provided with a heating stage that functions as a heating mechanism that supplies heat.

The heat conduction adjusting member 41 is mounted on the mounting table 40. The heat conduction adjusting member 41 adjusts the heat conduction from the mounting table 40 to the adhesive layer 12. The heat conduction adjusting member 41 includes a high heat conductive member 42 as a first member and a low heat conductive member 43 as a second member. The substrate 10 is placed on the heat conduction adjusting member 41.

Fig. 5 is a plan view showing the heat conduction adjusting member shown in Fig. 4. The high heat conductive member 42 is provided in the first region of the heat conduction adjusting member 41. The first region is located on the substrate 10 on the heat conduction adjusting member 41 The area under which the controller wafer 11 is placed is directly below. The high heat conductive member 42 is formed to be slightly smaller than the rectangular plate member of the controller wafer 11. The high heat conductive member 42 uses a member having a high thermal conductivity such as copper or aluminum.

The low heat conductive member 43 is provided in the second region of the heat conduction adjusting member 41. The second region is a region other than the first region of the heat conduction adjusting member 41 and is a region around the entire first region. The low heat conductive member 43 has a first region as an open plate member. A high heat conductive member 42 is embedded in the opening. The low heat conductive member 43 is made of a member having a thermal conductivity lower than that of the high heat conductive member 42, for example, a fluororesin material such as PTFE (polytetrafluoroethylene).

The heat conduction adjusting member 41 is detachably provided on the mounting table 40. The manufacturing apparatus can adjust the heat conduction corresponding to the position of the controller wafer 11 on the substrate 10 by combining the heat conduction adjusting member 41 in the mounting table 40 which is generally used in the manufacture of the semiconductor device.

A gap may also be provided between the high heat conductive member 42 and the low heat conductive member 43. By providing the gap, heat conduction from the high heat conductive member 42 to the low heat conductive member 43 can be reduced. The high heat conductive member 42 can also be integrally formed with the metal mounting table 40. Regarding the material of the high heat conductive member 42 and the low heat conductive member 43, any material may be used as long as the heat conductivity of the high heat conductive member 42 is higher than the heat conductivity of the low heat conductive member 43.

4(a) to (c) respectively show cross sections parallel to the plane shown in Fig. 2. In the step shown in FIG. 4(a), the substrate 10 is placed on the heat transfer regulating member 41 placed on the mounting table 40, and the controller wafer 11 is placed on the substrate 10. The controller wafer 11 is disposed in a region directly above the first region on the heat conduction adjusting member 41 in the substrate 10. The controller wafer 11 is next to the substrate 10 via an adhesive layer (not shown).

The transfer mechanism for transferring the semiconductor wafer includes the nozzle holding jig 44 and the suction nozzle 45 shown in FIG. 4(b). The nozzle holding jig 44 holds the suction nozzle 45. The adsorption nozzle 45 is connected to a vacuum pump (not shown). The adsorption nozzle 45 adsorbs the surface of the semiconductor wafer to be transferred by the suction force generated by the vacuum pump. The nozzle holding fixture 44 will be adsorbed in the half of the adsorption nozzle 45 The conductor wafer is lifted and the lifted semiconductor wafer is transferred.

In the step shown in FIG. 4(b), the nozzle holding jig 44 transfers the NAND wafer 21 to which the bonding layer 12 is bonded to the substrate 10. Layer 12 is then disposed over the entire lower surface of NAND wafer 21. The adsorption nozzle 45 adsorbs the upper surface of the NAND wafer 21. The NAND wafer 21 is transferred in a state in which the lower surface of the adhesive layer 12 is bonded downward. Next, the layer 12 is, for example, a die-bonding film using a thermosetting resin.

The nozzle holding jig 44 mounts the adhesive layer 12 and the NAND wafer 21 on the substrate 10 on which the controller wafer 11 is placed. The NAND wafer 21 is placed on the substrate 10 in a state in which the adhesive layer 12 faces the substrate 10 side. When the bonding layer 12 reaches the controller wafer 11 and the substrate 10, the bonding layer 12 is further pressed against the controller wafer 11 and the substrate 10 by the action of the nozzle holding jig 44.

The layer 12 is then softened by the heat transferred from the mounting table 40 to the thermally conductive adjustment member 41 and the substrate 10. Layer 12 is then changed from a solid state to a molten state by heating. The controller wafer 11 is buried in the adhesive layer 12 which has been in a molten state. The electrode 15 of the controller wafer 11, the connection terminal 14, and the wire between the electrode 15 and the connection terminal 14 are also buried in the adhesion layer 12 together with the controller wafer 11. The layer 12 then abuts the upper surface of the substrate 10 around the controller wafer 11. Thereby, as shown in FIG. 4(c), the NAND wafer 21 is adhered to the substrate 10 via the adhesion layer 12.

Fig. 6 is a view for explaining the viscosity at the time of melting of the adhesive layer in the manufacturing method of the first embodiment. 6 is a graph showing the relationship between the position in the adhesive layer 12 and the temperature T of the adhesive layer 12, and a graph showing the relationship between the position in the adhesive layer 12 and the viscosity η when the adhesive layer 12 is melted. The position in the subsequent layer 12 is a position along a direction including the cross section of the controller wafer 11 and the subsequent layer 12 and parallel to the upper surface of the substrate 10.

In the heat conduction adjusting member 41, the first region in which the high heat conductive member 42 is provided has a higher heat transfer efficiency (lower thermal resistance) than the second region in which the low heat conductive member 43 is provided. If the bonding layer 12 is reached to the controller wafer 11 and the substrate 10, then the bonding layer 12 The heating of the other portions is further suppressed as compared with the heating of the portion of the range placed on the controller wafer 11.

Here, the portion of the adhesive layer 12 placed on the controller wafer 11 is set as the first portion. A portion other than the first portion of the subsequent layer 12 and a portion around the entire first portion is referred to as a second portion.

The heating of the second portion is further suppressed as compared with the heating of the first portion, whereby the temperature T of the subsequent layer 12 is increased in the first portion, and is lowered in comparison with the first portion. In this manner, the heat conduction adjusting member 41 adjusts the heat conduction from the mounting table 40 to the adhesive layer 12 such that the temperature T of the first portion is higher than the temperature T of the second portion.

By adjusting the heat conduction as described above, the melting of the adhesive layer 12 in the first portion is promoted as compared with the second portion. The melting of the first portion is promoted compared to the melting of the second portion, whereby the viscosity η of the subsequent layer 12 is lowered in the first portion, and is increased in the second portion compared to the first portion. In the manufacturing method of the first embodiment, the controller wafer 11 is buried in the adhesive layer 12 in a state where the viscosity η of the first portion of the adhesive layer 12 is lower than the viscosity η of the second portion.

The controller wafer 11 is buried in the adhesion layer 12 and the NAND wafer 21 is adhered to the substrate 10 via the adhesion layer 12, and then the layer 12 is cured. The controller wafer 11 is subsequently placed in the subsequent layer 12 by hardening the bonding layer 12. The NAND wafer 21 is interposed between the subsequent layers 12 and then on the substrate 10. Next, the layer 12 is further cured by heating and pressurization at the time of sealing by the sealing member 13 described below.

Three NAND wafers 22 to 24 are sequentially stacked on the NAND wafer 21. Each of the NAND wafers 22 to 24 is superposed in a state in which an adhesive layer is bonded. After the four NAND wafers 21 to 24 are laminated, the electrodes 27 of the NAND wafers 21 to 24 and the connection terminals 26 are sequentially connected by wire bonding, thereby forming the wires 25. By stacking the four NAND chips 21 to 24 in a stepped manner, it is possible to save the time required to perform wire bonding every time the NAND wafers 21 to 24 are placed.

Four NAND wafers 31 to 34 are sequentially stacked on the NAND wafer 24. Each NAND The wafers 31 to 34 are superposed in a state in which the subsequent layers are bonded. After stacking the four NAND wafers 31 to 34, the electrodes 37 of the NAND wafers 31 to 34 and the connection terminals 36 are sequentially connected by wire bonding, thereby forming the wires 35. By stacking the four NAND wafers 31 to 34 in a stepped manner, it is possible to save the time required to perform wire bonding every time the NAND wafers 31 to 34 are arranged.

Further, the NAND wafers 22 to 24 and 31 to 34 may be stacked on the mounting table 40 including the heat conduction adjusting member 41 after the lowermost layer of the NAND wafer 21 is laminated. The stacking of the NAND wafers 22 to 24 and 31 to 34 may be performed after replacing the mounting table 40 including the heat conduction adjusting member 41 with another mounting table.

Thereby, the controller wafer 11 and the eight NAND chips 21 to 24 and 31 to 34 are mounted on the substrate 10. The structure on the substrate 10 is sealed by the sealing member 13, and is then singulated. By the above steps, the semiconductor device 1 shown in FIGS. 1 to 3 can be obtained.

It is assumed that the viscosity η of the entire adhesive layer 12 is substantially fixed, and the controller wafer 11 is buried in the adhesive layer 12. The layer 12 is then pressurized by the transfer mechanism and the contraction in the vertical direction is substantially equal to the position within the adhesive layer 12. In this case, there may be a case where the ridges correspond to the volume of the controller wafer 11 in comparison with the portion of the bonding layer 12 which is in contact with the controller wafer 11 and the surrounding portion thereof. By attaching the NAND wafer 21 to the substrate 10 by the bonding layer 12 interposed in this state, there is a possibility that the NAND wafer 21 is in a state of being bent in such a manner that a part of the controller wafer 11 is convex.

Since the lowermost NAND wafer 21 is bent, the NAND wafers 22 to 24 and 31 to 34 which are stacked on the upper side of the NAND wafer 21 are also respectively bent in a state of being bent. The NAND wafers 21 to 24 and 31 to 34 are easily deformed to cause damage or defective wafers.

Further, in the portion of the sealing member 13 which is located on the upper side of the uppermost NAND wafer 34, the portions of the NAND wafers 21 to 24, 31 to 34 which are convex are thinner than the portions thereof. In this state, the surface of the sealing member 13 is imprinted by laser irradiation, which is caused by the laser. The influence of heat may affect the uppermost NAND wafer 34. There may also be cases where the portion irradiated with the laser is exposed due to the sealing member 13 being cut off.

In the first embodiment, as described above, the controller wafer 11 is buried in the adhesive layer 12 in a state where the viscosity of the first portion of the adhesive layer 12 is lower than the viscosity of the second portion. By embedding the controller wafer 11 in the first portion in a state of being soft relative to the second portion, the swell of the first portion due to the presence of the controller wafer 11 of the bonding layer 12 can be reduced. Next, the layer 12 is surrounded by the controller wafer 11, and the NAND wafer 21 can be supported by the second portion which is in a state of being harder than the first portion.

Thereby, the bending of the partially convex NAND wafer 21 on the controller wafer 11 can be reduced. The NAND wafer 21 is attached to the substrate 10 while maintaining a flat state before the subsequent layer 12 is followed by the substrate 10. By reducing the bending of the lowermost NAND wafer 21, it is possible to reduce the bending of the NAND wafers 22 to 24, 31 to 34 which are stacked on the upper side than the NAND wafer 21. The NAND chips 21 to 24 and 31 to 34 can reduce damage due to deformation and poor adhesion between the wafers.

Further, the thickness of the upper portion of the uppermost NAND wafer 34 of the sealing member 13 is fixed to the upper portion of the controller wafer 11 and other portions. Since the position of the sealing member 13 is ensured to be sufficient for the thickness of the sealing member 13, the effect of the laser on the uppermost NAND wafer 34 can be reduced when the surface of the sealing member 13 is irradiated with laser light. Moreover, the exposure of the NAND wafer 34 at the portion irradiated with the laser can be suppressed. The semiconductor device 1 can suppress a decrease in reliability due to a defect in manufacturing.

The number of NAND chips stacked in the semiconductor device 1 is not limited to eight, and can be appropriately changed. The semiconductor device 1 is not limited to a controller chip 11 and a plurality of NAND chips. The second semiconductor wafer can also be any semiconductor wafer other than the NAND wafer. The semiconductor device 1 may be provided with any semiconductor wafer having a planar shape different from each other as the first and second semiconductor wafers. The semiconductor device 1 is configured to dispose a large semiconductor wafer on the adhesive layer 12 on which a small semiconductor wafer is embedded. Reducing the bending of large semiconductor wafers due to the presence of small semiconductor wafers. In the case where the semiconductor wafer provided on the adhesion layer 12 is large and thin, the bending of the semiconductor wafer can be effectively suppressed.

According to the first embodiment, the heat conduction from the mounting table 40 to the adhesive layer 12 is adjusted by the heat transfer adjusting member 41, and the temperature of the first portion of the layer 12 is higher than the temperature of the second portion. The first semiconductor wafer is buried in the adhesion layer 12 in a state where the viscosity of the first portion of the adhesive layer 12 which is in a molten state due to heating is lower than the viscosity of the second portion. It is possible to suppress the occurrence of a partial convex curvature on the first semiconductor wafer by the second semiconductor wafer. Thereby, the effect of suppressing the bending of the semiconductor wafer is exhibited.

(Second embodiment)

Fig. 7 is a view for explaining the procedure of a method of manufacturing the semiconductor device of the second embodiment. The same portions as those in the first embodiment are denoted by the same reference numerals, and the description thereof will not be repeated.

In the second embodiment, the substrate 10 is placed on a mounting table 50 that does not have the function of a heating mechanism. A heater 51 is attached to the nozzle holding jig 44. The heater 51 is a heating mechanism that supplies heat. Further, the mounting table 50 may have a function as a heating mechanism.

The transfer mechanism adsorbs the upper surface of the NAND wafer 21 to the adsorption nozzle 45 while the NAND wafer 21 is positioned relative to the adsorption nozzle 45. The heater 51 is partially mounted on a portion of the transfer mechanism that is positioned above the first portion in a state where the NAND wafer 21 is lifted.

While the transfer mechanism is raising the NAND wafer 21, the heat from the heater 51 is transferred to the adhesive layer 12 through the nozzle holding jig 44, the suction nozzle 45, and the NAND wafer 21. By mounting the heater 51 above the first portion of the adhesive layer 12, the heating of the second portion is suppressed in the adhesive layer 12 compared to the heating of the first portion.

The heating of the second portion is suppressed as compared with the heating of the first portion, whereby the temperature of the subsequent layer 12 is increased in the first portion, and is lowered in comparison with the first portion. With part 2 The melting of the layer 12 in the first portion is promoted. The melting of the first portion is promoted compared to the melting of the second portion, whereby the viscosity of the subsequent layer 12 is lowered in the first portion, and is increased in the second portion compared to the first portion. In the manufacturing method of the second embodiment, the controller wafer 11 is buried in the adhesive layer 12 in a state where the viscosity of the first portion of the adhesive layer 12 is lower than the viscosity of the second portion.

In the second embodiment, as in the first embodiment, the bending of the NAND wafer 21 which is partially convex on the controller wafer 11 can be reduced. The NAND chips 21 to 24 and 31 to 34 can reduce damage due to deformation and poor adhesion between the wafers. The semiconductor device 1 can suppress a decrease in reliability due to a problem in manufacturing.

Further, in the manufacturing method of the second embodiment, the mounting table 40 and the heat transfer adjusting member 41 in the first embodiment may be applied instead of the mounting table 50. Further, by combining the adjustment of the heat conduction in the first embodiment to the second embodiment, the heating of the first portion of the adhesive layer 12 can be promoted more than the heating of the second portion.

According to the second embodiment, the heating means is partially attached to a portion above the first portion in a state where the second semiconductor wafer is lifted by the transfer mechanism. Next, the layer 12 is supplied with heat from the heating means above the first portion, whereby the temperature of the first portion is higher than the temperature of the second portion. The first semiconductor wafer is buried in the adhesion layer 12 in a state where the viscosity of the first portion of the adhesive layer 12 which is in a molten state due to heating is lower than the viscosity of the second portion. It is possible to suppress the occurrence of a partial convex curvature on the first semiconductor wafer by the second semiconductor wafer. Thereby, the effect of suppressing the bending of the semiconductor wafer is exhibited.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in various other forms and various modifications, substitutions and changes may be made without departing from the scope of the invention. These embodiments and variations thereof are included in the scope and spirit of the invention, and are included in the scope of the invention described in the claims.

10‧‧‧Substrate

11‧‧‧ Controller chip

12‧‧‧Next layer

21‧‧‧NAND chip

40‧‧‧ mounting table

41‧‧‧thermal adjustment member

42‧‧‧High thermal conductivity components

43‧‧‧Low thermal conductivity components

44‧‧‧The nozzle keeps the fixture

45‧‧‧Adsorption nozzle

Claims (7)

A method of manufacturing a semiconductor device, wherein a first semiconductor wafer is placed on a substrate, and a second semiconductor wafer to which an adhesive layer is bonded is placed on the substrate in a state in which the adhesive layer faces the substrate side; When the second semiconductor wafer is placed on the substrate, the viscosity of the first portion of the adhesive layer placed on the first semiconductor wafer is lower than the first portion of the adhesive layer. In the state of the viscosity of the second portion, the first semiconductor wafer is buried in the adhesive layer, and the second semiconductor wafer is attached to the substrate via the adhesive layer. The method of manufacturing a semiconductor device according to claim 1, wherein the bonding layer bonded to the second semiconductor wafer is melted by heating, and the temperature of the first portion is higher than the temperature of the second portion during the heating. Thereby, the viscosity of the first portion is lower than the viscosity of the second portion. The method of manufacturing a semiconductor device according to claim 2, wherein the substrate is placed on a mounting table provided with a heating mechanism, and the temperature of the first portion is higher than the first portion by adjusting heat conduction from the mounting table to the bonding layer 2 parts of the temperature. The method of manufacturing a semiconductor device according to claim 3, wherein the substrate is placed on the mounting table via a heat transfer adjusting member provided on the mounting table, and the heat transfer adjusting member includes a first member positioned in the substrate The second member is placed under the region where the first semiconductor wafer is placed; and the second member is located around the first member; and the thermal conductivity of the first member is higher than the thermal conductivity of the second member. The method of manufacturing a semiconductor device according to claim 2, wherein the second semiconductor is transferred The transfer mechanism of the bulk wafer is provided with a heating mechanism that is partially attached to a portion above the first portion in a state where the second semiconductor wafer is lifted by the transfer mechanism. A manufacturing apparatus for a semiconductor device, comprising: a mounting table on which a substrate is placed; and a heating mechanism that mounts the second semiconductor wafer to which the adhesive layer is bonded to the substrate side When the substrate of the first semiconductor wafer is placed, the bonding layer is heated; and the heat conduction adjusting member has a first region located in a region of the substrate on which the first semiconductor wafer is placed, and is located in the first region a second heat transfer member having a first thermal conductivity in the first region and a second heat transfer member having a second thermal conductivity lower than the first thermal conductivity in the second region; And adjusting the heat conduction from the heating mechanism to the above-mentioned bonding layer. The apparatus for manufacturing a semiconductor device according to claim 6, wherein the first heat transfer member is smaller than the first region.