TWI607220B - Chip testing apparatus and electrical circuit board thereof - Google Patents

Description

Wafer test architecture and its board

The present invention relates to a test architecture and a circuit board thereof, and more particularly to a wafer test architecture and a circuit board thereof having a waveguide structure, such as a printed circuit board having a via hole and a conductive plate combined to form a rectangular waveguide ( Printed circuit board, PCB).

As electronic products are becoming more sophisticated and multi-functional, the wafer structure of integrated circuits in electronic products tends to be complex, and the operating frequency of the wafer structure is also greatly increased for use in electronic products in higher frequency bands. . The wafer test apparatus for testing the structure of the wafer must have the ability to test high frequency signals, as shown in FIG. 1, a schematic diagram of a wafer test architecture in a prior art, the test architecture including a printed circuit board (PCB) load board ( A load board 100 is connected to a socket 102 on the circuit board and a wafer 104 connected to the foot. The signal transmission path of the wafer 104 is transmitted from the wafer 104 via the foot 102, and then transmitted to the load board 100 of the printed circuit board to perform analysis and measurement of various signals by the instrument device 106 to confirm the wafer 104. Is the function normal?

In the prior art, the load board 100 of the printed circuit board transmits signals to the instrumentation device 106 via a microstrip trace 108, and each microstrip trace 108 is a small wire. However, when the operating frequency of the wafer 104 is at a higher frequency band, the signal response on the load board 100 The loss is large. For example, the loss of the medium (such as PCB material) or the reflection (such as the reflection loss of the signal) has a great influence on the response of the signal, which causes the transmission quality of the test signal to decrease, and the load board 100 cannot be used. The higher frequency range of wafer 104 testing. Therefore, it is necessary to propose a new type of circuit board structure to solve the above problems.

An object of the present invention is to provide a wafer test structure and a circuit board having a waveguide structure, such as a printed circuit board (PCB) having a via hole and a conductive plate combined to form a rectangular waveguide to utilize a rectangular waveguide. The preferred signal transmission feature replaces the traditional microstrip line, making the printed circuit board (PCB) suitable for higher operating frequency ranges during wafer testing.

To achieve the above objective, a wafer testing architecture in an embodiment of the present invention includes: a wafer; a foot having a plurality of pins for electrically interposing the wafer, the pins for transmitting the wafer a test signal; a circuit board electrically connected to the foot for transmitting the first test signal from the pins, wherein the circuit board is provided with at least one waveguide structure, and an input of the at least one waveguide structure The terminal electrically connects the pins to receive the first test signal from the pins, and the at least one waveguide structure directs the first test signal to be transmitted along a transmission direction for the at least one waveguide structure An output of the second test signal is outputted by adjusting a cross-sectional area of the at least one waveguide structure along the transmission direction to modulate a cutoff frequency of the at least one waveguide structure associated with the first test signal.

In one embodiment, the waveguide structure includes a plurality of vias connected to the second plane by a first plane of the circuit board, wherein the first plane and the second plane are different parallel planes of the circuit board Each of the via holes is provided with a conductive portion; a first conductive plate is disposed on the first plane to be electrically connected to the first end portion of the conductive portion; and a second conductive plate, The second plane is electrically connected to the second end of the conductive portion.

In one embodiment, the conductive portion, the first conductive plate, and the second conductive plate are the same conductive material.

In an embodiment, the electrically conductive material is a metal.

In an embodiment, the first plane and the second plane are different parallel faces of the inner or outer surface of the circuit board.

In one embodiment, the interval between each of the two via holes is less than 1/20 times the wavelength of the first test signal and/or the second test signal.

In one embodiment, the via holes are two columns of mutually parallel through holes, such that the conductive portions, the first conductive plate, and the second conductive plate in the two parallel rows of through holes are along The direction of transmission forms a rectangular waveguide structure.

In one embodiment, the waveguide structure has a cutoff frequency associated with the first test signal between 1 GHz and 300 GHz.

In an embodiment, the waveguide structure is represented by the following formula according to the cutoff frequency f _{c of} the first test signal on the circuit board:

Where μ and ε are the magnetic permeability and dielectric constant of the medium of the circuit board, m, n=1, 2, 3, ... are respectively a positive integer, and T is the section of the waveguide structure along the transmission direction The distance of the area, L is the length of the cross-sectional area of the waveguide structure along the transport direction.

The circuit board in another embodiment of the present invention is electrically connected to a foot, the circuit board is configured to transmit a first test signal from a foot of the foot, and at least one of the circuit board is provided a waveguide structure, an input end of the at least one waveguide structure is electrically connected to the pins to receive the first test signal from the pins, and the at least one waveguide structure guides the first test signal along a Transmitting, in a transmission direction, outputting a second test signal to an output end of the at least one waveguide structure, by adjusting a cross-sectional area of the at least one waveguide structure along the transmission direction, to modulate the at least one waveguide structure related to the The cutoff frequency of the first test signal.

100‧‧‧ load board

102‧‧‧ feet

104‧‧‧ wafer

106‧‧‧ instruments

108‧‧‧Microstrip line

200‧‧‧ wafer

202‧‧‧ feet

204‧‧‧Circuit board

205‧‧‧ instruments

206‧‧‧ feet

208‧‧‧Wave structure

208a‧‧‧ input

208b‧‧‧output

209‧‧‧ ring structure

400‧‧‧vias

402‧‧‧First conductive plate

404‧‧‧Second conductive plate

406‧‧‧ first plane

408‧‧‧ second plane

410‧‧‧Electrical Department

410a‧‧‧ first end

410b‧‧‧second end

A1‧‧‧ cross-sectional area

D1‧‧‧ interval

L‧‧‧ length

S1‧‧‧ first test signal

S2‧‧‧ second test signal

T‧‧‧ distance

TD1‧‧‧Transport direction

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below:

FIG. 1 is a schematic diagram of a wafer test architecture in the prior art.

2A is a schematic diagram of a wafer test architecture of a circuit board having a waveguide structure in an embodiment of the present invention.

2B is a schematic diagram of a wafer test architecture of a circuit board having two waveguide structures in an embodiment of the present invention.

3 is a partial perspective view of a circuit board having a waveguide structure in an embodiment of the present invention.

4 is a partial perspective perspective view of a circuit board having a waveguide structure in an embodiment of the present invention.

Referring to the drawings, wherein like reference numerals refer to the same or the The following description is based on the specific embodiments of the invention, which are not to be construed as limiting the invention.

Referring to FIG. 2A, a circuit having a waveguide structure 208 in an embodiment of the present invention is illustrated. Schematic diagram of the wafer test architecture of board 204. The wafer test architecture includes a wafer 200, a foot 202, and a circuit board 204 for performing various signal analysis and measurement by the instrument device 205 to confirm whether the function of the wafer 200 is normal. The chip 200 has, for example, a fixed-function integrated circuit having a plurality of pins (not shown) for generating a first test signal S1; the foot 202 has a plurality of pins 206, and the pins 206 are electrically connected. The pins of the chip are electrically connected to the chip 200, so that the pins 206 transmit the first test signal S1 of the wafer 200; in an embodiment, the chip 200 transmits different test signals according to the test requirements. Different feet 206 of the foot 202.

Referring to FIG. 2A and FIG. 3, FIG. 3 is a partial perspective view of a circuit board having a waveguide structure according to an embodiment of the present invention. As shown in FIG. 2A and FIG. 3, the circuit board 204 is electrically connected to the foot 202 for transmitting the first test signal S1 from the pins 206. The circuit board 204 is provided with a waveguide structure (wave- An input terminal 208a of the waveguide structure 208 is electrically connected to the pins 206 to receive the first test signal S1 from the socket 202, and the waveguide structure 208 guides the first test signal S1. Transmitting along a transmission direction TD1 to output a second test signal S2 at an output end 208b of the waveguide structure 208, by adjusting the cross-sectional area A1 of the waveguide structure 208 along the transmission direction TD1 to modulate the at least A waveguide structure 208 is associated with a cutoff frequency of the first test signal S1. The cutoff frequency is the boundary frequency at which the output signal energy of the second test signal S2 begins to drop significantly relative to the first test signal S1. The first test signal S1 and the second test signal S2 are, for example, in the form of electromagnetic waves. In other words, the waveguide structure 208 of the present invention is a ring structure 209 (shown in FIG. 3) along the transmission direction TD1 of the test signal, so that the transmission process of the first test signal S1 is limited to the ring structure. The power loss of the first test signal S1 is reduced to form a second test signal S2. In an embodiment, the first test signal S1 is reflected when the metal structure is touched inside the waveguide structure 208, and the first test signal after the reflection The S1 encounters another metal plate and reflects again. In this way, the first test signal S1 is transmitted along the metal plate to output the second test signal S2.

As shown in FIG. 2A and FIG. 3, the cutoff frequency f _{c of} the waveguide structure 208 with respect to the first test signal S1 is expressed by the following formula F1:

Where μ and ε are respectively the magnetic permeability and dielectric constant of the medium of the circuit board 204, m, n=1, 2, 3, ... are respectively a positive integer, and T is the distance of the cross-sectional area A1 of the waveguide structure 208. L is the length of the cross-sectional area A1 of the waveguide structure 208. According to the above formula F1, the present invention effectively increases the operating frequency of the circuit board 204 for the first test signal S1 by adjusting the distance T and the length L to modulate the cutoff frequency. In one embodiment, the cutoff frequency f _c of the waveguide structure 208 associated with the first test signal S1 is between 1 GHz and 300 GHz, but is not limited thereto, such as a higher or lower frequency range.

Referring to FIG. 4, a partial perspective perspective view of a circuit board 204 having a waveguide structure 208 in accordance with an embodiment of the present invention is shown. The waveguide structure 208 includes a plurality of vias 400, a first conductive plate 402, and a second conductive plate 404.

In FIG. 4, a plurality of vias 400 are connected to the second plane 408 by a first plane 406 of the circuit board 204, wherein the first plane 406 and the second plane 408 are different parallel faces of the circuit board 204. Each of the via holes 400 is provided with a conductive portion 410, and the via holes 400 of the conductive portion 410 are the same coplanar conductive regions to provide the first test signal S1 for waveguide reflection. The first plane 406 and the second plane 408 are internal to the circuit board 204 (for example, a circuit board of a multilayer wiring) or different parallel surfaces of the outer surface. In an embodiment, for example, a drill The hole or semiconductor process (for example, etching) forms the via hole 400 in the circuit board 204, and the manufacturing process thereof is relatively easy; the conductive portion 410 is formed, for example, on the inner wall of the via hole 400 or fills the via hole 400. The first conductive plate 402 is disposed on the first plane 406 to be electrically connected to the first end portion 410a of the conductive portion 410. In one embodiment, the first conductive plate 402 is formed, for example, by electroplating or deposition. The second conductive plate 404 is disposed on the second surface 408 to be electrically connected to the second end portion 410b of the conductive portion 410. In one embodiment, the second conductive plate 404 is formed, for example, by electroplating or deposition.

As shown in FIG. 4, in an embodiment, the conductive portion 410, the first conductive plate 402, and the second conductive plate 404 are made of the same conductive material, and the conductive material is metal. In one embodiment, the first test signal S1 is reflected when the first conductive plate 402 is touched inside the waveguide structure 208, and the reflected first test signal S1 hits the second conductive plate 404 and is reflected again. The first test signal S1 is transmitted along the conductive plate to output a second test signal S2.

In FIG. 4, in an embodiment, the interval d1 between each of the two via holes 400 is smaller than the wavelength of the first test signal S1 and/or the second test signal S2. In a preferred embodiment, the interval between each of the two via holes 400 is less than 1/20 times the wavelength of the first test signal S1 and/or the second test signal S2.

As shown in FIG. 4, the via holes 400 are two rows of mutually parallel via holes, such that the conductive portions 410, the first conductive plate 402, and the second conductive portion in the two parallel rows of the via holes are parallel. Plate 404 forms a rectangular waveguide structure 208. The invention is also applicable to waveguide structures 208 of different shapes, such as circular or irregular shapes, and the calculation of different cutoff frequencies to adjust the operating frequency range of the first test signal S1. In addition, the waveguide structure 208 of the present invention may also be a material layer in the circuit board 204, as shown in FIG. 2A to FIG. 4, or the waveguide structure 208 may also be the circuit board 204. The multi-layer layer is formed, as shown in FIG. 2B, the wafer test structure of the circuit board 204 having the waveguide structure 208 of the upper and lower layers, but the number is not limited thereto, for example, three or more waveguide structures 208, each waveguide structure 208 is electrically connected by a through hole (not shown).

In summary, the wafer test architecture and circuit board of the present invention have a waveguide structure circuit board, for example, a printed circuit board (PCB) having a via hole and a conductive plate combined to form a rectangular waveguide to utilize a rectangular waveguide. The better signal transmission characteristics replace the traditional microstrip line, making the printed circuit board (PCB) suitable for the higher operating frequency range of the wafer test, and the process is simple.

While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

204‧‧‧Circuit board

208‧‧‧Wave structure

208a‧‧‧ input

208b‧‧‧output

209‧‧‧ ring structure

400‧‧‧vias

402‧‧‧First conductive plate

404‧‧‧Second conductive plate

406‧‧‧ first plane

408‧‧‧ second plane

410‧‧‧Electrical Department

410a‧‧‧ first end

410b‧‧‧second end

A1‧‧‧ cross-sectional area

D1‧‧‧ interval

L‧‧‧ length

S1‧‧‧ first test signal

S2‧‧‧ second test signal

T‧‧‧ distance

TD1‧‧‧Transport direction

Claims (19)

A wafer test architecture comprising: a wafer; a foot having a plurality of pins for electrically inserting the chip, the pins for transmitting a first test signal of the chip; a circuit board, electrical Connecting the foot to transmit the first test signal from the pins, wherein at least one waveguide structure is disposed in the circuit board, and an input end of the at least one waveguide structure is electrically connected to the pins Receiving the first test signal from the pins, and the at least one waveguide structure guiding the first test signal to be transmitted along a transmission direction to output a second test signal at an output end of the at least one waveguide structure Adjusting a cutoff frequency of the at least one waveguide structure with respect to the first test signal by adjusting a cross-sectional area of the at least one waveguide structure along the transmission direction. The wafer test architecture of claim 1, wherein the at least one waveguide structure comprises: a plurality of vias connected by a first plane of the circuit board to a second plane, wherein the first plane and the second plane And a conductive portion of each of the conductive vias; the first conductive plate is disposed on the first plane to electrically conduct with the first end of the conductive portion And a second conductive plate disposed on the second plane to be electrically connected to the second end of the conductive portion. The wafer test architecture of claim 2, wherein the conductive portion, the first A conductive plate and a second conductive plate are the same conductive material. The wafer test architecture of claim 3, wherein the conductive material is a metal. The wafer test architecture of claim 2, wherein the first plane and the second plane are different parallel faces of the inner or outer surface of the circuit board. The wafer test architecture of claim 2, wherein the interval between each of the two via holes is less than 1/20 times the wavelength of the first test signal and/or the second test signal. The wafer test structure of claim 2, wherein the via holes are two columns of mutually parallel through holes, the conductive portions in the two parallel rows of through holes, the first conductive plate And the second conductive plate forms a rectangular waveguide structure along the transmission direction. The wafer test architecture of claim 1, wherein the waveguide structure has a cutoff frequency of between 1 GHz and 300 GHz with respect to the first test signal. The wafer test architecture of claim 1, wherein the cutoff frequency f _{c of} the waveguide structure associated with the first test signal is expressed by the following formula: Where μ and ε are the magnetic permeability and dielectric constant of the medium of the circuit board, m, n=1, 2, 3, ... are respectively a positive integer, and T is the section of the waveguide structure along the transmission direction The distance of the area, L is the length of the cross-sectional area of the waveguide structure along the transport direction. A circuit board electrically connected to a foot, the circuit board for transmitting a first test signal from a foot of the foot, wherein the circuit board is provided with at least one waveguide structure, and an input of the at least one waveguide structure The terminals are electrically connected to the pins to receive the first test message from the pins And the at least one waveguide structure guides the first test signal to be transmitted along a transmission direction to output a second test signal at an output end of the at least one waveguide structure, by adjusting the at least one waveguide structure along The cross-sectional area of the transmission direction is sized to modulate a cutoff frequency of the at least one waveguide structure associated with the first test signal. The circuit board of claim 10, wherein the at least one waveguide structure comprises: a plurality of vias connected by a first plane of the circuit board to a second plane, wherein the first plane and the second plane are a conductive portion is disposed in each of the two parallel surfaces of the circuit board; the first conductive plate is disposed on the first plane to be electrically connected to the first end of the conductive portion; And a second conductive plate disposed on the second surface to be electrically connected to the second end of the conductive portion. The circuit board of claim 11, wherein the conductive portion, the first conductive plate and the second conductive plate are the same conductive material. The circuit board of claim 12, wherein the conductive material is metal. The circuit board of claim 11, wherein the first plane and the second plane are different parallel faces of the inner or outer surface of the circuit board. The circuit board of claim 11, wherein the interval between each of the two via holes is less than 1/20 times the wavelength of the first test signal and/or the second test signal. The circuit board of claim 11, wherein the through holes are two rows of mutually parallel through holes, the conductive portions in the two parallel rows of the through holes, the first conductive The plate and the second conductive plate form a rectangular waveguide structure along the transport direction. The circuit board of claim 10, wherein the waveguide structure has a cutoff frequency of between 1 GHz and 300 GHz with respect to the first test signal. The circuit board of claim 10, wherein the cutoff frequency f _{c of} the at least one waveguide structure associated with the first test signal is expressed by the following formula: Where μ and ε are the magnetic permeability and dielectric constant of the medium of the circuit board, m, n=1, 2, 3, ... are respectively a positive integer, and T is the section of the waveguide structure along the transmission direction The distance of the area, L is the length of the cross-sectional area of the waveguide structure along the transport direction. The circuit board of claim 10, wherein the circuit board is used in a wafer test architecture to test a wafer.