TWI581270B - Data erasing methods - Google Patents

Description

Data erasure method

The present invention relates to a data erasing method, and more particularly to a data erasing method for flash memory.

In general, flash memory (such as NOR flash memory) is accompanied by a post-program operation to eliminate the over-erase of the erase operation on the bit line when performing the erase operation. Leakage phenomenon. However, when the system's power supply is turned off during the erase or post-program operation, the leakage may not be completely eliminated. Therefore, it has been developed to reduce the probability of occurrence of leakage by reducing the erase size of each memory sector (i.e., the number of word lines corresponding to one data erase). For example, a memory area includes 16 word lines, and each data erase is done through 4 word lines. In this way, the erasing operation of the memory area needs to be realized by 4 times of data erasing. However, reducing the erase size will lengthen the time of each erase operation. Therefore, how to perform the erase operation with an appropriate erase size and reduce the leakage phenomenon is an important issue in the technical field of the memory device.

Accordingly, the present invention provides a data erasing method for a memory device. The memory device includes a plurality of memory cells, complex digital lines, and complex bit lines configured as a memory array. Each memory cell is coupled to a set of interlaces The word line and the bit line. The memory cell is divided into a plurality of memory regions, and the memory cells in each memory region correspond to a predetermined number of word lines. The data erasing method comprises the steps of: initially setting the number of word lines for the erasing operation; performing a character line selecting operation to select a character line group in the target memory area as the target word according to the number of character lines. a line group; erasing the memory cells coupled to the target word line group by erasing the pulse wave; selecting a word line in the target word line group as the target word line, and sequentially Erasing verification is performed on a plurality of memory cells coupled to all of the byte groups; determining whether erasure verification performed on all the byte groups of the target word line is successful; when it is determined that any erasure verification is unsuccessful, the memory is All bit lines of the body array are sequentially subjected to over-erase verification; it is judged whether the soft programming operation caused by the over-erase verification has been performed; when it is judged that the soft programming operation has not been performed, it is determined whether the number of word lines is Less than a maximum number; and when it is determined that the number of word lines is less than the maximum number, the number of word lines is increased to re-execute the word line selection operation.

The present invention provides another data erasing method for a memory device. The memory device includes a plurality of memory cells, complex digital lines, and complex bit lines configured as a memory array. Each memory cell is coupled to a set of interlaced word lines and bit lines. The memory cell is divided into a plurality of memory regions, and the memory cells in each memory region correspond to a predetermined number of word lines. The data erasing method comprises the steps of: initially setting the number of word lines for the erasing operation; performing a character line selecting operation to select a character line group in the target memory area as the target word according to the number of character lines. a line group; erasing the memory cells coupled to the target word line group by erasing the pulse wave; selecting a target word line in the target word line group, and sequentially all the bytes thereof Multiple memory cells coupled for erasing Determining whether the erasure verification performed on all the tuples of the target word line is successful; when it is judged that any erasure verification is unsuccessful, all the bit lines of the memory array are sequentially over-erased and verified; Whether the soft programming operation caused by the over-erase verification has been performed; when it is judged that the soft programming operation has not been performed, it is judged whether the voltage value of the erased pulse wave is less than a maximum value or the pulse wave of the erased pulse wave is judged Whether the width is less than a maximum width; when it is judged that the voltage value of the erase pulse wave is less than the maximum value or the pulse width of the erase pulse wave is less than the maximum width, increase the voltage value or increase the pulse width to re-execute the erase Operation; when it is determined that the voltage value of the erase pulse wave is not less than the maximum value or it is determined that the pulse width of the erase pulse wave is not less than the maximum width, it is determined whether the number of word lines is less than a maximum number; when the word line is determined When the number is less than the maximum number, increase the number of word lines to re-execute the word line selection operation.

1‧‧‧ memory device

10‧‧‧ memory array

11‧‧‧ Address Decoder

12‧‧‧Write/read circuit

100‧‧‧ memory cells

BL0-BLY‧‧‧ bit line

S0~SN‧‧‧ memory area

WL0-WLX‧‧‧ character line

S200...S223‧‧‧ method steps

S316...S323‧‧‧ method steps

Fig. 1 shows an example of a memory device.

2A and 2B are views showing a control method for a memory device according to an embodiment of the present invention.

3A, 3B are diagrams showing a control method for a memory device in accordance with another embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

1 is a view showing a memory device according to an embodiment of the present invention. Set. Referring to FIG. 1, the memory device 1 includes a memory array 10, an address decoder 11, a write/read circuit 12, and a controller 13. The memory array 10 includes complex digital element lines WL0-WLX, complex bit lines BL0-BLY, and complex memory cells 100 arranged in a plurality of rows and a complex column. The word lines WL0-WLX and the bit lines BL0-BLY are interleaved with each other, and each memory cell 100 is coupled to a set of interleaved word lines and bit lines. These memory cells 100 are divided into a plurality of memory regions S0 to SN. Each memory region S0-SN includes a memory cell coupled to a predetermined number of word lines. For example, each memory region S0-SN includes a memory cell coupled to 16 word lines. When the address decoder 11 receives the address signal from the controller 13, the write/read circuit 12 cooperates with the address decoder 11 to perform a read and write operation on the selected memory cell. The controller 13 can change the execution parameters of the erase operation according to the result of the over-erase verification to eliminate the leakage phenomenon on the bit line caused by the excessive erase of the erase operation. In the embodiment of the present invention, the memory device 1 is a flash memory.

2A and 2B are diagrams showing a data erasing method according to an embodiment of the present invention. This mode is a data erasing method employed when the memory device 1 performs a plurality of erase operations. When the controller 13 selects a memory region as the target memory region, the memory cells coupled to the memory region are erased by the at least one erase pulse. For example, each memory region includes 16 word lines, and each erase operation performs data erasing on the memory cells coupled to the four word lines. Therefore, for a memory area, 4 erase operations need to be performed. In the embodiment of the present invention, the number N of the word lines corresponding to each data erasing (ie, 4 pieces, N=4) is referred to as the number N of character lines regarding the erasing operation (hereinafter referred to as a character element). The number of lines N). In other embodiments, the word line The number N can be 4 or 8 or 16 or more.

Please refer to the figures 1, 2A, and 2B at the same time. First, the controller 13 performs a pre-program operation on a target memory region in the memory array 10 (step S200) to program all the memory cells in the target memory region. The logic level is “0”. Next, the controller 13 also initially sets the number of word lines N to the preset value N0, and initially sets the voltage value V of the erase pulse for the erase operation to the preset value V0 and erases the pulse wave. The pulse width T is initially set to a preset value T0 (set N = N0, V = V0, T = T0) (step S201). In other embodiments, steps S200 and S201 can be exchanged with each other, that is, step S201 can be performed first and then S200 can be performed. Thereafter, the controller 13 performs a word line selection operation according to the address signal Addx and the number of word lines N (N=N0 at this time) to select a target word line group in a target memory area (ie, select A set of word lines having N0 word lines) (step S202). The controller 13 performs an erase operation on all the memory cells coupled to the target word line group according to the voltage value V (V=V0 at this time) and the pulse width T (at this time T=T0) (step S203), that is, The controller 13 writes a signal to the complex memory cell corresponding to the target word line group by the erase pulse wave having the voltage value V and the pulse width T through the write/read circuit 12, that is, the target word line The complex memory cells corresponding to the group are programmed to logic level "1". After erasing the target word line group, the controller 13 selects the first word line in the target word line group as the target word line and controls the write/read circuit 12 in units of bytes. A plurality of memory cells coupled to all the byte groups of the target word line are sequentially read to perform erasure verification, and it is judged whether or not the erase verification is successful (step S204). When the signals read by the plurality of memory cells in the byte are all logic level "1", the controller 13 determines that the erase verification is successful. Controller 13 then determines that all of the bytes in the target word line are Otherwise, the verification is successful (step S205). If all the bytes in the target word line are verified by erasing, the controller 13 then determines whether the address of the target word line has reached the last address of the target word line group (step S206). If the last address has not been reached, the controller 13 selects the next word line as the target word line (step S207), and the method returns to step S204 to continue the erase verification.

If the last address has been reached, the controller 13 performs a post-program operation on all the memory cells coupled to the target word line group (step S208) to eliminate the leakage on the bit line caused by the excessive erasing of the erase operation. That is, excessive erase verification and soft programming operations are performed on the target word line group. Thereafter, the controller 13 determines whether the address of the target word line group has reached the last address of the target memory area (step S209). If the last address has not been reached, the controller 13 sets Addx=Addx+N (step S210), and the method returns to step S202 to perform the next character line selection operation to select another word in the target memory area. The meta-line group is used as the target character line group. If the last address has been reached, the method ends (step S211).

In an embodiment, when the controller 13 determines in step S205 that any of the byte erase verifications in the target word line is unsuccessful, the controller 13 selects all the bit lines in the memory array 10 one by one. BL0-BLY performs over-erase verification to detect if there is any leakage on the bit line BL0-BLY. In detail, the controller 13 performs over-erase verification on a target bit line in the memory array 10 (step S212A) and judges whether or not the verification is successful (step S212B). When the controller 13 determines that the over-erase verification is unsuccessful, the controller 13 further defines the memory cell that failed the verification, and performs a soft programming operation on the memory cell that failed the verification (step S212C) to adjust the threshold voltage of the memory cell. value. At step S212C After the soft programming operation, the method returns to step S212A, and the controller 13 performs over-erase verification on the target bit line again, and again determines whether the verification is successful. When the controller 13 judges that the over-erase verification is successful, the controller 13 judges whether or not the target bit line is the last bit line (step S212D). When the controller 13 judges that the target bit line is not the last bit line, the controller 13 selects the next bit line as the target bit line (step S212E), and the method returns to step S212A. When the controller 13 judges that the target bit line is the last bit line, the controller 13 judges whether or not the soft program operation of step S212C has been performed (step S215). According to the above, the controller 13 performs over-erase verification on a pair of all bit lines. When a bit line is not verified by over-erase, the memory cell that failed the verification is further defined, and a soft programming operation is performed thereon to adjust the threshold voltage value of the memory cell.

When the controller 13 judges that the soft programming operation of step S212C has been performed, the controller 13 determines whether the current number of character lines N is greater than the minimum value Nmin (N > Nmin?) (step S216). When the controller determines that the current number of character lines N is greater than the minimum value Nmin, the controller 13 decreases the number N of character lines to be equal to N2 (N = N2) (step S217). Next, the method returns to step S202, and the controller 13 performs the character line selection operation again to adjust the original target word line according to the address signal Addx and the changed number of word lines N (in this case, N=N2). The number of word lines in the group (ie, a string of word lines having N2 word lines is selected again as the target word line group according to the address signal Addx). When the controller 13 determines that the current number of character lines N is not greater than the minimum value Nmin, the controller 13 determines whether the voltage value V is greater than the minimum value Vmin or determines whether the pulse width T is greater than the minimum value Tmin (V>Vmin or T>). Tmin?) (step S218). When the controller 13 determines that the voltage value V is greater than the minimum value Vmin or determines that the pulse width T is greater than the minimum value At Tmin, the controller 13 reduces the voltage value V to be equal to V2 or reduces the pulse width T to be equal to T2 (step S219). Next, the method returns to step S202, and the controller 13 first selects the target word line group according to the address signal Addx and the number of word lines N (in this case, N=N0) (step S202), and then according to the changed voltage value V. The erase operation is performed on all the memory cells of the target word line group with the pulse width T (in this case, V = V2 or T = T2) (step S203). In addition, when the controller 13 determines that the voltage value V is not greater than the minimum value Vmin or determines that the pulse width T is not greater than the minimum value Tmin, the method also returns to step S202. At this time, the controller 13 according to the address signal Addx according to the address first. And after the number of original word lines N (N=N0 at this time), the target word line group is selected (step S202), and then according to the original voltage value V and the original pulse width T (at this time, V=V0 and T=T0) All memory cells of the target word line group are erased (step S203).

When the controller 13 judges that the soft programming operation of step S212C has not been performed, the controller 13 determines whether the current number of character lines N is smaller than the maximum value Nmax (N < Nmax?) (step S220). When the controller 13 judges that the current number of character lines N is smaller than the maximum value Nmax, the controller 13 increments the number of word lines N to be equal to N3 (step S221). Next, the method returns to step S202, and the controller 13 performs the character line selection operation again to adjust the original target word line according to the address signal Addx and the changed number of word lines N (in this case, N=N3). The number of word lines in the group (ie, a set of word lines having N3 word lines are selected again as the target word line group according to the address signal Addx). When the controller 13 determines that the current number of character lines N is not smaller than the maximum value Nmax, the controller 13 determines whether the voltage value V is smaller than the maximum value Vmax or determines whether the pulse width T is smaller than the maximum value Tmax (V < Vmax or T < Tmax). ?) (step S222). When the controller 13 determines When the voltage value V is smaller than the maximum value Vmax or it is judged that the pulse width T is smaller than the maximum value Tmax, the controller 13 increases the voltage value V to be equal to V3 or increases the pulse width T to be equal to T3 (step S223). Next, the method returns to step S202, and the controller 13 first selects the target word line group according to the address signal Addx and the number of word lines N (in this case, N=N0) (step S202), and then according to the changed voltage value V. And erase the pulse width T (at this time V = V3 or T = T3) to erase all the memory cells of the target word line group. In addition, when the controller 13 determines that the voltage value V is not less than the maximum value Vmax or determines that the pulse width T is not less than the maximum value Tmax, the method also returns to step S202. At this time, the controller 13 first according to the address signal Addx and After the number of original word lines N (N=N0 at this time), the target word line group is selected (step S202), and then according to the original voltage value V and the original pulse width T (at this time, V=V0 and T=T0) All the memory cells of the target word line group perform an erase operation (step S203).

In steps S212A-S212E of performing over-erase verification on all bit lines BL0-BLY of a pair of memory arrays, a detection voltage is applied to the selected word line group, and at this time, the controller 13 detects whether the target bit line is With current, to determine whether there is leakage. In an embodiment of the invention, the sense voltage is a voltage greater than 0 volts. Since the memory device 1 may operate in different environments (eg, different ambient temperatures), the same detection voltage may not necessarily cause leakage or a different degree of leakage under different operating environments. And a detection voltage greater than 0 volts is relatively easy to cause leakage on the bit line for various operating environments. Therefore, the embodiment of the present invention uses a detection voltage greater than 0 volts to be a more stringent condition for detecting leakage.

According to the above embodiment, the number of word lines used in the erase operation of the present invention is variable, which can be adaptive with the current leakage state on the bit line. increase or decrease. In this way, not only can the probability of leakage caused by the erasing operation be reduced, but also the time required to perform the erasing operation can be more consistent with the current operating state of the memory device 1.

3A, 3B are diagrams showing a data erasing method according to another embodiment of the present invention. The data erase method of FIGS. 3A and 3B is the same as the data erase method of FIGS. 2A and 2B, and the same steps are denoted by the same symbols. The data erasing method of FIGS. 3A and 3B has substantially the same steps as the data erasing method of FIGS. 2A and 2B except for the steps subsequent to the soft programming operation (step S215). The same steps S200-S215 are omitted here. Please refer to the figures 1 , 3A, and 3B at the same time. When it is determined in step S215 that the soft programming operation of step S212C has been performed, the controller 13 determines whether the voltage value V is greater than the minimum value Vmin or determines whether the pulse width T is greater than or greater than The minimum value Tmin (V>Vmin or T>Tmin?) (step S316). When the controller 13 determines that the voltage value V is greater than the minimum value Vmin or determines that the pulse width T is greater than the minimum value Tmin, the controller 13 decreases the voltage value V to be equal to V2 or reduces the pulse width T to be equal to T2 (step S317). Next, the method returns to step S202, and the controller 13 first selects the target word line group according to the address signal Addx and the number of word lines N (in this case, N=N0) (step S202), and then according to the changed voltage value V. The erase operation is performed on all the memory cells of the target word line group with the pulse width T (in this case, V = V2 or T = T2). When the controller 13 determines that the voltage value V is not greater than the minimum value Vmin or determines that the pulse width T is greater than the minimum value Tmin, the controller 13 determines whether the current number of character lines N is greater than the minimum value Nmin (N>Nmin?) (Step S318). When the controller 13 judges that the current number of character lines N is greater than the minimum value Nmin, the controller 13 decreases the number N of character lines to be equal to N2 (step S319). Then, the method returns to step S202, The controller 13 performs the character line selection operation again to adjust the number of word lines in the original target character line group according to the address signal Addx and the changed number of word lines N (in this case, N=N2) ( That is, a group of word lines having N2 word lines are selected again as the target word line group according to the address signal Addx. In addition, when the controller 13 determines that the current number of character lines N is not greater than the minimum value Nmin, the method also returns to step S202. At this time, the controller 13 first according to the address signal Addx and the number of original word lines N (this When N=N0) selects the target word line group (step S202), and then according to the original voltage value V and the original pulse width T (at this time, V=V0 and T=T0), all the memory of the target character line group. The cell performs an erase operation (step S203).

When the controller 13 determines in step S215 that the soft programming operation of step S212C has not been performed, the controller 13 determines whether the voltage value V is smaller than the maximum value Vmax or determines whether the pulse width T is smaller than the maximum value Tmax (V < Vmax or T). <Tmax?) (step S320). When the controller 13 determines that the voltage value V is smaller than the maximum value Vmax or determines that the pulse width T is smaller than the maximum value Tmax, the controller 13 increases the voltage value V to be equal to V3 or increases the width T to be equal to T3 (step S321). . Next, the method returns to step S202, and the controller 13 first selects the target word line group according to the address signal Addx and the number of word lines N (in this case, N=N0) (step S202), and then according to the changed voltage value V. With the pulse width T (in this case, V = V3 or T = T3), all the memory cells coupled to the target word line group are erased. When the controller 13 determines that the voltage value V is not less than the maximum value Vmax or determines that the pulse width T is not less than the maximum value Tmax, the controller 13 determines whether the current number of character lines N is smaller than the maximum value Nmax (N < Nmax? (Step S322). When the controller 13 judges that the current number of character lines N is smaller than the maximum value Nmax, the controller 13 increments the number N of character lines to be equal to N3 (step S323). Then, the method is back Go to step S202, the controller 13 performs the character line selection operation again to adjust the words in the original target character line group according to the address signal Addx and the changed number of word lines N (in this case, N=N3). The number of element lines (ie, a set of word lines having N3 word lines are selected as the target word line group according to the address signal Addx). In addition, when the controller 13 determines that the current number of character lines N is not less than the maximum value Nmax, the method also returns to step S202. At this time, the controller 13 first according to the address signal Addx and the number of original word lines N (this When N=N0) selects the target word line group (step S202), and then according to the original voltage value V and the original pulse width T (at this time, V=V0 and T=T0), all the memory of the target character line group. The cell performs an erase operation (step S203).

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

S200...S223‧‧‧ method steps

Claims (12)

A data erasing method for a memory device, the memory device comprising a plurality of memory cells, a complex digital element line, and a plurality of bit lines configured as a memory array, each of the memory cells coupled to a set of interlaced The word line and the bit line, the memory cells are divided into a plurality of memory regions, and each of the memory cells in the memory region corresponds to a predetermined number of the word lines, and the data erasing method The method includes: initially setting a number of word lines for an erasing operation; performing a word line selecting operation to select a character line group in a target memory area as a target word line according to the number of the word lines; The erase operation is performed on the memory cells coupled to the target word line group by a wipe pulse wave; a word line in the target word line group is selected as a target word line, and Performing a erase verification on a plurality of memory cells coupled to all of the bytes in sequence; determining whether the erase verification performed on all the byte groups of the target word line is successful; When the erase verification is not successful, All the bit lines of the memory array are sequentially subjected to an over-erase verification; it is judged whether a soft programming operation that has not been performed by the excessive erase verification has been performed; when it is judged that the soft programming operation has not been performed, Determining whether the number of character lines is less than a maximum number; and when determining that the number of character lines is less than the maximum number, increasing the word line Quantity to re-execute the character line selection operation. The method for erasing data as described in claim 1 further includes: determining whether a voltage value of the erased pulse wave is less than a maximum value or determining when the number of the word line is not less than the maximum number. Whether a pulse width of the erase pulse wave is less than a maximum width; and determining that the voltage value of the erase pulse wave is less than the maximum value or determining that the pulse wave width of the erase pulse wave is less than the maximum width When the voltage value is increased or the pulse width is increased, the erase operation is re-executed. The method for erasing data as described in claim 1 further includes: determining whether the number of the character lines is greater than a minimum number when determining that the soft programming operation has been performed; and determining the word line When the number is greater than the minimum number, the number of word lines is reduced to re-execute the word line selection operation. The method for erasing data as described in claim 3, further comprising: determining whether a voltage value of the erased pulse wave is greater than a minimum value or judging when determining that the number of the character line is not greater than the minimum number Whether a pulse width of the erase pulse wave is greater than a minimum width; and determining that the voltage value of the erase pulse wave is greater than the minimum value or determining that the pulse wave width of the erase pulse wave is greater than the minimum width At this time, the voltage value is reduced or the pulse width is reduced to re-execute the erase operation. The data erasing method of claim 1, wherein when it is determined that any of the erasure verifications are unsuccessful, the step of performing the over-erasing verification on all the bit lines of the memory array is sequentially performed. The method includes: performing the over-erase verification on a target bit line of the memory array; Determining whether the over-wipe verification is successful; when it is determined that the over-erase verification is unsuccessful, defining the memory cells that have failed to erase the verification and performing the soft programming operation on the memory cells; when determining the over-wiping When the verification succeeds, it is determined whether the target bit line is the last bit line of the memory array; and when it is determined that the target bit line is not the last bit line of the memory array, the next bit is selected The line is taken as the target bit line; wherein, when it is determined that the target bit line is the last bit line of the memory array, a step of determining whether the soft programming operation has been performed is performed. The method for erasing data as described in claim 1 further includes: determining that the address of the target word line has reached the last bit of the target character line group when it is determined that the erasure verification is successful. And determining, when the address of the target word line has not reached the last address of the target character line group, selecting the next character line of the target character line group as the target word line . The data erasing method described in claim 6 further includes: when determining that the address of the target word line has reached the last address of the target character line group, coupling the target character The memory cells of the line group perform a post-program operation; determine whether the address of the target word line group has reached the last address of the target memory region; and when it is determined that the address of the target word line group has not yet been When the last address of the target memory area is reached, the character line selection operation is performed to select another character line group in the target memory area according to the number of the character lines as the Target character line group. A data erasing method for a memory device, the memory device comprising a plurality of memory cells, a complex digital element line, and a plurality of bit lines configured as a memory array, each of the memory cells coupled to a set of interlaced The word line and the bit line, the memory cells are divided into a plurality of memory regions, and each of the memory cells in the memory region corresponds to a predetermined number of the word lines, and the data erasing method The method includes: initially setting a number of word lines for an erasing operation; and performing a word line selecting operation to select a character line group in the target memory area as a target character according to the number of the word lines a line group; performing the erasing operation on the memory cells coupled to the target word line group by using a wipe pulse wave; selecting a target word line in the target word line group, and sequentially Performing a erase verification on a plurality of memory cells coupled to all of the byte groups; determining whether the erase verifications performed on all the byte groups of the target word line are successful; determining that any of the erase verifications are unsuccessful Memory array All the bit lines are sequentially subjected to an over-erase verification; it is judged whether a soft programming operation that has not been performed by the excessive erase verification has been performed; when it is judged that the soft programming operation has not been performed, the wipe is judged Whether or not a voltage value of the pulse wave is less than a maximum value or determining whether a pulse width of the erase pulse wave is less than a maximum width; and determining that the voltage value of the erase pulse wave is less than the maximum value or determining the When the width of the pulse wave of the erase pulse is less than the maximum width, increase the voltage value or increase the pulse width to re-execute the erase operation; when it is determined that the voltage value of the erase pulse is not less than the maximum And determining whether the pulse width of the erase pulse wave is not less than the maximum width, determining whether the number of the word lines is less than a maximum number; and when determining that the number of the word lines is less than the maximum number, increasing the word The number of meta lines to re-execute the character line selection operation. The method for erasing data as described in claim 8 further includes: determining whether the voltage value of the erase pulse wave is greater than a minimum value or determining the erase when determining that the soft programming operation has been performed. Whether the pulse width of the pulse wave is greater than a minimum width; when it is determined that the voltage value of the erase pulse wave is greater than the minimum value or determining that the pulse wave width of the erase pulse wave is greater than the minimum width, reducing the pulse width The voltage value or the pulse width is reduced to re-execute the erase operation; when it is determined that the voltage value of the erase pulse wave is not greater than the minimum value or the pulse width of the erase pulse wave is not greater than At the minimum width, it is determined whether the number of word lines is greater than a minimum number; and when it is determined that the number of word lines is greater than the minimum number, the number of word lines is reduced to re-execute the word line selection operation. The data erasing method of claim 8, wherein when it is determined that any of the erasure verifications are unsuccessful, the step of performing the over-erasing verification on all the bit lines of the memory array is sequentially performed. The method includes: performing the excessive erase verification on a target bit line of the memory array; determining whether the excessive erase verification is successful; When it is determined that the over-erasing verification is unsuccessful, the memory cells that have failed to erase the verification failure are defined and the soft programming operation is performed on the memory cells; when it is determined that the excessive erase verification is successful, the target bit is determined. Whether the meta-line is the last bit line of the memory array; and when it is determined that the target bit line is not the last bit line of the memory array, the next bit line is selected as the target bit line; Wherein, when it is determined that the target bit line is the last bit line of the memory array, then a step of determining whether the soft programming operation caused by the excessive erase verification has been performed is performed. The control method of claim 8 further includes: determining that the address of the target word line has reached the last address of the target character line group; And when it is determined that the address of the target word line has not reached the last address of the target character line group, the next character line of the first target element group is selected as the target word line. For example, the data erasing method described in claim 11 further includes: when determining that the address of the target word line has reached the last address of the target character line group, coupling the target character The memory cells of the line group perform a post-program operation; determine whether the address of the target word line group has reached the last address of the target memory region; and when it is determined that the address of the target word line group has not yet been When the last address of the target memory area is reached, the character line selection operation is performed to select another character line group in the target memory area according to the number of the character lines as the Target character line group.