TWI556252B - Memory test system and method thereof - Google Patents

Description

Memory test system and test method thereof

The invention relates to a test system and a test method, and in particular to a memory test system and a test method thereof.

Double Data Rate (DDR) memory is a revolutionary memory technology based on Synchronous Dynamic Random Access Memory (SDRAM) that provides a high performance, low cost memory solution. And, in the new generation of low-power dynamic memory (Low Power DRAM) specifications, it provides lower power, higher speed operation capabilities to meet the performance requirements of today's high-speed systems.

In the memory test, the traditional memory unit can generate a valid data window according to the external clock signal, and the data is taken by the memory tester for testing. However, as the speed of operation of the memory increases, the effective period of the data window is shortened. And the delay time between the clock signal and the data signal channel (data output) is relatively increased by the influence of temperature, volume and pressure (referred to as PVT). The data window generated by the memory unit is too large in the range of displacement error generated during the validity of the data. Therefore, the memory tester is difficult to capture correctly. The effective data of the data window displaced by the influence of PVT causes the failure of the memory test.

In view of this, the present invention provides a memory test system and a test method thereof, which can reduce the range of data window displacement errors to avoid the failure of the memory test.

The memory testing system of the present invention includes a memory tester and a memory unit. Among them, the memory tester generates a data selection communication number during the test. The memory unit detects the enablement of the data selection communication number during the test and outputs a test data signal having the stored test data to the memory tester. The memory tester determines whether the memory unit is damaged based on the test data.

In an embodiment of the invention, the memory unit includes a data selection communication number channel, a first input buffer, a data signal channel, and a first in first out register. The data selection communication number channel is used to receive the data selection communication number. The first input buffer is coupled to the data selection communication number channel for temporarily storing the data selection communication number. The data signal channel is used to output test data signals. The first in first out buffer is coupled to the first input buffer and the data signal channel for receiving the test data signal during the test and detecting whether the data selection number provided by the first input buffer is enabled. When the data selection communication number is enabled, the FIFO register transmits the test data signal to the data signal channel for output to the memory tester.

In an embodiment of the invention, the memory unit further includes a clock channel, a second input buffer, and a delay controller. Clock channel for receiving time signals number. The second input buffer is coupled to the clock channel for temporarily storing the clock signal. The delay controller is coupled to the second input buffer and the first-in first-out register for adjusting the clock signal and providing the first-in-first-out register. The FIFO register receives the read data signal with the read data during the reading, and the FIFO register transmits the read data signal to the data signal channel according to the clock signal.

In an embodiment of the invention, the memory tester outputs a write data signal having test data to the memory unit to store the test data to the memory unit.

In an embodiment of the invention, the memory tester described above includes a comparator. The comparator is configured to determine whether the test data obtained by the memory unit is equal to that when the memory unit is written, and to determine whether the memory unit is damaged.

The memory testing method of the present invention is suitable for testing a memory unit by an electronic device. This method generates a data selection communication number and transmits it to the memory unit during the test. Moreover, during the test, the detection of the data selection communication number is enabled, and the memory unit outputs a test data signal having the stored test data, and determines whether the memory unit is damaged according to the test data.

In an embodiment of the invention, the memory unit includes a data selection communication number channel and a data signal channel. The step of outputting the test data by the memory unit to enable the test data signal with the stored test data includes the detection of whether the data selection number received by the data selection channel is enabled during the test. And, when the data selection communication number is enabled, the test data signal is transmitted to the data signal channel.

In an embodiment of the invention, the memory unit further includes a clock channel. The memory test method further includes transmitting the read data signal with the read data to the data signal channel according to the clock signal received by the clock channel during the reading.

In an embodiment of the invention, before the step of generating the data selection communication number and transmitting to the memory unit, the method includes: outputting the written data signal with the test data to the memory unit to store the test data to the memory unit.

In an embodiment of the invention, the step of determining whether the memory unit is damaged according to the test data comprises determining whether the test data obtained by the memory unit is equal to when the memory unit is written, and determining whether the memory unit is damage.

Based on the above, the memory test system of the present invention can replace the clock signal to generate an effective data window by selecting a communication number that is closer to the data signal channel. Thereby, the delay time which is relatively increased by the influence of PVT can be reduced, and the displacement error of the data window can be reduced. Successfully capture valid data without completing the test cost to complete the memory test.

The above described features and advantages of the present invention will be more apparent from the following description.

100‧‧‧Memory Test System

110‧‧‧Memory Tester

120‧‧‧ memory unit

121‧‧‧Information selection communication number channel

122, 126‧‧‧ input buffer

123‧‧‧Information signal channel

124‧‧‧First In First Out Register

125‧‧‧Delay controller

127‧‧‧clock channel

CLK, CLK'‧‧‧ clock signal

D0, D1, D2, D3‧‧‧ test data

DQR‧‧‧ reading data signal

DQS‧‧‧ data selection communication number

DQT, DQT1, DQT2‧‧‧ test data signal

DQW‧‧‧ write data signal

P1, P2‧‧‧ processing path

T‧‧ cycle

T1, t2, t3, t4, t5‧‧‧ time

S410, S420‧‧‧ steps of the memory test method

FIG. 1 is a schematic diagram of a memory test system according to an embodiment of the invention.

2 is a data selection communication number and test capital according to an embodiment of the invention. Waveform of the signal.

FIG. 3 is a schematic diagram of a memory unit according to an embodiment of the invention.

4 is a flow chart of a method for testing a memory according to an embodiment of the invention.

First, please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory test system according to an embodiment of the invention. In the present embodiment, the memory test system 100 includes a memory tester 110 and a memory unit 120. The memory unit 120 to be tested may be, for example, double data rate (DDR) memory, second generation double data rate (DDR2) memory, low power second generation double data rate (LPDDR2) memory or Three generations of double data rate (DDR3) memory and other memory devices.

In FIG. 1, the memory tester 110 can generate a data selection communication number DQS during the test. Moreover, the memory tester 110 can transmit the data selection communication number DQS to the memory unit 120. In detail, the memory tester 110 outputs the write data signal DQW having the test data DT to the memory unit 120 in advance. Moreover, the tested memory cell in the memory unit 120 can store the test data DT (logic 0 or 1) according to the write data signal DQW for subsequent memory testing. The number of the measured memory cells in the memory unit 120 is determined/determined according to actual test requirements, and the embodiment of the present invention is not limited.

Next, during testing, the memory tester 110 can generate an enabled data selection communication number DQS. And transmitted to the memory unit 120 to trigger the memory unit 120 to output the test data DT stored in the tested memory cell.

In addition, the memory unit 120 is coupled to the memory tester 110. The memory unit 120 continuously detects the enablement of the data selection communication number DQS during the test and outputs the test data signal DQT having the stored test data DT to the memory tester 110. The memory tester 110 can determine whether the memory unit 120 is damaged based on the test data DT. In detail, when the data selection communication number DQS is enabled, the memory unit 120 outputs the test data signal DQT including the test data DT stored at the test memory cell to the memory tester 110 for memory. The body tester 110 determines the correctness of the test data DT stored via the memory unit 120, thereby determining whether the memory unit 120 (the measured memory cell) is damaged. For example, the memory tester 110 can include a comparator. The comparator can be used to determine whether the test data DT obtained by the memory unit 120 is equal to when it is previously written to the memory unit 120 via the write data signal DQW. If the obtained test data DT is the same as when the memory unit 120 is previously written, the memory tester 110 can determine that the memory unit 120 is normal. If the obtained test data DT is different from that written in advance to the memory unit 120, the memory tester 110 can determine that the memory unit 120 is damaged.

The following examples are used to further illustrate the relationship between the data selection communication number and the test data signal. 2 is a waveform diagram of a data selection communication number and a test data signal according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, the test data signals DQT1 and DQT2 in different situations under the influence of the PVT are illustrated. In the case where the memory unit 120 operates faster (for example, when the influence of the PVT is small), the memory unit 120 can output the test data signal DQT1 in response to the data selection communication number DQS generated by the memory tester 110. Operating in memory unit 120 In the case of a slower situation (for example, when the influence of the PVT is large), the memory unit 120 can output the test data signal DQT2 in response to the data selection communication number DQS.

Specifically, in FIG. 2, at time t1, the data selection communication number DQS starts to be enabled. In other words, at time t1, the memory tester 110 enables the data selection communication number DQS and transmits it to the memory unit 120. After the data selection communication number DQS is enabled to pass the time T2 of the period T, in the case of faster operation, at time t3, the memory unit 120 starts to react to the data selection communication number DQS and sequentially outputs the test data through the test data signal DQT1. D0~D3. In the case of slow operation, at time t4, the memory unit 120 starts to react to the data selection communication number DQS and sequentially outputs the test data D0~D3 through the test data signal DQT2. As shown in FIG. 2, the period T of the data selection communication number DQS may be, for example, 1.875 ns. The difference between time t3 and time t4 (displacement error) is approximately one quarter (0.46875 ns) of the data selection communication number DQS period. In contrast to the conventional method of using the clock signal to trigger the test data signal, the data error may exceed 6.7 ns or more in the case of different degrees of PVT influence. The memory test system 100 of the embodiment of the present invention. Reduces the displacement error caused by the influence of PVT. Therefore, as shown in FIG. 2, with the test data D0 as an example, the memory tester 110 can be operated faster (test data signal DQT1) or slower (test data signal DQT2) regardless of the memory unit 120 being affected by PVT. During the period from time t4 to time t5, the correct test data D0 is captured to overcome the defect that the memory tester is not affected by the PVT and the effective data cannot be correctly retrieved.

FIG. 3 is a schematic diagram of a memory unit according to an embodiment of the invention. Figure. Referring to FIG. 3, the processing path of the memory unit 120 when performing the test operation and the read operation is indicated in FIG. In this embodiment, the memory unit 120 includes a data selection communication number channel 121, an input buffer 122, a data signal channel 123, a first-in first-out register 124, a delay controller 125, an input buffer 126, and a clock channel 127. . The memory unit 120 of the present embodiment takes different processing paths (processing paths P1 and P2) for performing signals during the test for performing the memory test operation and during the reading for performing the normal read operation on the stored data. The transmission is to reduce the distance of the signal transmission during the memory test, and reduce the displacement error caused by the PVT effect of the data window.

Referring to FIG. 1 and FIG. 3, in the embodiment, during the test, the memory tester 110 can generate the data selection communication number DQS and transmit it to the data selection communication number channel 121 of the memory unit 120. Next, as shown in the processing path P1, the data selection communication number channel 121 can receive the data selection communication number DQS and transmit it to the input buffer 122. The input buffer 122 is coupled to the data selection communication number channel 121, and temporarily stores the data selection communication number DQS received by the data selection communication number channel 121.

In addition, during the test, the memory unit 120 can transmit the test data signal DQT including the test data DT stored at the time of the measured memory cell to the FIFO register 124. The FIFO register 124 is coupled to the input buffer 122 and the data signal channel 123. As shown in the processing path P1, the FIFO register 124 can receive the test data signal DQT during the test and continuously detect whether the data selection communication number DQS provided by the input buffer 122 is enabled. When the data selection communication number DQS is enabled, the first-in first-out register 124 can be transmitted according to the data selection communication number DQS. The test data signal DQT of the test data DT is sent to the data signal channel 123 to output the test data signal DQT to the memory tester 110 to determine whether the memory unit 120 (the measured memory cell) is damaged.

On the other hand, during the reading period, as shown in the processing path P2, the memory unit 120 can receive the external clock signal CLK from the clock channel 127 to trigger the output of the read data signal DQR having the read data DR. Specifically, the clock channel 127 can receive the clock signal CLK and transmit it to the input buffer 126. The input buffer 126 is coupled to the clock channel 127. The input buffer 126 can temporarily store the clock signal CLK received by the clock channel 127. Moreover, the delay controller 125 is coupled to the input buffer 126 and the first in first out register 124. The delay controller 125 can adjust the clock of the clock signal CLK to match the circuit structure of the memory unit 120, and provide the adjusted clock signal CLK' to the FIFO register 124.

In addition, during reading, the memory unit 120 can transmit the read data signal DQR including the stored read data DR to the FIFO register 124. As shown in the processing path P2, the FIFO register 124 can receive the read data signal DQR having the read data DR during the read period, and continuously detect the clock signal CLK' provided by the input buffer 126. Therefore, the FIFO register 124 can transmit the read data signal DQR to the data signal channel 123 according to the clock signal CLK', for example, output the read data signal DQR to the external memory controller.

4 is a flow chart of a method for testing a memory according to an embodiment of the invention. Referring to FIG. 1 and FIG. 4 simultaneously, the memory testing method of the present embodiment is applicable to the memory testing system 100 of FIG. 1, and the following is a memory testing system 100. The item describes various steps of the memory test method of the embodiment of the present invention.

In step S410, the memory tester 110 may generate a data selection communication number DQS and transmit it to the memory unit 120 during the test.

In step S420, during the test, the memory unit 120 can detect the enablement of the data selection communication number DQS, and the memory unit 120 outputs the test data signal DQT having the stored test data DT to the memory tester 110. Moreover, the memory tester 110 can determine whether the memory unit 120 is damaged according to the test data. The details of the above steps S410 and S420 can be referred to the embodiment of FIG. 1 to FIG. 3, and details are not described herein again.

In summary, the memory test system and the test method thereof of the present invention, when performing a memory test, the memory unit can select a communication number that is closer to the data signal channel to replace the clock signal to generate valid data. window. Thereby, the delay time inside the memory unit can be shortened to reduce the data window displacement error which is relatively increased by the influence of PVT. Successfully capture valid data without completing the test cost to complete the memory test.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Memory Test System

110‧‧‧Memory Tester

120‧‧‧ memory unit

DQS‧‧‧ data selection communication number

DQT‧‧‧ test data signal

DQW‧‧‧ write data signal

Claims (10)

A memory testing system includes: a memory tester that generates a data selection communication number during a test period; and a memory unit coupled to the memory tester to detect the data selection communication number during the test period And outputting a test data signal having a stored test data to the memory tester, the memory tester determining whether the memory unit is damaged according to the test data, wherein the memory unit operates faster When the response of the data selection communication number is output, the response time of the test data signal is less than one-half of the period of the data selection communication number, and when the memory unit operates slowly, the reaction is selected in the data selection communication. The response time of the enable signal outputting the test data signal is less than the period of the data selection communication number. The memory test system of claim 1, wherein the memory unit comprises: a data selection communication number channel, receiving the data selection communication number; a first input buffer coupled to the data selection communication number Channel, temporarily storing the data selection communication number; a data signal channel outputting the test data signal; and a first in first out register coupled to the first input buffer and the data signal channel, receiving the data during the test Testing the data signal and detecting whether the data selection communication number provided by the first input buffer is enabled. When the data selection communication number is enabled, the FIFO register transmits the test data signal to the data signal. Channel to output to the memory tester. The memory test system of claim 2, wherein the memory unit further comprises: a clock channel for receiving a clock signal; a second input buffer coupled to the clock channel, temporarily storing the time a delay signal, coupled to the second input buffer and the FIFO register, to adjust the clock signal and provide the FIFO to the FIFO, wherein the advanced The first-out register receives a read data signal having a read data, and the first-in first-out register transmits the read data signal to the data signal channel according to the clock signal. The memory test system of claim 1, wherein the memory tester outputs a write data signal having the test data to the memory unit to store the test data to the memory unit. The memory test system of claim 1, wherein the memory tester comprises: a comparator for determining whether the test data obtained by the memory unit is equal to writing to the memory unit. And according to whether the memory unit is damaged. A memory testing method for testing a memory unit by an electronic device, the method comprising the steps of: generating a data selection number during a test and transmitting to the memory unit; and detecting the data during the test The data selection communication number is enabled, and the memory unit outputs a test data signal having the stored test data, and according to the test The data is used to determine whether the memory unit is damaged. When the memory unit operates faster, the reaction time for outputting the test data signal in response to the data selection communication number is less than two-period of the period of the data selection communication number. First, when the memory unit operates slowly, the reaction time for outputting the test data signal in response to the data selection communication number is less than the period of the data selection communication number. The memory test method of claim 6, wherein the memory unit includes a data selection communication number channel and a data signal channel, and detecting the enabling of the data selection communication number by the memory unit The step of outputting the test data signal having the stored test data includes: detecting whether the data selection communication number received by the data selection communication channel is enabled during the test; and enabling the communication number when the data is selected The test data signal is transmitted to the data signal channel. The memory test method of claim 7, wherein the memory unit further comprises a clock channel, and the method further comprises: transmitting, according to a clock signal received by the clock channel during a reading period; A read data signal of the read data is sent to the data signal channel. The memory test method of claim 6, wherein before the step of generating the data selection communication number and transmitting to the memory unit, the method comprises: outputting a write data signal having the test data to the memory The unit stores the test data to the memory unit. The method for testing a memory as described in claim 6 of the patent application, wherein The step of determining whether the memory unit is damaged by the test data comprises: determining whether the test data obtained by the memory unit is equal to being written to the memory unit, and determining whether the memory unit is damaged.