TWI553926B - Resistive memory and method of fabricating the same - Google Patents

Description

Resistive memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a resistive memory and a method of fabricating the same.

In recent years, resistive memory (such as Resistive Random Access Memory (RRAM)) has developed extremely rapidly and is currently the most attractive structure of future memory. Resistive memory is ideal for low-power, high-speed operation, high density, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) process technology, making it ideal for next generation non-volatile Memory component.

Current resistive memories typically include opposing upper and lower electrodes and a dielectric layer between the upper and lower electrodes. Before the current resistive memory is operated, a forming process is first performed to apply a high positive bias to the resistive memory to cause oxygen vacancy or oxygen ions in the dielectric layer. (electrical ion) forms a conductive filament. When a reset operation is performed, a negative bias is applied to the resistive memory so that the conductive filament is broken. At this point, the oxygen vacancies adjacent to the upper electrode are refilled (or the oxygen ions are off the current path) such that the filament is disconnected adjacent the upper electrode. On the other hand, when a current set-up operation is performed on the resistive memory, a positive bias is applied to the resistive memory so that oxygen vacancies or oxygen ions are again generated in the dielectric layer to reform the conductive filament.

Since the conventional RRAM process defines a memory cell by an etching process, it is easy to form a dangling bond on the sidewall of the memory cell during the plasma step or the wet cleaning step in the etching process. ). During the reset process, the above floating key will combine with oxygen vacancies or oxygen ions, resulting in a reset failure. Therefore, how to provide a resistive memory and a manufacturing method thereof, which can protect the sidewall of the memory cell to avoid reset failure, thereby improving high-temperature data retention (HTDR) will become an important issue.

The invention provides a resistive memory and a manufacturing method thereof, which can protect sidewalls of a memory cell to avoid reset failure, thereby improving high temperature data retention capability.

The invention provides a resistive memory comprising: a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protective layer. The first electrode is disposed opposite to the second electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The oxygen exchange layer is disposed between the variable resistance layer and the second electrode. The protective layer is disposed at least on the sidewall of the oxygen exchange layer.

The present invention provides a method of manufacturing a resistive memory, the steps of which are as follows. A first electrode and a second electrode are formed in opposite configurations. A variable resistance layer is formed between the first electrode and the second electrode. An oxygen exchange layer is formed between the variable resistance layer and the second electrode. A protective layer is formed which covers at least the sidewalls of the oxygen exchange layer.

Based on the above, the present invention fills the opening in the first dielectric layer by the oxygen exchange layer, so that the plasma step or the wet cleaning step in the etching process does not damage the sidewall of the oxygen exchange layer, thereby improving oxygen exchange. The flatness of the side walls of the layer. In addition, the present invention covers the sidewall of the oxygen exchange layer by a protective layer having a high dielectric constant, which not only protects the sidewall of the oxygen exchange layer, but also serves to provide an oxygen to oxygen exchange layer and confines the filament to the oxygen exchange layer. The center to increase the current density, thereby increasing the high temperature data retention capability.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

1A to 1I are schematic cross-sectional views showing a manufacturing process of a resistive memory according to an embodiment of the present invention.

Referring to FIG. 1A, a via 104 is formed in the dielectric layer 102. In detail, the method of forming the via 104 may be, for example, first forming a via opening (not shown) in the dielectric layer 102. Then, the barrier layer 104b is conformally formed in the via opening. The plug 104a is then filled into the via opening such that the barrier layer 104b is disposed between the dielectric layer 102 and the plug 104a. In an embodiment, the plug 104a and the barrier layer 104b may be considered as a via 104. Although only one via window is illustrated in FIG. 1A, the present invention is not limited thereto, and in other embodiments, the number of vias may be adjusted as needed. In an embodiment, the material of the plug 104a includes a metal material, and the metal material may be, for example, tungsten, and the forming method thereof may be, for example, a chemical vapor deposition method. The material of the barrier layer 104b may be, for example, tungsten nitride, titanium nitride, tantalum nitride or a combination thereof, and the formation method thereof is, for example, a chemical vapor deposition method. The material of the dielectric layer 102 may include ruthenium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be, for example, a chemical vapor deposition method.

Then, the first electrode 106, the variable resistance layer 108, and the first dielectric layer 110 are sequentially formed on the dielectric layer 102. The material of the first electrode 106 may include titanium nitride (TiN), platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), Zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), yttrium (Y), manganese (Mo) or a combination thereof, which may be formed, for example, by physical means. Vapor deposition or chemical vapor deposition. The material of the variable resistance layer 108 may include cerium oxide (which may be, for example, HfO or HfO _{2 ,} etc.), cerium oxide, cerium oxide, cerium oxide, zirconium oxide, titanium oxide, cerium oxide, nickel oxide, tungsten oxide, copper oxide, oxidation. Cobalt, iron oxide, aluminum oxide or a combination thereof is formed, for example, by chemical vapor deposition. The material of the first dielectric layer 110 may include ruthenium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be, for example, Atomic Layer Deposition (ALD) or chemical vapor deposition.

Referring to FIG. 1B, an opening 10 is formed in the first dielectric layer 110, wherein the opening 10 exposes the top surface of the variable resistance layer 108. The opening 10 corresponds to the via 104, which can be used to define the region of the subsequent memory cell 120 (as shown in FIG. 1I).

Referring to FIG. 1C, a protective layer 112 is formed on the dielectric layer 102 in a conformal manner. The protective layer 112 covers the top surface of the first dielectric layer 110a and the surface of the opening 10. In an embodiment, the material of the protective layer 112 comprises a high dielectric constant material. The high dielectric constant material may include a metal oxide, which may be, for example, cerium oxide, cerium oxide, cerium oxide, cerium oxide, zirconium oxide, titanium oxide, cerium oxide, nickel oxide, tungsten oxide, copper oxide, oxidation. Cobalt, iron oxide, aluminum oxide or a combination thereof. The formation method of the protective layer 112 may be, for example, an atomic layer deposition method or a chemical vapor deposition method, and the thickness thereof may be between 0.3 nm and 2 nm.

Referring to FIG. 1D, an oxygen exchange layer 114 is formed on the protective layer 112. The oxygen exchange layer 114 fills the opening 10 and covers the surface of the protective layer 112 such that the protective layer 112 is located between the oxygen exchange layer 114 and the first dielectric layer 110a. The material of the oxygen exchange layer 114 may include titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr), platinum (Pt), aluminum (Al) or a combination thereof, and the formation method thereof may be, for example, a physical gas phase. Deposition or chemical vapor deposition. It should be noted that this embodiment can improve the oxygen exchange layer 114 by filling the oxygen exchange layer 114 into the opening 10 to prevent the plasma step or the wet cleaning step in the etching process from damaging the sidewall of the oxygen exchange layer 114. The flatness of the side walls avoids the generation of floating keys. Therefore, the present embodiment can avoid reset failure and improve high temperature data retention capability.

Referring to FIG. 1E, a planarization process is performed to remove a portion of the oxygen exchange layer 114 to expose the top surface of the protective layer 112. In an embodiment, the planarization process can be, for example, an etchback process or a chemical mechanical honing process (CMP).

Referring to FIG. 1F, a barrier layer 116 is formed on the oxygen exchange layer 114a. In an embodiment, the material of the barrier layer 116 comprises a metal oxide. In another embodiment, the material of the barrier layer 116 may include titanium oxynitride, aluminum oxide, cerium oxide, zirconium oxide, or a combination thereof. Taking titanium oxynitride as an example, nitriding treatment may be performed so that titanium oxynitride is formed only on the top surface of the oxygen exchange layer 114a. On the other hand, in the case of alumina, a deposition treatment may be performed such that the alumina covers not only the top surface of the oxygen exchange layer 114a but also the top surface of the protective layer 112 (not shown). It is worth noting that the barrier layer 116 prevents the filament from being uneven when a large current flows through the oxygen exchange layer 114a during setting or resetting.

Referring to FIG. 1G, a second electrode 118 is formed on the protective layer 112 and the barrier layer 116. The material of the second electrode 118 may include titanium nitride (TiN), platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), Zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), yttrium (Y), manganese (Mo) or a combination thereof, which may be formed, for example, by physical means. Vapor deposition or chemical vapor deposition.

Referring to FIG. 1H, a patterning process is performed to remove a portion of the second electrode 118, a portion of the protective layer 112, a portion of the first dielectric layer 110a, a portion of the variable resistance layer 108, and a portion of the first electrode 106 to expose the dielectric layer 102. The top surface, in turn, forms a memory cell 120.

Referring to FIG. 1I, a metal oxide layer 122 is formed on the top surface and sidewalls of the memory cell 120 and a top surface (not shown) of the dielectric layer 102. Next, a dielectric layer 124 is formed on the metal oxide layer 122 (not shown). Then, a planarization process is performed with the second electrode 118a as a stop layer to remove a portion of the metal oxide layer 122 and a portion of the dielectric layer 124 to expose the top surface of the second electrode 118a. In an embodiment, the material of the metal oxide layer 122 may include cerium oxide, cerium oxide, cerium oxide, cerium oxide, zirconium oxide, titanium oxide, cerium oxide, nickel oxide, tungsten oxide, copper oxide, cobalt oxide, iron oxide, Alumina or a combination thereof may be formed by, for example, atomic layer deposition or chemical vapor deposition. The material of the dielectric layer 124 may include ruthenium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be, for example, a chemical vapor deposition method.

Referring to FIG. 1I , the resistive memory 100 includes a dielectric layer 102 , a via 104 , a metal oxide layer 122 , a dielectric layer 124 , and a memory cell 120 . The via window 104 is disposed in the dielectric layer 102. The memory cell 120 is disposed on the via 104. Dielectric layer 124 is disposed adjacent to memory cell 120. The metal oxide layer 122 is disposed between the dielectric layer 124 and the memory cell 120 and between the dielectric layer 124 and the dielectric layer 102.

The memory cell 120 includes a first electrode 106a, a second electrode 118a, a variable resistance layer 108a, a first dielectric layer 110b, an oxygen exchange layer 114a, a barrier layer 116, and a protective layer 112a. The first electrode 106a is disposed opposite to the second electrode 118a. The variable resistance layer 108a is disposed between the first electrode 106a and the second electrode 118a. The oxygen exchange layer 114a is disposed between the variable resistance layer 108a and the second electrode 118a. The first dielectric layer 110b is disposed beside the oxygen exchange layer 114a and disposed on the variable resistance layer 108a. The barrier layer 116 is disposed between the oxygen exchange layer 114a and the second electrode 118a. In the present embodiment, the protective layer 112a is disposed not only on the sidewall of the oxygen exchange layer 114a but also between the oxygen exchange layer 114a and the variable resistance layer 108a and the top surface of the first dielectric layer 110b. On the other hand, the protective layer 112a is also disposed between the first dielectric layer 110b and the oxygen exchange layer 114a.

It is worth mentioning that, since the present embodiment is filled with the oxygen exchange layer 114 into the opening 10, the side wall of the oxygen exchange layer 114 is not damaged by the plasma step or the wet cleaning step in the etching process. The sidewalls of the oxygen exchange layer 114a form a floating bond, thereby reducing the chance of reset failure. On the other hand, the protective layer 112a of the present embodiment can be used to provide an oxygen to oxygen exchange layer 114a. In other words, at the time of setting, the density of oxygen vacancies or oxygen ions will be more easily controlled at the center of the oxygen exchange layer 114a (i.e., the filament is confined to the center of the oxygen exchange layer 114a), thereby increasing the current density and thereby increasing the temperature. Data retention capabilities.

In addition, the first dielectric layer 110b of the present embodiment is also disposed adjacent to the oxygen exchange layer 114a, which can concentrate the electric field more at the center of the oxygen exchange layer 114a, thereby generating a concentrated filament, thereby improving the high temperature data retention capability.

In summary, the present invention fills the opening in the first dielectric layer by the oxygen exchange layer, so that the plasma step or the wet cleaning step in the etching process does not damage the sidewall of the oxygen exchange layer, thereby improving The flatness of the side walls of the oxygen exchange layer. In addition, the present invention covers the sidewall of the oxygen exchange layer by a protective layer having a high dielectric constant, which not only protects the sidewall of the oxygen exchange layer, but also serves to provide an oxygen to oxygen exchange layer and confines the filament to the oxygen exchange layer. The center to increase the current density, thereby increasing the high temperature data retention capability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ openings
100‧‧‧Resistive memory
102, 124‧‧‧ dielectric layer
104‧‧‧layer window
104a‧‧‧ Plug
104b‧‧‧Barrier layer
106, 106a‧‧‧ first electrode
108, 108a‧‧‧variable resistance layer
110, 110a, 110b‧‧‧ first dielectric layer
112, 112a‧‧‧ protective layer
114, 114a‧‧‧ oxygen exchange layer
116‧‧‧Barrier layer
118, 118a‧‧‧ second electrode
120‧‧‧ memory cells
122‧‧‧metal oxide layer

1A to 1I are schematic cross-sectional views showing a manufacturing process of a resistive memory according to an embodiment of the present invention.

100‧‧‧Resistive memory

102, 124‧‧‧ dielectric layer

104‧‧‧layer window

106a‧‧‧First electrode

108a‧‧‧Variable Resistance Layer

110b‧‧‧First dielectric layer

112a‧‧‧Protective layer

114a‧‧‧Oxygen exchange layer

116‧‧‧Barrier layer

118a‧‧‧second electrode

120‧‧‧ memory cells

122‧‧‧metal oxide layer

Claims (10)

A resistive memory comprising: a first electrode and a second electrode disposed opposite to each other; a variable resistance layer disposed between the first electrode and the second electrode; an oxygen exchange layer disposed at the a variable resistance layer and the second electrode; and a protective layer disposed on at least a sidewall of the oxygen exchange layer. The resistive memory of claim 1, wherein the material of the protective layer comprises a high dielectric constant material. The resistive memory of claim 1, further comprising a first dielectric layer disposed on a sidewall of the protective layer. The resistive memory of claim 3, wherein the protective layer extends further between the oxygen exchange layer and the variable resistance layer and a top surface of the first dielectric layer. The resistive memory according to claim 1, further comprising a barrier layer disposed between the oxygen exchange layer and the second electrode. A method of manufacturing a resistive memory, comprising: forming a first electrode and a second electrode disposed opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer Between the variable resistance layer and the second electrode; and forming a protective layer covering at least a sidewall of the oxygen exchange layer. The method of manufacturing a resistive memory according to claim 6, wherein the step of forming the oxygen exchange layer between the variable resistance layer and the second electrode comprises: forming a first dielectric layer Forming an opening in the first dielectric layer; and filling the oxygen exchange layer into the opening. The method of manufacturing a resistive memory according to claim 7, further comprising forming the protective layer in the opening before filling the oxygen exchange layer into the opening. The method of manufacturing a resistive memory according to claim 8, wherein the protective layer extends further between the oxygen exchange layer and the variable resistance layer and a top surface of the first dielectric layer. The method of manufacturing the resistive memory according to claim 8, after the oxygen exchange layer is filled in the opening, further comprising forming a barrier layer between the oxygen exchange layer and the second electrode. .