TWI539870B - Built-in components of the substrate - Google Patents
Built-in components of the substrate Download PDFInfo
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- TWI539870B TWI539870B TW100129324A TW100129324A TWI539870B TW I539870 B TWI539870 B TW I539870B TW 100129324 A TW100129324 A TW 100129324A TW 100129324 A TW100129324 A TW 100129324A TW I539870 B TWI539870 B TW I539870B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
本發明是關於一種將電子元件埋設於絕緣基材內的內藏元件之基板。 The present invention relates to a substrate in which an electronic component is embedded in a built-in component in an insulating substrate.
內藏元件之基板在專利文獻1中得到揭示。專利文獻1中所記載之內藏元件之基板包括絕緣基材、形成於其兩面的導體電路及電子元件。此電子元件為一種內藏元件，其埋設於絕緣基材之中，與端子部設置於基板側之連接端子部連接，再連接至導體電路。用來與此內藏元件之基板的連接端子連接的連接端子部在專利文獻1中被記載為使用阻焊層形成的範例。 The substrate of the built-in element is disclosed in Patent Document 1. The substrate of the built-in element described in Patent Document 1 includes an insulating base material, a conductor circuit formed on both surfaces thereof, and an electronic component. The electronic component is a built-in component that is embedded in an insulating base material, and is connected to a connection terminal portion on which the terminal portion is provided on the substrate side, and is connected to the conductor circuit. The connection terminal portion for connecting to the connection terminal of the substrate of the built-in element is described in Patent Document 1 as an example in which a solder resist layer is used.
然而，阻焊層在篩網印刷後藉由曝光、顯影、紫外線硬化或熱硬化而形成。因此，當在相鄰之內藏元件之間形成阻焊層時，難以縮小內藏元件之間的間隔。換言之，難以針對基板表面達到元件之高密度化。又，如專利文獻1所示，當藉由轉印法製作基板時，導體圖樣設計得比與電子元件連接之連接部大，所以，也難以達到配線之高密度化。 However, the solder resist layer is formed by exposure, development, ultraviolet curing or thermal hardening after screen printing. Therefore, when a solder resist layer is formed between adjacent built-in elements, it is difficult to narrow the interval between the built-in elements. In other words, it is difficult to achieve high density of components for the surface of the substrate. Moreover, as shown in Patent Document 1, when the substrate is produced by the transfer method, the conductor pattern is designed to be larger than the connection portion to which the electronic component is connected. Therefore, it is difficult to increase the density of the wiring.
[專利文獻1]特開2010-27917號公報 [Patent Document 1] JP-A-2010-27917
本發明為考慮上述習知技術之發明，目的在提供一種內藏元件之基板，其可縮小內藏元件之間的間隔而配置，於是，可達到元件之高密度化(提高元件之封裝密度)，再者，也可達到配線之高密度化。 The present invention has been made in view of the above-described prior art, and it is an object of the invention to provide a substrate having built-in components which can be arranged to reduce the interval between the components, thereby achieving high density of components (increasing package density of components). Furthermore, the density of wiring can be increased.
為達成上述目的，在本發明中，提供一種內藏元件之基板，其特徵在於：包括形成板狀的樹脂製之絕緣基材、埋設於該絕緣基材內的複數個電子元件、該元件透過接合材料封裝於其中一面且上述其中一面及周側面被上述絕緣基材覆蓋的板狀之導電墊片及形成於該導電墊片之另一面且相對於上述另一面之外緣形成於內側的導體圖樣。 In order to achieve the above object, a substrate for a built-in element is provided, comprising: a resin-made insulating substrate formed in a plate shape; a plurality of electronic components embedded in the insulating substrate; a plate-shaped conductive spacer in which one surface and one side surface of the bonding material are covered by the insulating base material, and a conductor formed on the other surface of the conductive spacer and formed on the inner side with respect to the outer surface of the other surface pattern.
更好的設計為，上述導體圖樣之形成方式為使上述另一面之一部分露出，則會更好。 More preferably, it is preferable that the conductor pattern is formed in such a manner that one of the other surfaces is partially exposed.
又，更好的設計為，在上述元件上設有複數個連接端子，上述導電墊片透過上述接合材料與上述連接端子作電子連接，藉由連接至各連接端子的各個上述導電墊片形成墊片單元，在相鄰之上述墊片單元之間，僅存在上述絕緣基材。 Further, it is more preferable to provide a plurality of connection terminals on the element, wherein the conductive pad is electrically connected to the connection terminal through the bonding material, and the pad is formed by each of the conductive pads connected to each connection terminal. In the sheet unit, only the insulating substrate is present between adjacent spacer units.
又，更好的設計為，上述連接端子設置於上述元件之兩端部，上述墊片單元之配設為墊片對，與上述導電墊片相向。 Further, it is preferable that the connection terminals are provided at both end portions of the element, and the spacer unit is disposed as a pair of pads facing the conductive pads.
再者，更好的設計為，在形成上述墊片對之上述導電墊片之間，設有用來保持上述元件與上述絕緣基材之表面之間隔的隔片。 Further, it is more preferable to provide a spacer for maintaining a space between the element and the surface of the insulating substrate between the conductive pads forming the pair of spacers.
又，上述接合材料為銲錫，上述隔片為阻焊膜。 Further, the bonding material is solder, and the spacer is a solder resist film.
本發明之內藏元件之基板包括絕緣基材、複數個元件、導電墊片及導體圖樣，導體圖樣形成於比作為導電墊片之另一面的圖樣形成面之外緣還小的範圍。於是，不越過導電墊片之外緣形成導體圖樣，各元件之間的間隔根據導電墊片之大小來決定。藉此，可縮小導電墊片之間的間隔而配置，所以，可提高元件之封裝密度。此時，導體圖樣若形成於比另一面(圖樣形成面)之外緣還小的範圍，亦即，使另一面之一部分露出，可確實提高元件之封裝密度。 The substrate of the built-in component of the present invention includes an insulating substrate, a plurality of components, a conductive spacer, and a conductor pattern, and the conductor pattern is formed in a range smaller than the outer edge of the pattern forming surface of the other surface of the conductive spacer. Thus, the conductor pattern is not formed beyond the outer edge of the conductive pad, and the spacing between the elements is determined by the size of the conductive pad. Thereby, the interval between the conductive pads can be reduced and arranged, so that the package density of the elements can be improved. At this time, if the conductor pattern is formed in a range smaller than the outer edge of the other surface (pattern forming surface), that is, a part of the other surface is exposed, the packing density of the element can be surely improved.
又，藉由元件之連接端子上分別連接的導電墊片形成墊片對，在此墊片對之間僅存在絕緣基材。於是，習知之阻焊層無法形成，所以，可縮小墊片對之間的間隔。因此，可提高元件之封裝密度。此外，當形成墊片對的有時是電阻、電容器等雙端子元件，若為連接端子更多的多端子元件(電晶體、IC、LSI等)，則藉由連接至各個連接端子的導電墊片形成墊片單元。藉由墊片單元，也能發揮相同的效果。 Further, a pair of pads are formed by conductive pads respectively connected to the connection terminals of the components, and only the insulating substrate exists between the pair of pads. Thus, the conventional solder resist layer cannot be formed, so that the interval between the pair of spacers can be reduced. Therefore, the packing density of the components can be increased. In addition, when a pair of pads is formed, it may be a two-terminal element such as a resistor or a capacitor, and if it is a multi-terminal element (a transistor, an IC, an LSI, or the like) having more connection terminals, a conductive pad connected to each connection terminal is used. The sheet forms a spacer unit. The same effect can be achieved by the spacer unit.
又，在形成墊片對之導電圖樣之間，設有用來保持元件與絕緣基材之表面之間隔的隔片，藉此，可防止元件隱沒。特別是當連接材料為銲錫時，效果明顯。隔片宜使用阻焊膜。 Further, a spacer for maintaining a space between the element and the surface of the insulating substrate is provided between the conductive patterns forming the spacer pair, whereby the element can be prevented from being hidden. Especially when the connecting material is solder, the effect is obvious. A solder mask should be used for the spacer.
如第1圖所示，本發明之內藏元件之基板1包括板狀之絕緣基材2。此絕緣基材2為樹脂製，例如預浸材料。此絕緣基材2埋設於電子元件3中。此元件3埋設於絕緣基材2內。在此絕緣基材2內，進一步埋設板狀之導電圖樣4。具體而言，導電墊片4之其中一面(元件封裝面4a)及周側面被絕緣基材2覆蓋，另一面與絕緣基材2之表面形成無段差狀態。亦即，導電墊片4之另一面(後述之圖樣形成面4b)從絕緣基材2露出。導電墊片可為鍍金墊片。 As shown in Fig. 1, the substrate 1 of the built-in component of the present invention comprises a plate-shaped insulating substrate 2. This insulating base material 2 is made of a resin such as a prepreg. This insulating base material 2 is embedded in the electronic component 3. This element 3 is embedded in the insulating substrate 2. In the insulating substrate 2, a plate-shaped conductive pattern 4 is further embedded. Specifically, one surface (component package surface 4a) and the circumferential side surface of the conductive spacer 4 are covered by the insulating base material 2, and the other surface is in a stepless state with the surface of the insulating base material 2. That is, the other surface of the conductive spacer 4 (the pattern forming surface 4b to be described later) is exposed from the insulating base material 2. The conductive gasket can be a gold plated gasket.
上述之元件3封裝於此導電墊片4之其中一面(元件封裝面4a)。具體而言，對應元件3之兩端部上分別設置的連接端子5分別配置導電墊片4，透過接合材料6作電子連接。接合材料6可使用銲錫或導電性之接著劑。又，藉由封裝同一元件3之各個導電墊片4(與各個連接端子5連接且為2個一組的導電墊片4)形成墊片對8。此外，在圖例中，是以電阻、電容器等雙端子元件為範例，然而，在電晶體、IC、LSI等連接端子更多之多端子元件中，墊片對8為墊片單元。具體而言，墊片單元由3個以上之導電墊片4所構成。 The above-described component 3 is packaged on one side of the conductive spacer 4 (element package surface 4a). Specifically, the connection pads 5 provided at the respective end portions of the corresponding elements 3 are respectively provided with the conductive pads 4, and are electrically connected through the bonding material 6. The bonding material 6 may use solder or a conductive adhesive. Further, the spacer pair 8 is formed by encapsulating each of the conductive pads 4 of the same element 3 (the conductive pads 4 connected to the respective connection terminals 5 and being two sets). Further, in the illustrated example, a two-terminal element such as a resistor or a capacitor is exemplified. However, in a plurality of terminal elements such as a transistor, an IC, or an LSI, the spacer pair 8 is a spacer unit. Specifically, the spacer unit is composed of three or more conductive spacers 4.
在導電墊片4之另一面(圖樣形成面4b)上，形成導體圖樣7。在第1圖及第2圖的範例中，相對於圖樣形成面4b之外緣，形成導體圖樣7。如此，可在與圖樣形成面4b之外緣同等或比外緣小的範圍內形成導體圖樣7，所以，無法越過導電墊片4之外緣形成導體圖樣7。於是，各元件3之間的間隔，亦即，墊片對8之間的間隔根據導電墊片4之大小來決定。換言之，導體圖樣7之形成方式無法從導電墊片4露出， 所以，可縮小導電墊片4(實際上為墊片對8)之間的間隔而配置。藉此，可針對元件3之製品基板提高封裝密度。 On the other surface (pattern forming surface 4b) of the conductive spacer 4, a conductor pattern 7 is formed. In the examples of Figs. 1 and 2, the conductor pattern 7 is formed with respect to the outer edge of the pattern forming surface 4b. Thus, the conductor pattern 7 can be formed in the same range as the outer edge of the pattern forming surface 4b or smaller than the outer edge. Therefore, the conductor pattern 7 cannot be formed beyond the outer edge of the conductive spacer 4. Thus, the spacing between the elements 3, that is, the spacing between the pairs of pads 8, is determined by the size of the conductive pads 4. In other words, the manner in which the conductor pattern 7 is formed cannot be exposed from the conductive spacer 4, Therefore, it is possible to reduce the interval between the conductive pads 4 (actually the spacer pairs 8). Thereby, the packing density can be increased for the product substrate of the component 3.
此時，如第1圖、第2圖所示，導體圖樣7若形成於比另一面(圖樣形成面4b)之外緣小的範圍，亦即，形成方式為使另一面之一部分露出，確實可提高元件3之封裝密度。又，如第2圖所示，即使在元件3之間設置與導體圖樣7連接之配線部9，可縮小元件3與配線部9之間的間隔，於是可提高元件3之封裝密度。又，只要是可設置配線部9之位置，就可靠近導電墊片4，所以，可達到配線之高密度化。 At this time, as shown in FIG. 1 and FIG. 2, the conductor pattern 7 is formed in a range smaller than the outer edge of the other surface (pattern forming surface 4b), that is, the forming method is such that one of the other surfaces is partially exposed. The packing density of the component 3 can be increased. Moreover, as shown in FIG. 2, even if the wiring part 9 connected to the conductor pattern 7 is provided between the elements 3, the space between the element 3 and the wiring part 9 can be made small, and the packing density of the element 3 can be improved. Moreover, as long as the position of the wiring portion 9 can be provided, the conductive spacer 4 can be brought close to each other, so that the wiring can be made denser.
另一方面，在相鄰之墊片對8之間，僅存在絕緣基材2。亦即，在相鄰之墊片對8之間，無法形成習知之阻焊曾。因此，墊片對8之間的間隔得以縮小。此種構造有助於提高元件3之封裝密度。又，在形成墊片對8之導電墊片4之間，亦即，元件3之下側，設有隔片10(在圖中記載為僅在一部分之元件3設置隔片10)。此隔片10可用來保持元件3與絕緣基材2之表面的間隔。藉由設置此隔片10，可防止元件3隱沒。特別是當接合材料為銲錫時，效果顯著。隔片10宜使用阻焊膜。亦可藉由變更此隔片10之形狀、高度來控制元件之設置高度。 On the other hand, only the insulating substrate 2 is present between adjacent pairs of spacers 8. That is, a conventional solder mask cannot be formed between adjacent pairs of spacers 8. Therefore, the interval between the spacer pairs 8 is reduced. This configuration helps to increase the packing density of the component 3. Further, between the conductive spacers 4 on which the spacers 8 are formed, that is, on the lower side of the element 3, spacers 10 are provided (in the figure, only a part of the elements 3 are provided with the spacers 10). This spacer 10 can be used to maintain the spacing of the component 3 from the surface of the insulating substrate 2. By providing this spacer 10, the component 3 can be prevented from being hidden. Especially when the bonding material is solder, the effect is remarkable. It is preferable to use a solder resist film for the spacer 10. The height of the component can also be controlled by changing the shape and height of the spacer 10.
以下將根據第3圖至第9圖說明本發明之內藏元件之基板之製造方法之一例。 Hereinafter, an example of a method of manufacturing a substrate of the built-in element of the present invention will be described with reference to Figs. 3 to 9 .
首先，如第3圖所示，在支持板11上形成導電層12。支持板11可為SUS板。導電層12可為由鍍銅等所構成的銅薄膜。接著，如第4圖所示，在導電層12上載置上述之導電墊 片4。當導電墊片4為鍍金墊片時，此導電墊片4對銅製之墊片施以軟蝕刻處理，之後，施以鎳厚度1μm~10μm(最好為5μm)、金厚度0.01μm~1μm(最好為0.03μm)的鍍金處理。藉由軟蝕刻處理，導電墊片4之表面若以表面粗度(Rz)來表示時，為0μm~1.5μm，所以，形成平坦的形狀。此外，作為對鍍金墊片7之表面進行平坦化處理的方法，亦可使用微蝕刻、酸洗或電漿蝕刻。 First, as shown in FIG. 3, a conductive layer 12 is formed on the support plate 11. The support board 11 can be a SUS board. The conductive layer 12 may be a copper thin film made of copper plating or the like. Next, as shown in FIG. 4, the above-mentioned conductive pad is placed on the conductive layer 12. Sheet 4. When the conductive pad 4 is a gold-plated pad, the conductive pad 4 is subjected to a soft etching treatment on the copper pad, and then a nickel thickness of 1 μm to 10 μm (preferably 5 μm) and a gold thickness of 0.01 μm to 1 μm ( It is preferably a gold plating treatment of 0.03 μm). When the surface of the conductive spacer 4 is represented by the surface roughness (Rz) by the soft etching treatment, it is 0 μm to 1.5 μm, so that a flat shape is formed. Further, as a method of planarizing the surface of the gold plating pad 7, micro etching, pickling, or plasma etching may be used.
另外，如第5圖所示，對導電層12之表面施以粗面化處理，形成粗面12a。此粗面化處理之進行方式為，使用黑化還原處理、膠膜處理、CZ處理，針對導電層12之表面，對銅表面進行蝕刻處理，形成有機皮膜。其表面粗度(Rz)為0.1μm~10μm。在此，所謂膠膜處理，是指使用ATOTHCH公司所製造之藥液來進行的處理。其為藉由銅表面之粗面化及有機金屬皮膜之形成來提高樹脂密著性的處理。又，所謂CZ處理，是指使用公司所製造之藥液來進行的處理。其為提高銅表面之粗面化及樹脂密著性的處理。 Further, as shown in Fig. 5, the surface of the conductive layer 12 is roughened to form a rough surface 12a. This roughening treatment is carried out by using a blackening reduction treatment, a film treatment, and a CZ treatment, and etching the copper surface on the surface of the conductive layer 12 to form an organic film. The surface roughness (Rz) is from 0.1 μm to 10 μm. Here, the film treatment refers to a treatment using a chemical liquid manufactured by ATOTHCH Co., Ltd. This is a treatment for improving the resin adhesion by roughening the surface of the copper and forming an organic metal film. Also, the so-called CZ processing refers to the use The chemical liquid produced by the company is processed. This is a treatment for improving the roughening of the copper surface and the resin adhesion.
另外，如第6圖所示，在導電墊片4之元件封裝面4a配置接合材料6。在圖中，表示出接合材料6為銲錫的範例。另外，如第7圖所示，元件3之連接端子5與導電墊片4透過接合材料6作電子連接。在圖例中，具體而言是進行回流焊接。藉此，元件3封裝於導電墊片4上。此時，上述之粗面12a形成於與導電墊片4之側緣相接的位置，所以，可確實防止焊接的擴張超過導電墊片4。換言之，可達到阻止藉由粗面12a阻止和焊接之擴張的效果。於是，不需要形成過去 所使用之錫堤。由於不需要錫堤，所以，可縮小上述相鄰之墊片對8之間的間隔。藉此，可縮小配置元件3的間隔，進而提高元件3之封裝密度。又，由於不需要用來形成錫堤之阻焊膜形成製程，所以製程可縮短，連帶也不需要使用在該製程的材料，於是大大降低了成本。 Further, as shown in Fig. 6, the bonding material 6 is disposed on the element package surface 4a of the conductive spacer 4. In the figure, an example in which the bonding material 6 is solder is shown. Further, as shown in Fig. 7, the connection terminal 5 of the element 3 and the conductive spacer 4 are electrically connected through the bonding material 6. In the illustration, specifically, reflow soldering is performed. Thereby, the component 3 is encapsulated on the conductive spacer 4. At this time, since the rough surface 12a is formed at a position in contact with the side edge of the conductive spacer 4, it is possible to surely prevent the expansion of the solder from exceeding the conductive spacer 4. In other words, the effect of preventing the expansion by the rough surface 12a and the welding can be achieved. So, there is no need to form the past The tin bank used. Since the tin bank is not required, the interval between the adjacent pairs of spacers 8 can be reduced. Thereby, the interval between the arrangement elements 3 can be reduced, thereby increasing the packing density of the elements 3. Moreover, since the solder resist film forming process for forming the tin bank is not required, the process can be shortened, and the material used in the process is not required to be attached, thereby greatly reducing the cost.
另外，如第8圖所示，將元件3埋設於絕緣基材2內。具體而言，導電層12與絕緣基材2之間夾持有元件3，相互壓接導電層12與絕緣基材2。之後，去除支持板11。 Further, as shown in Fig. 8, the element 3 is buried in the insulating base material 2. Specifically, the element 3 is sandwiched between the conductive layer 12 and the insulating base material 2, and the conductive layer 12 and the insulating base material 2 are bonded to each other. Thereafter, the support board 11 is removed.
另外，如第9圖所示，在導電墊片4之圖樣形成面4b上形成導體圖樣7。具體而言，去除導電層12之一部分而形成導體圖樣7。此導體圖樣7對導電層12施以蝕刻處理而形成。此時，導電墊片4作為蝕刻阻劑，可防止接合材料6露出。再者，可防止已封裝好之元件3之電子連接之可靠性下降。此導體圖樣7如上所述，形成於與圖樣形成面4b之外緣相等或比其小的範圍。在形成導電圖樣7的同時，可形成配線部9。如此之外，在圖中表示出僅在基板之單面側形成導體圖樣7的單面基板的範例，但本發明理所當然可應用於雙面基板。又，本發明亦可應用於將以上組合起來之多層基板。 Further, as shown in Fig. 9, a conductor pattern 7 is formed on the pattern forming surface 4b of the conductive spacer 4. Specifically, a portion of the conductive layer 12 is removed to form a conductor pattern 7. This conductor pattern 7 is formed by applying an etching treatment to the conductive layer 12. At this time, the conductive spacer 4 serves as an etching resist to prevent the bonding material 6 from being exposed. Furthermore, the reliability of the electronic connection of the packaged component 3 can be prevented from deteriorating. As described above, this conductor pattern 7 is formed in a range equal to or smaller than the outer edge of the pattern forming surface 4b. The wiring portion 9 can be formed while forming the conductive pattern 7. In addition, in the figure, an example in which the single-sided substrate of the conductor pattern 7 is formed only on one side of the substrate is shown, but the present invention is of course applicable to the double-sided substrate. Further, the present invention is also applicable to a multilayer substrate in which the above is combined.
1‧‧‧內藏元件之基板 1‧‧‧Substrate of built-in components
2‧‧‧絕緣基材 2‧‧‧Insulating substrate
3‧‧‧元件 3‧‧‧ components
4‧‧‧導電墊片 4‧‧‧Electrical gasket
4a‧‧‧元件封裝面(其中一面) 4a‧‧‧ Component package surface (one side)
4b‧‧‧圖樣形成面(另一面) 4b‧‧‧ pattern forming surface (the other side)
5‧‧‧連接端子 5‧‧‧Connecting terminal
6‧‧‧接合件 6‧‧‧Joint parts
7‧‧‧導體圖樣 7‧‧‧Conductor pattern
8‧‧‧墊片對 8‧‧‧shield pair
9‧‧‧配線部 9‧‧‧Wiring Department
10‧‧‧隔片 10‧‧‧ spacer
11‧‧‧支持板 11‧‧‧Support board
12‧‧‧導電層 12‧‧‧ Conductive layer
12a‧‧‧粗面 12a‧‧‧
第1圖為本發明之元件內藏基板的概略剖面圖。 Fig. 1 is a schematic cross-sectional view showing a substrate built in the component of the present invention.
第2圖為第1圖的A-A視圖。 Figure 2 is a view of the A-A of Figure 1.
第3圖為依序表示本發明之元件內藏基板之製造方法 的概略圖。 3 is a view showing a method of manufacturing a component-embedded substrate of the present invention in order Schematic diagram.
第4圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 4 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order.
第5圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 5 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order.
第6圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 6 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order.
第7圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 7 is a schematic view showing the method of manufacturing the element-embedded substrate of the present invention in order.
第8圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 8 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order.
第9圖為依序表示本發明之元件內藏基板之製造方法的概略圖。 Fig. 9 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order.
1‧‧‧元件內藏機基板 1‧‧‧Component built-in machine substrate
2‧‧‧絕緣基材 2‧‧‧Insulating substrate
3‧‧‧元件 3‧‧‧ components
4‧‧‧導電墊片 4‧‧‧Electrical gasket
4a‧‧‧元件封裝面(其中一面) 4a‧‧‧ Component package surface (one side)
4b‧‧‧圖樣形成面(另一面) 4b‧‧‧ pattern forming surface (the other side)
5‧‧‧連接端子 5‧‧‧Connecting terminal
6‧‧‧接合件 6‧‧‧Joint parts
7‧‧‧導體圖樣 7‧‧‧Conductor pattern
8‧‧‧墊片對 8‧‧‧shield pair
9‧‧‧配線部 9‧‧‧Wiring Department
10‧‧‧隔片 10‧‧‧ spacer
Claims (6)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2010/065626 WO2012032654A1 (en) | 2010-09-10 | 2010-09-10 | Substrate with built-in components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201216793A TW201216793A (en) | 2012-04-16 |
| TWI539870B true TWI539870B (en) | 2016-06-21 |
Family
ID=45810274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100129324A TWI539870B (en) | 2010-09-10 | 2011-08-17 | Built-in components of the substrate |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP5659234B2 (en) |
| KR (1) | KR101713640B1 (en) |
| CN (1) | CN103098565B (en) |
| TW (1) | TWI539870B (en) |
| WO (1) | WO2012032654A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6073339B2 (en) * | 2012-09-11 | 2017-02-01 | 株式会社メイコー | Manufacturing method of component-embedded substrate and component-embedded substrate using the same |
| EP2897447A4 (en) | 2012-09-11 | 2016-05-25 | Meiko Electronics Co Ltd | Method for manufacturing embedded component substrate, and embedded component substrate manufactured using this method |
| KR102281458B1 (en) * | 2014-06-23 | 2021-07-27 | 삼성전기주식회사 | Printed circuit board having an embedded device, semiconductor package and method of manufacturing the same |
| US20220312591A1 (en) * | 2021-03-26 | 2022-09-29 | Juniper Networks, Inc. | Substrate with conductive pads and conductive layers |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3173423B2 (en) * | 1997-05-02 | 2001-06-04 | 日本電気株式会社 | Printed wiring board |
| JP4034073B2 (en) * | 2001-05-11 | 2008-01-16 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP2006324567A (en) * | 2005-05-20 | 2006-11-30 | Matsushita Electric Ind Co Ltd | Substrate incorporating component and its manufacturing method |
| CN101690434B (en) * | 2007-06-26 | 2011-08-17 | 株式会社村田制作所 | Method for manufacturing substrate having built-in components |
| JP4874305B2 (en) * | 2008-07-22 | 2012-02-15 | 株式会社メイコー | Circuit board with built-in electric / electronic components and manufacturing method thereof |
-
2010
- 2010-09-10 CN CN201080069036.5A patent/CN103098565B/en not_active Expired - Fee Related
- 2010-09-10 WO PCT/JP2010/065626 patent/WO2012032654A1/en active Application Filing
- 2010-09-10 KR KR1020137006798A patent/KR101713640B1/en active IP Right Grant
- 2010-09-10 JP JP2012532818A patent/JP5659234B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| JP5659234B2 (en) | 2015-01-28 |
| KR20140006771A (en) | 2014-01-16 |
| TW201216793A (en) | 2012-04-16 |
| CN103098565A (en) | 2013-05-08 |
| WO2012032654A1 (en) | 2012-03-15 |
| JPWO2012032654A1 (en) | 2013-12-12 |
| CN103098565B (en) | 2016-08-03 |
| KR101713640B1 (en) | 2017-03-08 |
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