TWI527045B - Shift register circuit - Google Patents

Description

Shift register circuit

The present invention relates to a shift register circuit, and more particularly to a shift register circuit having better drive capability.

The shift register determines whether to output a gate driving signal according to one of the internal control signals, and stabilizes the gate driving signal and the control signal in a period in which the shift register does not need to output the gate driving signal. At low potential, to avoid shifting the register at the wrong time, the gate drive signal drives the wrong gate line. However, the control signal of the conventional control is not able to correctly drive the gate drive signal due to interference of external signals or leakage, which causes the shift register to fail to operate normally.

In order to solve the above drawbacks, the present invention provides a shift register circuit embodiment including a first pull-up circuit, a second pull-up circuit, a first pull-down control circuit, and a first pull-down circuit. a second pull-down control circuit, a second pull-down circuit, a main pull-down circuit, and a first capacitor.

The first pull-up circuit is configured to receive a high frequency clock signal, and determine whether to output an nth gate control signal according to an nth level control signal; the second pull-up circuit is electrically coupled to the first pull-up circuit Connected, used to output a The n+m level control signal; the first pull-down control circuit is configured to receive a clock signal, and output a first pull-down control signal according to the clock signal and the n-th control signal; the first pull-down circuit is used to Determining whether to stabilize the nth control signal and the nth gate control signal to a low voltage level according to the first pulldown control signal; a second pulldown control circuit is configured to receive another clock signal, and according to the time The pulse signal and the nth control signal output a second pulldown control signal; the second pulldown circuit is configured to determine whether to stabilize the nth control signal and the nth gate control signal to a low voltage level according to the second pulldown control signal The main pull-down circuit is configured to determine whether to stabilize the nth control signal and the nth gate control signal to a low voltage level according to an n+4th gate control signal; the first capacitor has a first end And the second end is configured to receive an nth-level control signal, and the second end is configured to be electrically coupled to the nth-level control signal, where m, n, and p are positive integers.

In view of the above, the embodiment of the shift register circuit of the present invention electrically couples the control signal of the nth-stage shift register circuit and the n+m-stage shift register circuit by using a capacitor. The control signal enables the control signal of this level to be compensated by the np-level control signal and the n+m-level control signal. Therefore, the control signal of the current level can effectively avoid the control signal driving capability of the current level due to external signal interference or leakage. Low or drive errors, etc., and thus greatly reduce the situation in which the shift register is not working properly.

10‧‧‧First pull-up circuit

20‧‧‧Second pull-up circuit

30‧‧‧First pull-down control circuit

40‧‧‧First pull-down circuit

50‧‧‧Second pull-down control circuit

60‧‧‧Second pull-down circuit

70‧‧‧Main pull-down circuit

T11, T21, T22, T23, T31, T32, T33, T34, T41, T42, T51, T52, T53, T54, T61, T62, T71, T72‧‧

C1‧‧‧first capacitor

C2‧‧‧second capacitor

LC1‧‧‧ first clock signal

LC2‧‧‧ second clock signal

HC(n-4)‧‧‧n-4th high frequency clock signal

HC(n-3)‧‧‧n-3th high frequency clock signal

HC(n-2)‧‧‧n-2th high frequency clock signal

HC(n-1)‧‧‧n-1th high frequency clock signal

HC(n)‧‧‧n-level high frequency clock signal

HC(n+1)‧‧‧n+1th high frequency clock signal

HC(n+2)‧‧‧n+2 high frequency clock signal

HC(n+3)‧‧‧n+3 high frequency clock signal

Q(n-2)‧‧‧n-2 level control signal

Q(n-1)‧‧‧n-1th level control signal

Q(n)‧‧‧n level control signal

Q(n+2)‧‧‧n+2 control signals

Q(n+4)‧‧‧n+4 control signals

G(n)‧‧‧n-th gate control signal

G(n+2)‧‧‧n+2 level gate control signal

G(n+4)‧‧‧th n+4 gate control signal

VSS1‧‧‧low voltage level

P(n)‧‧‧first pulldown control signal

K(n)‧‧‧Second pull-down control signal

FIG. 1A is a schematic diagram of an embodiment of the present invention.

FIG. 1B is a schematic diagram of Embodiment 2 of the present invention.

FIG. 1C is a schematic diagram of Embodiment 3 of the present invention.

2A is a schematic diagram of a high frequency clock signal of a 2D display according to an embodiment of the present invention.

2B is a schematic diagram of control signal compensation in a 2D display according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a high frequency clock signal of a 3D display according to an embodiment of the present invention.

FIG. 3B is a schematic diagram of control signal compensation in a 3D display according to an embodiment of the present invention.

4A is a schematic view of Embodiment 4 of the present invention.

4B is a schematic diagram of Embodiment 5 of the present invention.

4C is a schematic view of Embodiment 6 of the present invention.

FIG. 5 is a schematic diagram of the high frequency clock signal and control signal compensation driven by the dot inversion method according to the fourth embodiment of the present invention.

FIG. 6 is a schematic diagram of the high frequency clock signal and control signal compensation driven by the line inversion method according to the fourth embodiment of the present invention.

In order to explain the present invention more clearly, the following description will be made in conjunction with the drawings.

Referring to FIG. 1A, FIG. 1A shows a first embodiment of a shift register circuit of the present invention, which includes a first pull-up circuit 10, a second pull-up circuit 20, a first pull-down control circuit 30, and a first The pull-down circuit 40, a second pull-down control circuit 50, a second pull-down circuit 60, a main pull-down circuit 70, and a first capacitor C1 can be applied to the 2D display mode or the 3D display mode at the same time.

The first pull-up circuit 10 includes a transistor T11 having a first end, a second end, and a control end, the first end of which is configured to receive an n-th high frequency clock signal HC(n), and the control end thereof The system is configured to receive an nth level control signal Q(n), and the second end is to determine whether to output an nth level gate control signal G according to the nth level control signal Q(n) received by the control end ( n). In addition, the first one The pull-up circuit 10 further includes a second capacitor C2. The first end of the second capacitor C2 is electrically coupled to the second end of the transistor T11, and the second end of the second capacitor C2 is electrically connected to the control terminal of the transistor T11. Coupling, when the second terminal of the transistor T11 outputs the nth gate control signal G(n), the second capacitor C2 can compensate the nth gate control signal G(n) to the nth control signal. Q(n) to increase the driving capability of the nth stage control signal Q(n).

The second pull-up circuit 20 includes a transistor T21 and a transistor T22. The transistor T21 and the transistor T22 have a first end, a second end, and a control end. The first end of the transistor T21 is configured to receive the foregoing The n-th high frequency clock signal HC(n), the control end of the transistor T21 is for receiving the nth stage control signal Q(n), and the second end of the transistor T21 is used for the control end of the transistor T22 Electrically coupled, the first end of the transistor T22 is for receiving the nth gate control signal G(n), and the second end of the transistor T22 is for outputting an n+4th control signal Q(n +4). Therefore, when the transistor T21 is turned on by the nth stage control signal Q(n) and the nth stage high frequency clock signal HC(n) is transmitted to the control terminal of the transistor T22, the transistor T22 is about to be the first The nth gate control signal G(n) received by the terminal is transmitted to the second terminal and output as the n+4th control signal Q(n+4), that is, the shift of 1 transmission 5 is used in this embodiment. Similarly, the nth stage control signal Q(n) is provided by the n-4th stage shift register circuit.

The first pull-down control circuit 30 includes a transistor T31, a transistor T32, a transistor T33, and a transistor T34. The transistor T31 includes a first end, a second end, and a control end. The first end is electrically coupled to the control end to receive a first clock signal LC1. The transistor T32 includes a first end and a second end. And a control end, the first end is electrically coupled to the first end of the transistor T31, the control end is electrically coupled to the second end of the transistor T31, and the second end is electrically coupled Is used to output a first pull-down control signal P(n); the transistor T33 includes a first end, a second end, and a control end, and the first end thereof is electrically coupled to the second end of the transistor T31, and the control thereof is controlled. The end is configured to receive the nth stage control signal Q(n), the second end of which is electrically coupled to a low voltage level VSS1; the transistor T34 includes a first end, a second end, and a control end, the first end thereof The system is configured to receive the first pull-down control signal P(n), the control end is configured to receive the n-th control signal Q(n), and the second end is configured to be electrically coupled to the low voltage level VSS1. Pick up. Therefore, when it is not necessary to output the nth gate control signal G(n), the transistor T33 and the transistor T34 are turned off, so the transistor T31 and the transistor T32 can output the foregoing according to the received first clock signal LC1. The first pull-down control signal P(n), and when the n-th gate control signal G(n) is to be output, the transistor T33 and the transistor T34 are at the n-th level control signal Q(n) Turning on, the second end of the transistor T31 electrically coupled to the transistor T33 and the first pull-down control signal P(n) electrically coupled to the transistor T34 are pulled down by the transistor T33 and the transistor T34. To the low voltage level VSS1, to prevent the first pull-down circuit 40 from being turned on at the wrong time.

The first pull-down circuit 40 includes a transistor T41 and a transistor T42. The transistor T41 includes a first end, a second end, and a control end. The first end is configured to be electrically connected to the nth stage control signal Q(n). The control terminal is configured to receive the first pull-down control signal P(n), the second end of the second pull-down control signal is coupled to the low voltage level VSS1; the transistor T42 includes the first end and the second end. The first end of the terminal and the control end are electrically coupled to the nth gate control signal G(n), and the control end is configured to receive the first pulldown control signal P(n), the second The terminal is configured to be electrically coupled to the low voltage level VSS1. Therefore, the first pull-down circuit 40 is configured to determine whether to turn on the transistor T41 and the transistor T42 according to the first pull-down control signal P(n). The nth level control signal Q(n) and the nth stage The gate control signal G(n) is pulled down to the low voltage level VSS1.

The second pull-down control circuit 50 includes a transistor T51, a transistor T52, a transistor T53, and a transistor T54. The transistor T51 includes a first end, a second end, and a control end. The first end is electrically coupled to the control end to receive a second clock signal LC2. The transistor T52 includes a first end and a second end. And a control end, the first end is electrically coupled to the first end of the transistor T51, the control end is electrically coupled to the second end of the transistor T51, and the second end is configured to output a second pulldown The control signal K(n) includes a first end, a second end, and a control end. The first end is electrically coupled to the second end of the transistor T51, and the control end is configured to receive the nth stage control. The second end of the signal Q(n) is electrically coupled to a low voltage level VSS1; the transistor T54 includes a first end, a second end, and a control end, and the first end is configured to receive the second pulldown control signal K(n), whose control terminal is used to receive the nth stage control signal Q(n), and the second end thereof is used to be electrically coupled to the aforementioned low voltage level VSS1. Therefore, when it is not necessary to output the nth gate control signal G(n), the transistor T53 and the transistor T54 are turned off, so the transistor T51 and the transistor T52 can be made according to the received second clock signal LC2. The second pull-down control signal K(n) is the operating voltage level, and when the n-th gate control signal G(n) is to be output, the transistor T33 and the transistor T34 are turned on, and thus the transistor T33 is electrically connected. The second end of the coupled transistor T31 and the second pull-down control signal K(n) electrically coupled to the transistor T34 are pulled down to the low voltage level VSS1 to prevent the second pull-down circuit 60 from being in error. Time is turned on.

The second pull-down circuit 60 includes a transistor T61 and a transistor T62. The transistor T61 includes a first end, a second end, and a control end, and the first end is used for electrical connection with the nth stage control signal Q(n). Coupling, the control end is for receiving the second pull-down control signal K(n), and the second end is used for low voltage The bit VSS1 is electrically coupled; the transistor T62 includes a first end, a second end, and a control end, and the first end is electrically coupled to the nth gate control signal G(n), and the control end is The second pull-down circuit 60 is configured to receive the second pull-down control signal K(n), and the second pull-down circuit 60 is configured to be coupled to the second pull-down control signal K(n) according to the second pull-down control signal K(n). The transistor T61 and the transistor T62 are turned on to pull down the nth control signal Q(n) and the nth gate control signal G(n) to the low voltage level VSS1.

The main pull-down circuit 70 includes a transistor T71 and a transistor T72. The transistor T71 includes a first end, a second end, and a control end. The first end is electrically coupled to the nth control signal Q(n). The control terminal is configured to receive the n+4th gate control signal G(n+4), the second end thereof is electrically coupled to the low voltage level VSS1, and the transistor T72 includes the first end. The second end and the control end are respectively configured to be electrically coupled to the nth gate control signal G(n), and the control end is configured to receive the n+4th gate control signal G ( n+4), the second end is used to be electrically coupled to the low voltage level VSS1. Therefore, when the transistor T71 and the transistor T72 are turned on, the nth level control signal electrically coupled to the transistor T71 is connected. Q(n) and the nth gate control signal G(n) electrically coupled to the transistor T72 will be pulled down to the low voltage level VSS1.

The capacitor C1 has a first end and a second end, the first end of which is configured to receive the n-2th control signal Q(n-2), and the second end is electrically connected to the nth stage control signal Q(n) Coupling, so the nth-level control signal Q(n-2) can be used to compensate the n-th control signal Q(n), or the n-th control signal Q(n) of the current stage can be used to compensate the n-2 The level control signal Q(n-2), similarly, the nth stage control signal Q(n) of the stage can also compensate the n+2 level through the capacitance of the n+2 stage shift register circuit. The control signal Q(n+2) or the nth-level control signal Q(n+2) compensates the n-th control signal Q(n), and the detailed compensation mode will cooperate. The drawings are further illustrated in Figures 2B and 3B.

Please refer to FIG. 1B. FIG. 1B is a second embodiment of the shift register circuit of the present invention. The difference between FIG. 1B and FIG. 1A is that the first end of the transistor T22 of the second pull-up circuit 20 can be connected to the transistor T22. The control terminal is electrically coupled, that is, when the transistor T21 is turned on, the transistor T22 receives the first end of the transistor T22 according to the nth high frequency clock signal HC(n) received by the control terminal. The n-stage high frequency clock signal HC(n) output is the n+4th level control signal Q(n+4).

Please refer to FIG. 1C. FIG. 1C is a third embodiment of the shift register circuit of the present invention. FIG. 1C differs from FIG. 1A in that the second pull-up circuit 20 can include a transistor T23, and the transistor T23 includes a first end. The second end and the control end are electrically coupled to the first end and the control end for receiving the nth gate control signal G(n), so the transistor T23 is based on the nth gate control signal G(n) outputs the nth gate control signal G(n) received by the first terminal as the n+4th control signal Q(n+4).

2A is a high frequency clock signal embodiment of the shift register circuit of the first embodiment for use in the 2D display mode, which includes the n-4th high frequency clock signal HC(n-4), the n-3th. High-frequency clock signal HC(n-3), n-2th high-frequency clock signal HC(n-2), n-1th high-frequency clock signal HC(n-1), nth stage High frequency clock signal HC(n), n+1th high frequency clock signal HC(n+1), n+2 high frequency clock signal HC(n+2) and n+3 level high Frequency clock signal HC(n+3), and n-4th high frequency clock signal HC(n-4), n-3th high frequency clock signal HC(n-3), n-2 High frequency clock signal HC(n-2), n-1th high frequency clock signal HC(n-1), nth high frequency clock signal HC(n), n+1th high frequency The clock signal HC(n+1), the n+2th high frequency clock signal HC(n+2), and the n+3th high frequency clock signal HC(n+3) have the same Energy time, the n+3th high frequency clock signal HC(n+3) is behind the n+2th high frequency clock signal HC(n+2) for a preset time and the n+2th high frequency The pulse signal HC(n+2) is behind the n+1th high frequency clock signal HC(n+1) for a preset time, and the n+1th high frequency clock signal HC(n+1) is behind the first The n-level high-frequency clock signal HC(n) is a preset time, the n-th high-frequency clock signal HC(n) is behind the n-1th high-frequency clock signal HC(n-1) for a preset time The n-1th high frequency clock signal HC(n-1) is behind the n-2th high frequency clock signal HC(n-2) for a preset time, the n-2th high frequency clock signal HC(n-2) is behind the n-3th high frequency clock signal HC(n-3) for a preset time, the n-3th high frequency clock signal HC(n-3) and is behind the n-th The 4-level high-frequency clock signal HC (n-4) is a preset time.

Next, please refer to FIG. 2B, and the compensation mode of the n-th control signal Q(n) is mainly described with reference to FIG. 2A. The n-2th control signal Q(n-2), the nth control signal Q(n), and the n+2th control signal Q(n+2) all include a first working voltage level I and a second operation. The voltage level II, the third working voltage level III and the fourth working voltage level IV. According to FIG. 1A, the nth stage shift register circuit outputs the n+4th control signal Q(n+4). Similarly, the n-4th stage shift register circuit outputs. The nth stage controls the signal Q(n), so when the n-4th stage shift register circuit of the present stage high frequency signal, that is, the n-4th stage high frequency clock signal HC(n-4) is high At the voltage level, the nth control signal Q(n) is raised to the first operating voltage level I; then, the high frequency clock signal of the current level of the nth control signal Q(n) is also When the nth high frequency clock signal HC(n) is not at the high voltage level, since the n-2th control signal Q(n-2) is raised to the third working voltage level III, the nth The +2 level control signal Q(n+2) is raised to the first working voltage level I, so the n-2th level control signal Q(n-2) can be obtained by the first capacitor C1 described in FIG. 1A. The n+2th level control signal Q(n+2) can be powered by the n+2th stage shift register The capacitor in the circuit is individually compensated to the nth stage control signal Q(n), so the nth stage control signal Q(n) at this time is controlled by the n-2th level control signal Q(n-2) and the n+2 stage. The control signal Q(n+2) is raised to the second working voltage level II; when the nth high frequency clock signal HC(n) is at the high voltage level, the nth stage gate control signal G(n) The second capacitor C2 can be compensated to the nth control signal Q(n), so that the nth control signal Q(n) is raised to the third operating voltage level III, although the nth- The level 2 control signal Q(n-2) is the lower fourth operating voltage level IV, and the nth level control signal Q(n) is pulled down slightly, but since the nth stage control signal Q(n) in the previous stage The second operating voltage level II of the nth stage control signal Q(n) is still higher than the voltage level of the nth stage control signal Q(n). When the n-2th control signal Q(n-2) returns to the low voltage level, and the n+2th control signal Q(n+2) is the third operating voltage level III, although the nth - Level 2 control signal Q(n-2) has returned to the low voltage level, but the third operation of the n+2 level control signal Q(n+2) The voltage level III is greater than the low voltage level of the n-2th control signal Q(n-2), so the n+2th control signal Q(n+2) can still compensate the nth level control signal Q(n). The voltage level is such that the nth control signal Q(n) maintains a higher fourth operating voltage level IV.

Since the shift register embodiment of the present invention can control the nth level control signal Q by the n-2th level control signal Q(n-2) and the n+2 level control signal Q(n+2) ( n) compensation, so after the nth stage control signal Q(n) is raised to the first working voltage level I and before the nth high frequency clock signal HC(n) is high voltage level floating (floating In the phase, the nth control signal Q(n) can be raised to the second operation by the compensation of the n-2th control signal Q(n-2) and the n+2 control signal Q(n+2) Voltage level II can effectively reduce the impact of leakage and noise on the nth control signal Q(n). In addition, because of the n+2 level control The signal signal Q(n+2) can compensate the nth stage control signal Q(n) after the nth stage high frequency clock signal HC(n) returns to the low voltage level, so that the nth stage control signal Q(n) After the nth high frequency clock signal HC(n) returns to the low voltage level, it can be maintained at a higher fourth operating voltage level IV, so that the nth stage control signal Q(n) can still maintain better. The driving capability, so the nth gate control signal G(n) can be quickly pulled down to the low voltage level through the transistor T11.

3A is a high frequency clock signal embodiment used in the 3D display mode of the shift register circuit of the first embodiment, which includes the n-4th high frequency clock signal HC(n-4), the n-th Level 3 high frequency clock signal HC(n-3), n-2th high frequency clock signal HC(n-2), n-1th high frequency clock signal HC(n-1), nth Level high frequency clock signal HC(n), n+1th high frequency clock signal HC(n+1), n+2 high frequency clock signal HC(n+2) and n+3 level High frequency clock signal HC(n+3), and n-4th high frequency clock signal HC(n-4), n-3th high frequency clock signal HC(n-3), n-th Level 2 high frequency clock signal HC(n-2), n-1th high frequency clock signal HC(n-1), nth stage high frequency clock signal HC(n), n+1th high The frequency pulse signal HC(n+1), the n+2 high frequency clock signal HC(n+2), and the n+3 high frequency clock signal HC(n+3) have the same enabling time. The n+3th high frequency clock signal HC(n+3) is the same as the n+2th high frequency clock signal HC(n+2) and is behind the n+1th high frequency clock signal HC(n). +1) with the nth high frequency clock signal HC(n) for a preset time, the n+1th high frequency clock signal HC(n+1) and the nth high frequency clock signal HC(n) Same and behind the n-1th high frequency Clock signal HC(n-1) and n-2th high frequency clock signal HC(n-2) for a preset time, n-1th high frequency clock signal HC(n-1) and nth - Level 2 high frequency clock signal HC(n-2) is the same and behind the n-3th high frequency clock signal HC(n-3) and the n-4th high frequency clock signal HC(n-4) A preset time.

Next, please refer to FIG. 3B, and the n-th level control is illustrated with FIG. 3A. Compensation method for signal Q(n). The n-2th control signal Q(n-2), the nth control signal Q(n), and the n+2th control signal Q(n+2) all include a first working voltage level I and a second operation. The voltage level II, the third working voltage level III and the fourth working voltage level IV. When the high-frequency signal of the n-4th stage shift register circuit, that is, the n-4th high-frequency clock signal HC(n-4) is a high voltage level, the nth stage control The signal Q(n) will be raised to the first working voltage level I; then, the high-frequency clock signal of the n-th level control signal Q(n), that is, the n-th high-frequency clock signal HC ( n) When the high voltage level is not yet established, since the n-2th control signal Q(n-2) is raised to the third working voltage level III, the n+2th control signal Q(n+2) Raised to the first operating voltage level I, so the n-2th control signal Q(n-2) can be controlled by the capacitor C1 and the n+2th level control signal Q(n+2) as shown in FIG. The capacitor in the n+2th stage shift register circuit can be individually compensated to the nth stage control signal Q(n), so the nth stage control signal Q(n) at this time is controlled by the n-2th stage. The signal Q(n-2) and the n+2th control signal Q(n+2) are raised to a higher second operating voltage level II; when the nth high frequency clock signal HC(n) is a high voltage At the level, since the nth gate control signal G(n) can be compensated to the nth control signal Q(n) by the second capacitor C2 of FIG. 1A, the nth stage control The number Q(n) is raised to the third working voltage level III, and the n-2th control signal Q(n-2) at this time is the fourth working voltage which is lowered to the lower by the third working voltage level III. In the stage of the level IV, the n+2th control signal Q(n+2) is in the stage of rising from the second working voltage level II to the third working voltage level III, so the nth stage control signal Q ( n) The third operating voltage level III is only slightly affected by the n-2th control signal Q(n-2) and the n+2th control signal Q(n+2), and due to the nth level control The signal Q(n) has been previously raised to the higher second operating voltage level II, so the third operating voltage level III of the nth control signal Q(n) is still higher than the conventional nth level control signal. The third operating voltage level III of the number Q(n); and the nth stage control signal Q(n) is at the stage of the fourth operating voltage level IV, since the nth stage control signal Q(n) is due to the nth +4 level gate control signal G(n+4) and fast pull-down to low voltage level, so it is not affected by the n-2th level control signal Q(n-2) and the n+2 level control signal Q(n+ 2) The impact.

In the 3D display mode, the shift register embodiment of the present invention can be used by the n-2th control signal Q(n-2) and the n+2th control signal Q(n+2). The n-level control signal Q(n) is compensated, so after the n-th control signal Q(n) is raised to the first working voltage level I and the n-th high-frequency clock signal HC(n) is high voltage In the floating phase before the bit, the nth control signal Q(n) can be raised by the compensation of the n-2th control signal Q(n-2) and the n+2th control signal Q(n+2). The high second operating voltage level II can improve the driving capability of the overall n-th control signal Q(n), effectively reducing the leakage and the influence of noise on the n-th control signal Q(n).

Please refer to FIG. 4A. FIG. 4A shows a fourth embodiment of the present invention. The present embodiment can be applied to a 2D display mode. The difference between FIG. 4A and FIG. 1 is that the second pull-up circuit 20 of FIG. 4A is used to output the n+th. The level 2 control signal Q(n+2), that is, the shift register circuit of the first transmission 3 in this embodiment. In addition, the control terminals of the transistor T71 and the transistor T72 of the main pull-down circuit 70 of the embodiment are configured to receive the n+2th gate control signal G(n+2) to be based on the n+2th gate. The control signal G(n+2) is used to pull the nth control signal Q(n) and the nth gate control signal G(n) to a low voltage level. Moreover, the first end of the capacitor C1 of the embodiment is configured to receive the n-1th level control signal Q(n-1), that is, the n-1th level control signal Q(n-1) can be used in this embodiment. Compensating the nth level control signal Q(n) of this stage, the nth level control signal Q(n) can also be compensated for the n-1th level control signal Q(n-1). Similarly, the nth level of the level is known. Level control signal Q(n) The n+1th control signal Q(n+1) or the n+1th control signal Q(n+1) may be compensated by the capacitance of the n+1th stage shift register circuit. The n-level control signal Q(n), the detailed compensation method will be further explained with the drawing.

Please refer to FIG. 4B. FIG. 4B is a fifth embodiment of the shift register circuit of the present invention. FIG. 4B is different from FIG. 4A in that the first end of the transistor T22 of the second pull-up circuit 20 can be connected to the transistor T22. The control terminal is electrically coupled, that is, when the transistor T21 is turned on, the transistor T22 receives the first end of the transistor T22 according to the nth high frequency clock signal HC(n) received by the control terminal. The n-stage high frequency clock signal HC(n) is output as the n+2th control signal Q(n+2).

Please refer to FIG. 4C. FIG. 4C is a sixth embodiment of the shift register circuit of the present invention. FIG. 4C is different from FIG. 4A in that the second pull-up circuit 20 can include a transistor T23, and the transistor T23 includes a first end. The second end and the control end are electrically coupled to the first end and the control end for receiving the nth gate control signal G(n). Therefore, the transistor T23 is based on the nth gate control signal G. (n) outputting the nth gate control signal G(n) received by the first terminal as the n+2th control signal Q(n+2).

5 is a high frequency clock signal embodiment of a shift register circuit of the fourth embodiment for driving a liquid crystal display in a dot inversion manner, which includes an n-2th high frequency clock signal HC(n-2), The n-1th high frequency clock signal HC(n-1), the nth high frequency clock signal HC(n), the n+1th high frequency clock signal HC(n+1), and the nth -2 high frequency clock signal HC(n-2), n-1th high frequency clock signal HC(n-1), nth high frequency clock signal HC(n) and n+1th stage The high frequency clock signal HC(n+1) has the same enabling time, and the n+1th high frequency clock signal HC(n+1) is behind the nth stage high frequency clock signal HC(n). Set the time, the nth high frequency clock signal HC(n) and the n-1th high frequency The pulse signal HC(n-1) is a preset time, the n-1th high frequency clock signal HC(n-1) is behind the n-2th high frequency clock signal HC(n-2). time.

Next, the n-th control signal Q(n) will be mainly used to explain the compensation mode. The n-1th control signal Q(n-1), the nth control signal Q(n), and the n+1th control signal Q(n+1) all include the first working voltage level I and the second operation. The voltage level II, the third working voltage level III and the fourth working voltage level IV. According to FIG. 4A, the nth stage shift register circuit outputs the n+2th control signal Q(n+2). Similarly, the n-2th stage shift register circuit outputs. The nth stage controls the signal Q(n), so when the nth stage shift register circuit has the high frequency signal of the current stage, that is, the n-2th high frequency clock signal HC(n-2) is high. At the voltage level, the nth control signal Q(n) is raised to the first operating voltage level I; then, the high frequency clock signal of the current level of the nth control signal Q(n) is also When the nth high frequency clock signal HC(n) is not at the high voltage level, since the n-1th control signal Q(n-1) is raised to the third working voltage level III, the nth The +1 level control signal Q(n+1) is raised to the first working voltage level I, so the n-1th level control signal Q(n-1) can be passed through the first capacitor C1 described in FIG. 4A. The n+1th control signal Q(n+1) can be individually compensated to the nth stage control signal Q(n) by the capacitance in the n+1th stage shift register circuit, so the nth stage at this time The control signal Q(n) is raised to the second working voltage level II by the n-1th control signal Q(n-1) and the n+1th control signal Q(n+1); When the n-stage high frequency clock signal HC(n) is at a high voltage level, the nth gate control signal G(n) can be compensated to the nth level control signal Q(n) by the second capacitor C2 of FIG. 4A. Therefore, the nth control signal Q(n) is raised to the third operating voltage level III, although the n-1th control signal Q(n-1) at this time is the lower fourth operating voltage level. IV, the n-th control signal Q(n) will be pulled down slightly, but the n-th control signal Q(n) has been boosted in the previous stage. Up to the second operating voltage level II, so that the third operating voltage level III of the nth control signal Q(n) is still higher than the voltage level of the conventional nth control signal Q(n); When the n-1th control signal Q(n-1) returns to the low voltage level, and the n+1th control signal Q(n+1) is the third operating voltage level III, although the n-1th The level control signal Q(n-1) has returned to the low voltage level, but the third operating voltage level III of the n+1th control signal Q(n+1) is greater than the n-1th level control signal Q(n -1) low voltage level, so the n+1th control signal Q(n+1) can still compensate the voltage level of the nth stage control signal Q(n), so that the nth stage control signal Q(n) Maintain a higher fourth operating voltage level IV.

According to the above, when the liquid crystal display is driven in a dot inversion manner, since the n-1th stage control signal Q(n-1) and the n+1th level control signal Q(n+1) can be used in this embodiment. The n-th control signal Q(n) is compensated, so after the n-th control signal Q(n) is raised to the first working voltage level I and the n-th high-frequency clock signal HC(n) is In the floating state before the high voltage level, the nth control signal Q(n) can be compensated by the n-1th control signal Q(n-1) and the n+1th control signal Q(n+1) And raised to the second working voltage level II, effectively reducing the impact of leakage and noise on the nth control signal Q(n), and, in addition, because the n+1th control signal Q(n+1) can be in the first After the n-level high-frequency clock signal HC(n) returns to the low voltage level, the n-th control signal Q(n) is compensated, so that the n-th control signal Q(n) is in the n-th high-frequency clock signal HC ( n) After returning to the low voltage level, the fourth operating voltage level IV can be maintained, so that the nth stage control signal Q(n) maintains a better driving capability, so the nth stage gate control signal G(n) can be Quickly pull down to the low voltage level through transistor T11.

6 is a high frequency clock signal of the fourth embodiment of the shift register circuit for driving the liquid crystal display in a line inversion manner, which includes the n-2th high frequency clock signal HC(n-2), nth -1 high frequency clock signal HC(n-1), nth level The high frequency clock signal HC(n) and the n+1th high frequency clock signal HC(n+1), and the n-2th high frequency clock signal HC(n-2), the n-1th stage The high frequency clock signal HC(n-1), the nth high frequency clock signal HC(n), and the n+1th high frequency clock signal HC(n+1) have the same enabling time, nth The +1 level high frequency clock signal HC(n+1) lags behind the nth stage high frequency clock signal HC(n) for a preset time, and the nth stage high frequency clock signal HC(n) falls behind the n-1th stage. The high frequency clock signal HC(n-1) is a preset time, and the n-1th high frequency clock signal HC(n-1) lags behind the n-2th high frequency clock signal HC(n-2) Preset time.

Next, the compensation method of the nth stage control signal Q(n) will be described. The n-1th control signal Q(n-1), the nth control signal Q(n), and the n+1th control signal Q(n+1) all include the first working voltage level I and the second operation. The voltage level II, the third working voltage level III and the fourth working voltage level IV. When the high-frequency signal of the n-2th stage shift register circuit, that is, the n-2th high-frequency clock signal HC(n-2) is a high voltage level, the nth stage control The signal Q(n) will be raised to the first working voltage level I; then, the high-frequency clock signal of the n-th level control signal Q(n), that is, the n-th high-frequency clock signal HC ( n) When the high voltage level is not yet established, since the n-1th control signal Q(n-1) is raised to the third working voltage level III, the n+1th control signal Q(n+1) It is raised to the first working voltage level I, so the n-1th level control signal Q(n-1) can be controlled by the first capacitor C1 and the n+1th level control signal Q(n+) as shown in FIG. 4A. 1) The first capacitor in the n+1th shift register circuit can be individually compensated to the nth control signal Q(n), so the nth control signal Q(n) at this time is nth -1 level control signal Q(n-1) and n+1th level control signal Q(n+1) are raised to a higher second working voltage level II; when the nth stage high frequency clock signal HC(n When the voltage is at a high voltage level, since the nth gate control signal G(n) can be compensated to the nth control signal Q(n) by the second capacitor C2 of FIG. 4A, The nth control signal Q(n) is raised to the third working voltage level III, and the n-1th control signal Q(n-1) at this time is lowered to the lower by the third working voltage level III. The fourth operating voltage level IV, the n+1th control signal Q(n+2) will rise from the second working voltage level II to the third working voltage level III, so the nth stage control signal Q ( The third operating voltage level III of n) is only slightly affected by the n-1th control signal Q(n-1) and the n+1th control signal Q(n+1), and due to the nth stage control The signal Q(n) has been previously raised to the higher second operating voltage level II, so the third operating voltage level III of the nth control signal Q(n) is still higher than the conventional nth level control signal Q. (n) the third working voltage level III; and the nth stage control signal Q(n) is in the stage of the fourth working voltage level IV, since the nth stage control signal Q(n) is due to the n+2 The gate control signal G(n+2) is quickly pulled down to the low voltage level, so it is not affected by the n-1th control signal Q(n-1) and the n+1th control signal Q(n+1) Impact.

When the liquid crystal display is driven in a row inversion manner, since the nth stage control signal Q(n-1) and the n+1th level control signal Q(n+1) can be used for the nth stage. The control signal Q(n) is compensated, so after the nth stage control signal Q(n) is raised to the first working voltage level I and before the nth stage high frequency clock signal HC(n) is at the high voltage level The nth-level control signal Q(n) can be raised to a higher second operation by the compensation of the n-1th control signal Q(n-1) and the n+1th control signal Q(n+1). The voltage level II can improve the driving capability of the overall n-th control signal Q(n), effectively reducing the influence of leakage and noise on the n-th control signal Q(n).

In summary, the embodiment of the shift register circuit of the present invention can electrically couple the control signal of the nth-stage shift register circuit and the n+m-level shift register circuit by using a capacitor. Control the signal so that the control signal of this level is in the case of 2D display mode or 3D display mode. It can be compensated by the np-level control signal and the n+m-level control signal to improve the driving ability of the control signal of this level, and it can effectively avoid the driving ability of the control signal of this level is low or driven due to external signal interference or leakage. In the case of errors, etc., the situation in which the shift register is not normally used is greatly reduced.

However, the above description is only the preferred embodiment of the present invention, and the equivalent changes or modifications made by the scope of the present invention and the contents of the specification are still in the present invention. Within the scope of the patent.

10‧‧‧First pull-up circuit

20‧‧‧Second pull-up circuit

30‧‧‧First pull-down control circuit

40‧‧‧First pull-down circuit

50‧‧‧Second pull-down control circuit

60‧‧‧Second pull-down circuit

70‧‧‧Main pull-down circuit

T11, T21, T22, T31, T32, T33, T34, T41, T42, T51, T52, T53, T54, T61, T62, T71, T72‧‧

C1‧‧‧first capacitor

C2‧‧‧second capacitor

LC1‧‧‧ first clock signal

LC2‧‧‧ second clock signal

HC(n)‧‧‧n-level high frequency clock signal

Q(n)‧‧‧n level control signal

Q(n-2)‧‧‧n-2 level control signal

Q(n+4)‧‧‧n+4 control signals

G(n)‧‧‧n-th gate control signal

G(n+4)‧‧‧th n+4 gate control signal

VSS1‧‧‧low voltage level

P(n)‧‧‧first pulldown control signal

K(n)‧‧‧Second pull-down control signal

Claims (13)

A shift register circuit includes: a first pull-up circuit for receiving a high frequency clock signal, and determining whether to output an nth gate control signal according to an nth level control signal; The second pull-up circuit is electrically coupled to the first pull-up circuit for outputting an n+m-level control signal; and a first pull-down control circuit is configured to receive a first clock signal. And outputting a first pull-down control signal according to the first clock signal and the n-th control signal; a first pull-down circuit is configured to determine whether to control the n-th stage according to the first pull-down control signal The signal and the nth gate control signal are stabilized at a low voltage level; a second pull-down control circuit is configured to receive a second clock signal and control the second clock signal according to the second clock signal The signal outputting a second pull-down control signal; a second pull-down circuit is configured to determine, according to the second pull-down control signal, whether the n-th control signal and the n-th gate control signal are stabilized at the low voltage level a main pull-down circuit for controlling the gate according to an n+m level Deciding whether to stabilize the nth control signal and the nth gate control signal at the low voltage level; and a first capacitor having a first end and a second end, the first end of which is for receiving An nth-level control signal, wherein the second end is electrically coupled to the n-th control signal; Where m, n and p are positive integers. The shift register circuit of claim 1, wherein the n-th level control signal is an n-2th control signal or an n-1th control signal. The shift register circuit according to claim 1, wherein the n+m level control signal is an n+4th control signal or an n+2th control signal. The shift register circuit of claim 1, wherein the second pull-up circuit comprises: a first transistor having a first end, a second end, and a control end, the first end of which is configured to receive the high a frequency clock signal, the control end is configured to receive the nth stage control signal; and a second transistor has a first end, a second end, and a control end, the first end of which is configured to receive the nth stage The gate control signal is electrically coupled to the second end of the first transistor, and the second end is configured to output the n+mth level control signal. The shift register circuit of claim 1, wherein the second pull-up circuit comprises: a first transistor having a first end, a second end, and a control end, the first end of which is configured to receive the high a frequency clock signal, the control end is configured to receive the nth stage control signal; and a second transistor has a first end, a second end, and a control end, wherein the first end and the control end are used to The second end of the first transistor is electrically The second end is configured to output the n+mth level control signal. The shift register circuit of claim 1, wherein the second pull-up circuit comprises a first transistor having a first end, a second end, and a control end, the first end thereof and the control The end system is configured to receive the nth level gate control signal, and the second end is configured to output the n+m level control signal. The shift register circuit of claim 1, wherein the first pull-down control circuit comprises: a third transistor having a first end, a second end, and a control end, the first end and the control end For receiving the first clock signal; a fourth transistor having a first end, a second end, and a control end, the first end of which is electrically coupled to the first end of the third transistor, and the control thereof The second end is electrically coupled to the second end of the third transistor, and the second end is configured to output the first pull-down control signal; a fifth transistor having a first end, a second end, and a control end The first end is electrically coupled to the second end of the third transistor, the control end is configured to receive the nth stage control signal, and the second end is configured to be electrically coupled to the low voltage level And a sixth transistor having a first end, a second end, and a control end, wherein the first end is electrically coupled to the first pull-down control signal, and the control end is configured to receive the n-th stage The second end of the control signal is electrically coupled to the low voltage level. The shift register circuit as claimed in claim 1, the first pull-down circuit The method includes: a seventh transistor having a first end, a second end, and a control end, wherein the first end is electrically coupled to the nth stage control signal, and the control end is configured to receive the first pull down control a signal, the second end of the second end is electrically coupled to the low voltage level; and an eighth transistor having a first end, a second end, and a control end, the first end thereof and the nth stage gate The control signal is electrically coupled to the first pull-down control signal, and the second end is electrically coupled to the low voltage level. The shift register circuit of claim 1, wherein the second pull-down control circuit comprises: a ninth transistor having a first end, a second end, and a control end, wherein the first end and the control end are used Receiving the second clock signal; a tenth transistor having a first end, a second end and a control end, the first end of which is electrically coupled to the first end of the ninth transistor, and the control end thereof The second end of the ninth transistor is electrically coupled to the second end of the ninth transistor for outputting the second pull-down control signal; the eleventh transistor has a first end, a second end, and a control end, The first end is electrically coupled to the second end of the ninth transistor, the control end is configured to receive the nth stage control signal, and the second end is electrically coupled to the low voltage level And a twelfth transistor having a first end, a second end and a control end, wherein the first end is electrically coupled to the second pull-down control signal, and the control end is configured to receive the n-th level control The second end of the signal is electrically coupled to the low voltage level. The shift register circuit of claim 1, wherein the second pull-down circuit comprises: a thirteenth transistor having a first end, a second end, and a control end, the first end and the nth stage The control signal is electrically coupled, and the control end is configured to receive the second pull-down control signal, the second end is electrically coupled to the low voltage level; and the fourteenth transistor has a The first end, the second end and the control end are electrically coupled to the first-stage gate control signal, and the control end is configured to receive the second pull-down control signal, and the second end is used for The low voltage level is electrically coupled. The shift register circuit of claim 1, wherein the first pull-up circuit comprises: a fifteenth transistor having a first end, a second end, and a control end, the first end of which is configured to receive The high frequency clock signal has a control end for receiving the nth stage control signal, a second end for outputting the nth stage gate control signal, and a second end having a first end and The second end is electrically coupled to the second end of the fifteenth transistor, and the second end is electrically coupled to the nth stage control signal. The shift register circuit of claim 1, wherein the main pull-down circuit comprises: a sixteenth transistor having a first end, a second end, and a control end, the first end of which is used to The n-level control signal is electrically coupled, and the control end is configured to receive the n+m-th gate control signal, and the The two ends are electrically coupled to the low voltage level; and a seventeenth transistor has a first end, a second end and a control end, the first end of which is used for the nth stage gate The pole control signal is electrically coupled, and the control end is configured to receive the n+mth level gate control signal, and the second end is configured to be electrically coupled to the low voltage level. The shift register circuit of claim 12, wherein the n+mth gate control signal is an n+4th gate control signal or an n+2th gate control signal.