TWI495080B - Integrated circuit package in package system with adhesiveless package attach and method of forming the same - Google Patents

Integrated circuit package in package system with adhesiveless package attach and method of forming the same Download PDF

Info

Publication number
TWI495080B
TWI495080B TW097120150A TW97120150A TWI495080B TW I495080 B TWI495080 B TW I495080B TW 097120150 A TW097120150 A TW 097120150A TW 97120150 A TW97120150 A TW 97120150A TW I495080 B TWI495080 B TW I495080B
Authority
TW
Taiwan
Prior art keywords
package
integrated circuit
encapsulant
lead
leads
Prior art date
Application number
TW097120150A
Other languages
Chinese (zh)
Other versions
TW200905857A (en
Inventor
Henry Descalzo Bathan
Zigmund Ramirez Camacho
Lionel Chien Hui Tay
Jeffrey D Punzalan
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200905857A publication Critical patent/TW200905857A/en
Application granted granted Critical
Publication of TWI495080B publication Critical patent/TWI495080B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

具有無黏性封裝件固接之積體電路封裝件內封裝件系統及其形成方法Package system in integrated circuit package with non-adhesive package fixing and forming method thereof

本發明大致上係關於積體電路封裝件系統，且尤係關於一種用於具有封裝件內封裝件的積體電路封裝件之系統。SUMMARY OF THE INVENTION The present invention generally relates to integrated circuit package systems, and more particularly to a system for an integrated circuit package having a package within a package.

現代消費者電子個人攜帶式裝置(例如手機、數位相機與音樂撥放器)須要增加積體電路晶片的內容用以安裝於越來越小(ever-shrinking)的實體空間中以及增加效能。Modern consumer electronic personal portable devices (such as cell phones, digital cameras, and music players) need to increase the content of integrated circuit chips for installation in ever-shrinking physical spaces and increase performance.

對於較小、較高效能之半導體裝置的需求已刺激了用於製造較小且較不昂貴的半導體裝置之新技術的發展。其中一種技術係涉及將積體電路晶片儘可能的封裝入越小的形狀中以及儘可能有效率地生產積體電路晶片。The demand for smaller, higher performance semiconductor devices has spurred the development of new technologies for fabricating smaller and less expensive semiconductor devices. One of the techniques involves packaging the integrated circuit wafer into a smaller shape as much as possible and producing the integrated circuit wafer as efficiently as possible.

通常，很多單獨裝置係由相同晶圓構成。當該裝置被區分為個別矩形單元時，每一個均成為積體電路晶片的形狀。為了將晶片與其他電路接合，通常將其與引線指(lead finger)固定且個別地將晶片上的墊(pad)連接至使用極佳電線的引線指。然後，該組裝件(assembly)藉由個別地將其封裝入壓模塑膠或陶瓷本體來進行封裝。Typically, many individual devices are constructed from the same wafer. When the device is divided into individual rectangular units, each becomes the shape of the integrated circuit wafer. In order to bond the wafer to other circuits, it is typically secured to the lead fingers and the pads on the wafer are individually connected to the lead fingers using the excellent wires. The assembly is then packaged by individually encapsulating it into a molded plastic or ceramic body.

比起減少電路中必要元件的數量，積體電路封裝技術表現於增加安裝於單一電路板或基板的晶片數量。如此導致封裝設計於實體尺寸或裝置形狀越來越緊密，且於整體積體電路密度中有顯著的增加。然而，積體電路密度持續被於基板上安裝晶片的可用面積所限制。Integral circuit packaging techniques are shown to increase the number of wafers mounted on a single circuit board or substrate, rather than reducing the number of components necessary in the circuit. This results in a package design that is increasingly compact in physical size or device shape and has a significant increase in overall bulk circuit density. However, the integrated circuit density is constantly limited by the available area of the wafer on which the substrate is mounted.

為了壓縮個別裝置的封裝，封裝件已發展至可於每一封裝件部位一次封裝一個以上的裝置。每一封裝件部位為對個別積體電路裝置提供機械支持的結構。該結構也提供一個或多個可使得該裝置電性地連接至周圍電路之互連線層。In order to compress the package of individual devices, packages have evolved to package more than one device at a time in each package. Each package location is a structure that provides mechanical support to individual integrated circuit devices. The structure also provides one or more interconnect layers that enable the device to be electrically connected to surrounding circuitry.

於某些情況，多重晶片(multi-chip)裝置可比對應的單一積體電路晶片較快速且較便宜地製造，如此能合併所有相同的功能。某些多重晶片模組已被發現用於增加電路密度與微型化(miniaturization)、改善信號傳播速度、減少整體裝置尺寸、改善效能以及降低成本。In some cases, a multi-chip device can be fabricated faster and cheaper than a corresponding single integrated circuit die, thus combining all of the same functions. Some multi-chip modules have been found to increase circuit density and miniaturization, improve signal propagation speed, reduce overall device size, improve performance, and reduce cost.

然而，這種多重晶片模組會非常龐大。封裝件密度係藉由用以於電路板上安裝晶片或模組所需的面積而決定。一種用於減少多重晶片模組的電路板尺寸而因此增加其有效密度之方法係於該模組或封裝件內垂直地堆疊晶片。這種設計是習知封裝件的改善方法，能於單一水平層中組合許多晶片且並排地連結被動元件。However, this multi-chip module can be very large. The package density is determined by the area required to mount the wafer or module on the board. One method for reducing the board size of a multi-wafer module and thus increasing its effective density is to vertically stack the wafers within the module or package. This design is an improved method of conventional packages that combines many wafers in a single horizontal layer and joins the passive components side by side.

然而，不管多重晶片模組係垂直地或水平地排列，仍會產生問題，因為於晶片與晶片連接測試前通常必須組裝該多重晶片模組。也就是，因為晶片上的電性結合墊(bond pad)非常小，因此於組裝入封裝件之前很難測試晶片。However, regardless of whether the multi-chip modules are arranged vertically or horizontally, problems still arise because the multi-wafer module must typically be assembled prior to the wafer-to-wafer connection test. That is, since the electrical bond pads on the wafer are very small, it is difficult to test the wafer before being assembled into the package.

當個別地安裝與連接晶片時，可測試晶片與連接點，以及然後，沒有缺點的已知良好單元(known-good-unit, KGU)係被組裝入較大的電路。使用KGU的製程因此較可靠且較不易於組裝由於不良晶片所引入的缺點。因為習知的 多重晶片模組，於最後組裝前該晶片無法被個別地認定為KGU。When the wafer is individually mounted and connected, the wafer and the connection point can be tested, and then, a known-good-unit (KGU) without defects is assembled into a larger circuit. Processes using KGU are therefore more reliable and less prone to assembly due to the disadvantages introduced by poor wafers. Because of the conventional The multi-wafer module cannot be individually identified as a KGU prior to final assembly.

雖然有於半導體製造與封裝技術近來發展的優點存在，對於改善封裝方法、系統與設計仍有持續的需求。Despite the recent advances in semiconductor fabrication and packaging technology, there is a continuing need to improve packaging methods, systems, and designs.

因此，對於提供較低的外形、增加封裝件系統中裝置的數量以及減少分層(delamination)、黏著劑與黏著失敗的積體電路封裝件內封裝件系統仍然有需求。考慮到積體電路的改良密度與尤其是攜帶式電子產品的需求，尋找這些問題的答案是越來越急迫。Accordingly, there is still a need for a package system for integrated circuit packages that provides a lower profile, increases the number of devices in the package system, and reduces delamination, adhesive, and adhesion failure. Given the improved density of integrated circuits and the need for especially portable electronic products, the answer to these questions is increasingly urgent.

這些問題之解決方案長期以來一直被尋求，但先前發展尚未教示或建議任何解決方案，因此這些問題之解決方案已長期困惑在此技術領域具有通常知識者。Solutions to these problems have long been sought, but previous developments have not taught or suggested any solutions, so solutions to these problems have long been confusing in the field of technology.

本發明提供一種具有實質上為平面之封裝件內封裝件引線表面之封裝件內封裝件引線，固接與該封裝件內封裝件引線表面實質上共面之具有第一封裝膠體表面之第一積體電路封裝件，固接鄰近該第一積體電路封裝件之第二積體電路，以及，於第一積體電路封裝件與第二積體電路上方形成封裝件內封裝件封裝膠體。The present invention provides a package inner lead having a lead surface of a package in a substantially planar package, the first of which has a first encapsulant surface that is substantially coplanar with the lead surface of the package within the package The integrated circuit package is fixed to the second integrated circuit adjacent to the first integrated circuit package, and the package encapsulant colloid is formed over the first integrated circuit package and the second integrated circuit.

除了上述範例以外或代替上述範例外，本發明的某些實施例還具有其他態樣。當透過參考附加圖式來研讀以下詳細的說明，對於本技術領域具有通常知識之人而言，這些態樣將會變得明顯。In addition to or in place of the above examples, certain embodiments of the invention have other aspects. These details will become apparent to those of ordinary skill in the art in view of the following detailed description.

以下實施例係充分詳細描述以使熟悉本領域之技藝人士可製造及使用本發明。其他實施例依此揭露可明瞭而理解，並且可改變其系統、製程或機構而未悖離本發明之範疇。The following examples are described in sufficient detail to enable those skilled in the art to make and use the invention. Other embodiments are disclosed and understood, and the system, process, or mechanism may be modified without departing from the scope of the invention.

於下列敘述中，係給定數個詳細說明以提供本發明之完整瞭解。然而，該發明之實施可為顯而易見者則不會有這些詳細細節。為避免模糊本發明，一些已知的電路、系統配置及製程步驟未詳細地揭露。同樣地，本發明系統實施例之該些圖式的顯示係為概略的且未按比例縮放，且特別地，一些尺寸為清楚呈現本發明而誇大地顯示於圖式中。In the following description, numerous details are set forth to provide a complete understanding of the invention. However, the implementation of the invention may be obvious without these details. In order to avoid obscuring the present invention, some known circuits, system configurations, and process steps have not been disclosed in detail. In the same manner, the drawings of the embodiments of the present invention are shown in the drawings and are not to scale, and in particular, some of the dimensions are exaggeratedly shown in the drawings.

另外，在多個實施例中揭露及描述具有某些共同特徵，為清楚及容易說明、描述及理解，彼此相似及相同特徵將一般以相同參考編號來描述。實施例可被標號為第一實施例、第二實施例等，以方便描述標的物且並不具有任何重要性或提供本發明的限制。In addition, the various features and advantages of the invention are disclosed and described in the various embodiments. The embodiments may be referred to as the first embodiment, the second embodiment, etc., to facilitate the description of the subject matter and do not have any importance or provide a limitation of the present invention.

為了說明的原因，在此使用的用語“水平(horizontal)”係定義為平行本發明的平面或表面，無論其方向；用語“垂直(vertical)”係指垂直所定義的“水平”之方向，用語，如“在…上(on)”、“在…上面(above)”、“在…下面(below)”、“底部(bottom)”、“上方(top)”、“側邊(side)”(如在“側壁(sidewall)”)、“較高(higher)”、“較低(lower)”、“上面的(upper)”、“覆於…上(over)”以及“在…之下(under)”，係相對該水平平面而定義。For the purposes of this description, the term "horizontal" is used herein to mean a plane or surface that is parallel to the invention, regardless of its orientation; the term "vertical" refers to the direction of the "horizontal" defined vertically. Terms such as "on", "above", "below", "bottom", "top", "side" (eg in "sidewall"), "higher", "lower", "upper", "over" and "in" Under, defined relative to the horizontal plane.

於此使用的用語“在…上(on)”係指在元件間有直接接觸。於此使用的用語“處理(processing)”包含材料沉積、圖案化、曝光、顯影、蝕刻、清洗、與/或如需要於形成所述結構之材料或修整(trimming)之移除。於此使用的用語“系統(system)”意指且係指依照上下文使用該用語的本發明之方法及裝置。The term "on" as used herein refers to direct contact between elements. The term "processing" as used herein includes material deposition, patterning, exposure, development, etching, cleaning, and/or removal of materials or trimming as needed to form the structure. The term "system" as used herein refers to and refers to the method and apparatus of the present invention that uses the term in accordance with the context.

現在參考第1圖，顯示本發明之實施例中沿著第2圖的線1-1之積體電路封裝件內封裝件系統100之剖面圖。該積體電路封裝件內封裝件系統100較佳地包含具有第一封裝膠體(encapsulant)104之第一積體電路封裝件102。該第一積體電路封裝件102之第一封裝膠體104可包含較佳地形成具有實質上平面表面之第一封裝膠體表面106。Referring now to Fig. 1, there is shown a cross-sectional view of the package circuit system 100 in the integrated circuit package along line 1-1 of Fig. 2 in an embodiment of the present invention. The integrated circuit package inner package system 100 preferably includes a first integrated circuit package 102 having a first encapsulant 104. The first encapsulant 104 of the first integrated circuit package 102 can include a first encapsulant surface 106 that preferably forms a substantially planar surface.

該第一封裝膠體表面106可形成於第一封裝件積體電路108、第一封裝件晶片墊110、以及第一封裝件引線112上。第一封裝件積體電路108可隨著第一封裝件安裝層114(如黏著劑層)安裝於該第一封裝件晶片墊110上。該第一封裝件積體電路108可隨著第一封裝件連接器116(如結合導線)電性連接至該第一封裝件引線112。The first encapsulant surface 106 can be formed on the first package integrated circuit 108, the first package wafer pad 110, and the first package leads 112. The first package integrated circuit 108 can be mounted on the first package wafer pad 110 along with a first package mounting layer 114 (eg, an adhesive layer). The first package integrated circuit 108 can be electrically connected to the first package lead 112 along with the first package connector 116 (eg, a bonding wire).

該積體電路封裝件內封裝件系統100也較佳地包含第二積體電路118。該第二積體電路118可隨著第二安裝層120(如黏著劑)安裝於該第一積體電路封裝件102上。該第二積體電路118可隨著第二連接器122(如結合導線)電性連接至該第一積體電路封裝件102。The integrated circuit package inner package system 100 also preferably includes a second integrated circuit 118. The second integrated circuit 118 can be mounted on the first integrated circuit package 102 along with the second mounting layer 120 (eg, an adhesive). The second integrated circuit 118 can be electrically connected to the first integrated circuit package 102 along with the second connector 122 (eg, a bonding wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件 102可較佳地固接於該積體電路封裝件內封裝件系統100而不需要黏著劑。該第一積體電路封裝件102以及因此該第二積體電路118可隨著封裝件內封裝件連接器126(如結合導線)電性連接至封裝件內封裝件引線124。該封裝件內封裝件引線124較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。The first integrated circuit package is for the non-adhesive package fixing The 102 can be preferably secured to the package system 100 within the integrated circuit package without the need for an adhesive. The first integrated circuit package 102 and thus the second integrated circuit 118 can be electrically coupled to the package inner package leads 124 with the package inner package connector 126 (eg, bonding wires). The package inner package leads 124 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統100較佳地包含封裝件內封裝件封裝膠體128。該封裝件內封裝件封裝膠體128可提供結構上的完整與保護給該第一積體電路封裝件102、該第二積體電路118、該第二連接器122、該封裝件內封裝件連接器126、以及該封裝件內封裝件引線124之部分。該第一封裝膠體表面106可與藉由封裝件內封裝件封裝膠體128之封裝件內封裝件安裝表面130以及封裝件內封裝件引線124之封裝件內封裝件引線表面132所形成之平面實質上共面。The integrated circuit package inner package system 100 preferably includes an in-package package encapsulant colloid 128. The package inner package encapsulant 128 can provide structural integrity and protection to the first integrated circuit package 102, the second integrated circuit 118, the second connector 122, and the package inner package. The 126, and portions of the package leads 124 within the package. The first encapsulant surface 106 can be planar with the encapsulation mounting surface 130 of the package encapsulating the encapsulant 120 in the package and the package lead surface 132 of the package in the package. On the surface.

雖然了解到可以使用任何數量之該第一積體電路封裝件102或該第二積體電路118，但為了描述的目的，該積體電路封裝件內封裝件系統100顯示具有該第一積體電路封裝件102其中一者以及該第二積體電路118其中一者。舉例而言，具有安裝於每一第一積體電路封裝件102上之該第二積體電路118之兩組第一積體電路封裝件102可相鄰且彼此相互連接。對於本技術領域中具有通常知識者將會很明顯知道，該積體電路封裝件內封裝件系統100的任何實施例可包含任何數量的第一積體電路封裝件102或第 二積體電路118。Although it is understood that any number of the first integrated circuit package 102 or the second integrated circuit 118 can be used, the integrated circuit package inner package system 100 is shown to have the first integrated body for purposes of description. One of the circuit packages 102 and one of the second integrated circuits 118. For example, two sets of first integrated circuit packages 102 having the second integrated circuit 118 mounted on each of the first integrated circuit packages 102 may be adjacent and connected to each other. It will be apparent to those of ordinary skill in the art that any embodiment of the integrated circuit package package system 100 can include any number of first integrated circuit packages 102 or The second integrated circuit 118.

經發現，具有無黏性封裝件固接之該積體電路封裝件內封裝件系統100排除了另一晶片固接槳(paddle)或黏著劑接合線(bondline)的需求以顯著地改善垂直空間或尺寸以及提供較低外形封裝件。進一步地，該積體電路封裝件內封裝件系統100顯著地簡化處理以及排除製程控制的複雜性以顯著地增加製程中可整合入封裝件內封裝件系統之裝置的數量。更進一步地，該積體電路封裝件內封裝件系統100顯著地減少來自該黏著劑層顯著地減少分層、黏著劑與黏著失敗之熱膨脹係數(coefficient of thermal expansion, CTE)的不匹配。The integrated circuit package package system 100 with a non-adhesive package has been found to eliminate the need for another wafer paddle or adhesive bondline to significantly improve vertical space. Or size and offer a lower profile package. Further, the integrated circuit package in-package system 100 significantly simplifies processing and eliminates the complexity of process control to significantly increase the number of devices in the process that can be integrated into the package system within the package. Still further, the integrated circuit package inner package system 100 significantly reduces the mismatch in the coefficient of thermal expansion (CTE) from the adhesive layer that significantly reduces delamination, adhesive and adhesion failure.

現在參考第2圖，顯示積體電路封裝件內封裝件系統100之上平面視圖。該積體電路封裝件內封裝件系統100較佳地包含封裝件內封裝件封裝膠體128與封裝件內封裝件引線124。該封裝件內封裝件引線124可選擇性地延伸而超過該封裝件內封裝件封裝膠體128的範圍。Referring now to Figure 2, there is shown a plan view of the package system 100 within the integrated circuit package. The integrated circuit package inner package system 100 preferably includes an in-package package encapsulant 128 and an in-package package lead 124. The package inner package leads 124 are selectively extendable beyond the range of the package encapsulants 128 within the package.

該封裝件內封裝件引線124的暴露部位202可提供電性連接至下一層級的系統。該暴露部位202可較佳地延伸至相鄰第1圖的封裝件內封裝件安裝表面130之第1圖之封裝件內封裝件引線表面132。該暴露部位202可選擇性地提供干擾裝設(如於基座中)、焊接連接點(如於表面底座上)、或結合表面(如用於接合導線)。The exposed portion 202 of the package lead 124 within the package can provide a system that is electrically connected to the next level. The exposed portion 202 can preferably extend to the package in-package lead surface 132 of FIG. 1 of the package mounting surface 130 of the package adjacent to FIG. The exposed portion 202 can optionally provide a distracting device (such as in a pedestal), a solder joint (such as on a surface mount), or a bonding surface (such as for bonding wires).

雖然了解到該積體電路封裝件內封裝件系統100可不同地形成為例如鋸開形態(sawn type)的四邊扁平無接腳 (quad flt no-lead, QFN)封裝件或突出引線QFN，但為了描述的理由，該積體電路封裝件內封裝件系統100顯示具有接近該暴露部位202之實心凸緣(solid flange)，作為在標準QFN中。Although it is understood that the package circuit system 100 in the integrated circuit package can be differently formed into a four-sided flat pinless type such as a sawn type. (quad flt no-lead, QFN) package or protruding lead QFN, but for reasons of description, the integrated circuit package inner package system 100 exhibits a solid flange having proximity to the exposed portion 202 as In the standard QFN.

進一步地，為了描述的理由，該積體電路封裝件內封裝件系統100顯示為正方形，雖然了解到該積體電路封裝件內封裝件系統100可為任何形狀。更進一步地，為了描述的理由，該積體電路封裝件內封裝件系統100顯示於每一邊具有八個封裝件內封裝件引線124，雖然了解到該積體電路封裝件內封裝件系統100可包含任何數量的封裝件內封裝件引線124。Further, for integrated reasoning, the integrated circuit package inner package system 100 is shown as a square, although it is understood that the package circuit system 100 can be of any shape within the integrated circuit package. Still further, for illustrative reasons, the integrated circuit package inner package system 100 is shown with eight package inner package leads 124 on each side, although it is understood that the integrated circuit package inner package system 100 is Any number of package inner package leads 124 are included.

現在參考第3圖，顯示本發明之第一實施例中積體電路封裝件內封裝件系統300之剖面圖。該積體電路封裝件內封裝件系統300較佳地包含具有第一封裝膠體304之第一積體電路封裝件302。該第一積體電路封裝件302之第一封裝膠體304可包含較佳地形成具有實質上平面表面之第一封裝膠體表面306。Referring now to Figure 3, there is shown a cross-sectional view of a package system 300 in an integrated circuit package in a first embodiment of the present invention. The integrated circuit package inner package system 300 preferably includes a first integrated circuit package 302 having a first encapsulant 304. The first encapsulant 304 of the first integrated circuit package 302 can include a first encapsulant surface 306 that preferably forms a substantially planar surface.

該第一封裝膠體表面306可形成於第一封裝件積體電路308、第一封裝件晶片墊310、以及第一封裝件引線312上。第一封裝件積體電路308可隨著第一封裝件安裝層314(如黏著劑層)安裝於該第一封裝件晶片墊310上。該第一封裝件積體電路308可隨著第一封裝件連接器316(如結合導線)電性連接至該第一封裝件引線312。The first encapsulant surface 306 can be formed on the first package integrated circuit 308, the first package wafer pad 310, and the first package leads 312. The first package integrated circuit 308 can be mounted on the first package wafer pad 310 along with a first package mounting layer 314, such as an adhesive layer. The first package integrated circuit 308 can be electrically connected to the first package lead 312 along with the first package connector 316 (eg, a bonding wire).

該積體電路封裝件內封裝件系統300也較佳地包含第 二積體電路318。該第二積體電路318可安裝於相鄰該第一積體電路封裝件302而不需要安裝層(如黏著劑)。第二積體電路安裝表面320可為實質上平面。該第二積體電路318可隨著第二連接器322(如結合導線)電性連接至該第一積體電路封裝件302。The integrated circuit package package system 300 also preferably includes Two integrated circuits 318. The second integrated circuit 318 can be mounted adjacent to the first integrated circuit package 302 without requiring a mounting layer (such as an adhesive). The second integrated circuit mounting surface 320 can be substantially planar. The second integrated circuit 318 can be electrically connected to the first integrated circuit package 302 along with the second connector 322 (eg, a bonding wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件302可較佳地固接於該積體電路封裝件內封裝件系統300而不需要黏著劑。該第一積體電路封裝件302以及該第二積體電路318可隨著封裝件內封裝件連接器326(如結合導線)電性連接至封裝件內封裝件引線324。該封裝件內封裝件引線324較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package fixing, the first integrated circuit package 302 can be preferably fixed to the package circuit system 300 in the integrated circuit package without requiring an adhesive. The first integrated circuit package 302 and the second integrated circuit 318 can be electrically connected to the package inner package leads 324 along the package inner package connector 326 (eg, bonding wires). The package inner package leads 324 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統300較佳地包含封裝件內封裝件封裝膠體328。該封裝件內封裝件封裝膠體328可提供結構上的完整與保護給該第一積體電路封裝件302、該第二積體電路318、該第二連接器322、該封裝件內封裝件連接器326、以及該封裝件內封裝件引線324之部分。該第一封裝膠體表面306以及該第二積體電路安裝表面320可與藉由封裝件內封裝件封裝膠體328之封裝件內封裝件安裝表面330以及封裝件內封裝件引線324之封裝件內封裝件引線表面332所形成之平面實質上共面。The integrated circuit package inner package system 300 preferably includes an in-package package encapsulant 328. The package inner package encapsulant 328 can provide structural integrity and protection to the first integrated circuit package 302, the second integrated circuit 318, the second connector 322, and the package in the package. The device 326, and portions of the package leads 324 within the package. The first encapsulant surface 306 and the second integrated circuit mounting surface 320 can be in a package with the package in-package mounting surface 330 and the in-package package leads 324 of the encapsulant 328 in the package. The plane formed by the package lead surface 332 is substantially coplanar.

現在參考第4圖，顯示本發明之第二實施例中積體電路封裝件內封裝件系統400之剖面圖。類似於該積體電路封裝件內封裝件系統300，該積體電路封裝件內封裝件系 統400較佳地包含具有第一封裝膠體404之第一積體電路封裝件402。該第一積體電路封裝件402之第一封裝膠體404可包含較佳地形成具有實質上平面表面之第一封裝膠體表面406。Referring now to Figure 4, there is shown a cross-sectional view of a package system 400 of an integrated circuit package in a second embodiment of the present invention. Similar to the integrated circuit package in-package system 300, the package in the integrated circuit package The system 400 preferably includes a first integrated circuit package 402 having a first encapsulant 404. The first encapsulant 404 of the first integrated circuit package 402 can include a first encapsulant surface 406 that preferably forms a substantially planar surface.

該第一封裝膠體表面406可形成於第一封裝件積體電路408、第一封裝件晶片墊410、以及第一封裝件引線412上。第一封裝件積體電路408可隨著第一封裝件安裝層414(如黏著劑層)安裝於該第一封裝件晶片墊410上。該第一封裝件積體電路408可隨著第一封裝件連接器416(如結合導線)電性連接至該第一封裝件引線412。The first encapsulant surface 406 can be formed on the first package integrated circuit 408, the first package wafer pad 410, and the first package leads 412. The first package integrated circuit 408 can be mounted on the first package wafer pad 410 along with a first package mounting layer 414, such as an adhesive layer. The first package integrated circuit 408 can be electrically connected to the first package lead 412 along with the first package connector 416 (eg, bonding wires).

該積體電路封裝件內封裝件系統400也較佳地包含第二積體電路418。該第二積體電路418可安裝於相鄰該第一積體電路封裝件402而不需要安裝層(如黏著劑)。晶片隱藏器(die concealer)420可應用於該第二積體電路418。該第二積體電路418可隨著第二連接器422(如結合導線)電性連接至該第一積體電路封裝件402。The integrated circuit package inner package system 400 also preferably includes a second integrated circuit 418. The second integrated circuit 418 can be mounted adjacent to the first integrated circuit package 402 without requiring a mounting layer (such as an adhesive). A die concealer 420 can be applied to the second integrated circuit 418. The second integrated circuit 418 can be electrically connected to the first integrated circuit package 402 along with the second connector 422 (eg, a bonding wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件402可較佳地固接於該積體電路封裝件內封裝件系統400而不需要黏著劑。該第一積體電路封裝件402以及該第二積體電路418可隨著封裝件內封裝件連接器426(如結合導線)電性連接至封裝件內封裝件引線424。該封裝件內封裝件引線424較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package attachment, the first integrated circuit package 402 can be preferably secured to the package circuit system 400 within the integrated circuit package without the need for an adhesive. The first integrated circuit package 402 and the second integrated circuit 418 can be electrically connected to the package inner package leads 424 along the package inner package connector 426 (eg, bonding wires). The package inner package leads 424 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統400較佳地包含封裝 件內封裝件封裝膠體428。該封裝件內封裝件封裝膠體428可提供結構上的完整與保護給該第一積體電路封裝件402、該第二積體電路418、該第二連接器422、該封裝件內封裝件連接器426、以及該封裝件內封裝件引線424之部分。該第一封裝膠體表面406以及相對該第二積體電路418之晶片隱藏器420的表面可與藉由封裝件內封裝件封裝膠體428之封裝件內封裝件安裝表面430以及封裝件內封裝件引線424之封裝件內封裝件引線表面432所形成之平面實質上共面。The integrated circuit package inner package system 400 preferably includes a package The in-piece package encapsulant 428. The package inner package encapsulant 428 can provide structural integrity and protection to the first integrated circuit package 402, the second integrated circuit 418, the second connector 422, and the package inner package. The 426, and portions of the package leads 424 within the package. The first encapsulant surface 406 and the surface of the wafer concealer 420 opposite the second integrator circuit 418 can be used with the package in-package mounting surface 430 and the in-package package by the in-package encapsulation encapsulant 428 The plane formed by the package lead surface 432 within the package of leads 424 is substantially coplanar.

現在參考第5圖，顯示本發明之第三實施例中積體電路封裝件內封裝件系統500之剖面圖。該積體電路封裝件內封裝件系統500較佳地包含具有第一封裝膠體504之第一積體電路封裝件502。該第一積體電路封裝件502之第一封裝膠體504可包含較佳地形成具有實質上平面表面之第一封裝膠體表面506。Referring now to Figure 5, there is shown a cross-sectional view of a package system 500 in an integrated circuit package in accordance with a third embodiment of the present invention. The integrated circuit package inner package system 500 preferably includes a first integrated circuit package 502 having a first encapsulant 504. The first encapsulant 504 of the first integrated circuit package 502 can include a first encapsulant surface 506 that preferably forms a substantially planar surface.

該第一封裝膠體表面506可形成於第一封裝件積體電路508、第一封裝件晶片墊510、以及第一封裝件引線512上。第一封裝件積體電路508可隨著第一封裝件安裝層514(如黏著劑層)安裝於該第一封裝件晶片墊510上。該第一封裝件積體電路508可隨著第一封裝件連接器516(如結合導線)電性連接至該第一封裝件引線512。The first encapsulant surface 506 can be formed on the first package integrated circuit 508, the first package wafer pad 510, and the first package leads 512. The first package integrated circuit 508 can be mounted on the first package wafer pad 510 along with a first package mounting layer 514, such as an adhesive layer. The first package integrated circuit 508 can be electrically connected to the first package lead 512 along with the first package connector 516 (eg, a bonding wire).

該積體電路封裝件內封裝件系統500也較佳地包含第二積體電路518。該第二積體電路518可安裝於相鄰該第一積體電路封裝件502而不需要安裝層(如黏著劑)。第二 積體電路安裝表面520可為實質上平面。該第二積體電路518可隨著第二連接器522(如結合導線)電性連接至該第一積體電路封裝件502。The integrated circuit package inner package system 500 also preferably includes a second integrated circuit 518. The second integrated circuit 518 can be mounted adjacent to the first integrated circuit package 502 without requiring a mounting layer (such as an adhesive). second The integrated circuit mounting surface 520 can be substantially planar. The second integrated circuit 518 can be electrically connected to the first integrated circuit package 502 along with the second connector 522 (eg, a bonding wire).

該積體電路封裝件內封裝件系統500也可包含於該第一積體電路封裝件502上之第三積體電路524以及於該第二積體電路518上之第四積體電路526。該第三積體電路524可隨著第三安裝層528來安裝以及該第四積體電路526可隨著第四安裝層530來安裝。第三連接器532可連接該第三積體電路524以及該第一積體電路封裝件502。第四連接器534可電性連接該第四積體電路526以及該第二積體電路518。The integrated circuit package package system 500 can also include a third integrated circuit 524 on the first integrated circuit package 502 and a fourth integrated circuit 526 on the second integrated circuit 518. The third integrated circuit 524 can be mounted with the third mounting layer 528 and the fourth integrated circuit 526 can be mounted with the fourth mounting layer 530. The third connector 532 can connect the third integrated circuit 524 and the first integrated circuit package 502. The fourth connector 534 is electrically connected to the fourth integrated circuit 526 and the second integrated circuit 518.

對於無黏性封裝件固接來說，該第一積體電路封裝件502可較佳地固接於該積體電路封裝件內封裝件系統500而不需要黏著劑。該第一積體電路封裝件502以及該第二積體電路518可隨著封裝件內封裝件連接器538(如結合導線)電性連接至封裝件內封裝件引線536。該封裝件內封裝件引線536較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package attachment, the first integrated circuit package 502 can be preferably secured to the package circuit package system 500 without the need for an adhesive. The first integrated circuit package 502 and the second integrated circuit 518 can be electrically connected to the package inner package leads 536 along the package inner package connector 538 (eg, bonding wires). The package inner package leads 536 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統500較佳地包含封裝件內封裝件封裝膠體540。該封裝件內封裝件封裝膠體540可提供結構上的完整與保護給該第一積體電路封裝件502、該第二積體電路518、該第二連接器522、該封裝件內封裝件連接器538、以及該封裝件內封裝件引線536之部分。該第一封裝膠體表面506以及該第二積體電路安裝 表面520可與藉由封裝件內封裝件封裝膠體540之封裝件內封裝件安裝表面542以及封裝件內封裝件引線536之封裝件內封裝件引線表面544所形成之平面實質上共面。The integrated circuit package inner package system 500 preferably includes an in-package package encapsulant 540. The package inner package encapsulant 540 can provide structural integrity and protection to the first integrated circuit package 502, the second integrated circuit 518, the second connector 522, and the package in the package. The device 538, and portions of the package leads 536 within the package. The first encapsulant surface 506 and the second integrated circuit are mounted The surface 520 can be substantially coplanar with the plane formed by the package inner package mounting surface 542 and the package inner package lead surface 544 of the package inner package leader 536 within the package inner package encapsulant 540.

現在參考第6圖，顯示本發明之第四實施例中積體電路封裝件內封裝件系統600之剖面圖。類似於該積體電路封裝件內封裝件系統500，該積體電路封裝件內封裝件系統600較佳地包含具有第一封裝膠體604之第一積體電路封裝件602。該第一積體電路封裝件602之第一封裝膠體604可包含較佳地形成具有實質上平面表面之第一封裝膠體表面606。Referring now to Fig. 6, there is shown a cross-sectional view of a package system 600 in an integrated circuit package in a fourth embodiment of the present invention. Similar to the integrated circuit package inner package system 500, the integrated circuit package inner package system 600 preferably includes a first integrated circuit package 602 having a first encapsulant 604. The first encapsulant 604 of the first integrated circuit package 602 can include a first encapsulant surface 606 that preferably forms a substantially planar surface.

該第一封裝膠體表面606可形成於第一封裝件積體電路608、第一封裝件晶片墊610、以及第一封裝件引線612上。第一封裝件積體電路608可隨著第一封裝件安裝層614(如黏著劑層)安裝於該第一封裝件晶片墊610上。該第一封裝件積體電路608可隨著第一封裝件連接器616(如結合導線)電性連接至該第一封裝件引線612。The first encapsulant surface 606 can be formed on the first package integrated circuit 608, the first package wafer pad 610, and the first package leads 612. The first package integrated circuit 608 can be mounted on the first package wafer pad 610 with a first package mounting layer 614, such as an adhesive layer. The first package integrated circuit 608 can be electrically connected to the first package lead 612 along with the first package connector 616 (eg, a bonding wire).

該積體電路封裝件內封裝件系統600也較佳地包含第二積體電路618。該第二積體電路618可安裝於相鄰該第一積體電路封裝件602而不需要安裝層(如黏著劑)。晶片隱藏器620可應用於該第二積體電路618。該第二積體電路618可隨著第二連接器622(如結合導線)電性連接至該第一積體電路封裝件602。The integrated circuit package inner package system 600 also preferably includes a second integrated circuit 618. The second integrated circuit 618 can be mounted adjacent to the first integrated circuit package 602 without requiring a mounting layer (such as an adhesive). The wafer concealer 620 can be applied to the second integrated circuit 618. The second integrated circuit 618 can be electrically connected to the first integrated circuit package 602 along with the second connector 622 (eg, a bonding wire).

該積體電路封裝件內封裝件系統600也可包含於該第一積體電路封裝件602上之第三積體電路624以及於該第 二積體電路618上之第四積體電路626。該第三積體電路624可隨著第三安裝層628來安裝以及該第四積體電路626可隨著第四安裝層630來安裝。第三連接器632可連接該第三積體電路624以及該第一積體電路封裝件602。第四連接器634可電性連接該第四積體電路626以及該第二積體電路618。The integrated circuit package package system 600 can also be included in the third integrated circuit 624 on the first integrated circuit package 602 and The fourth integrated circuit 626 on the second integrated circuit 618. The third integrated circuit 624 can be mounted with the third mounting layer 628 and the fourth integrated circuit 626 can be mounted with the fourth mounting layer 630. The third connector 632 can connect the third integrated circuit 624 and the first integrated circuit package 602. The fourth connector 634 is electrically connected to the fourth integrated circuit 626 and the second integrated circuit 618.

對於無黏性封裝件固接來說，該第一積體電路封裝件602可較佳地固接於該積體電路封裝件內封裝件系統600而不需要黏著劑。該第一積體電路封裝件602以及該第二積體電路618可隨著封裝件內封裝件連接器638(如結合導線)電性連接至封裝件內封裝件引線636。該封裝件內封裝件引線636較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package attachment, the first integrated circuit package 602 can be preferably secured to the package circuit assembly 600 within the integrated circuit package without the need for an adhesive. The first integrated circuit package 602 and the second integrated circuit 618 can be electrically connected to the package inner package leads 636 along the package inner package connector 638 (eg, bonding wires). The package inner package leads 636 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統600較佳地包含封裝件內封裝件封裝膠體640。該封裝件內封裝件封裝膠體640可提供結構上的完整與保護給該第一積體電路封裝件602、該第二積體電路618、該第二連接器622、該封裝件內封裝件連接器638、以及該封裝件內封裝件引線636之部分。該第一封裝膠體表面606以及相對該第二積體電路618之晶片隱藏器620的表面可與藉由封裝件內封裝件封裝膠體640之封裝件內封裝件安裝表面642以及封裝件內封裝件引線636之封裝件內封裝件引線表面644所形成之平面實質上共面。The integrated circuit package inner package system 600 preferably includes an in-package package encapsulation colloid 640. The package inner package encapsulant 640 can provide structural integrity and protection to the first integrated circuit package 602, the second integrated circuit 618, the second connector 622, and the package in the package. The device 638, and portions of the package leads 636 within the package. The first encapsulant surface 606 and the surface of the wafer concealer 620 opposite the second integrator circuit 618 can be used with the package in-package mounting surface 642 and the in-package package by the in-package encapsulation encapsulant 640 The plane formed by the package lead surface 644 within the package of lead 636 is substantially coplanar.

現在參考第7圖，顯示本發明之第五實施例中積體電 路封裝件內封裝件系統700之剖面圖。類似於該積體電路封裝件內封裝件系統100，該積體電路封裝件內封裝件系統700較佳地包含具有第一封裝膠體704之第一積體電路封裝件702。該第一積體電路封裝件702之第一封裝膠體704可包含較佳地形成具有實質上平面表面之第一封裝膠體表面706。Referring now to Figure 7, there is shown an integrated body in a fifth embodiment of the present invention. A cross-sectional view of the package system 700 within the package. Similar to the integrated circuit package inner package system 100, the integrated circuit package inner package system 700 preferably includes a first integrated circuit package 702 having a first encapsulant 704. The first encapsulant 704 of the first integrated circuit package 702 can include a first encapsulant surface 706 that preferably forms a substantially planar surface.

該第一封裝膠體表面706可形成於第一封裝件積體電路708、第一封裝件晶片墊710、以及第一封裝件引線712上。第一封裝件積體電路708可隨著第一封裝件安裝層714(如黏著劑層)安裝於該第一封裝件晶片墊710上。該第一封裝件積體電路708可隨著第一封裝件連接器716(如結合導線)電性連接至該第一封裝件引線712。The first encapsulant surface 706 can be formed on the first package integrated circuit 708, the first package wafer pad 710, and the first package leads 712. The first package integrated circuit 708 can be mounted on the first package wafer pad 710 along with a first package mounting layer 714 (eg, an adhesive layer). The first package integrated circuit 708 can be electrically connected to the first package lead 712 along with the first package connector 716 (eg, a bonding wire).

該積體電路封裝件內封裝件系統700也較佳地包含第二積體電路718。該第二積體電路718可隨著第二安裝層720(如黏著劑)安裝於該第一積體電路封裝件702上。該第二積體電路718可隨著第二連接器722(如結合導線)電性連接至該第一積體電路封裝件702。The integrated circuit package inner package system 700 also preferably includes a second integrated circuit 718. The second integrated circuit 718 can be mounted on the first integrated circuit package 702 along with a second mounting layer 720 (eg, an adhesive). The second integrated circuit 718 can be electrically connected to the first integrated circuit package 702 along with the second connector 722 (eg, a bonding wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件702可較佳地固接於該積體電路封裝件內封裝件系統700而不需要黏著劑。該第一積體電路封裝件702以及因此該第二積體電路718可隨著封裝件內封裝件連接器726(如焊凸塊(solder bump)或焊球)電性連接至封裝件內封裝件引線724。該封裝件內封裝件引線724較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package fixing, the first integrated circuit package 702 can be preferably fixed to the package circuit system 700 in the integrated circuit package without an adhesive. The first integrated circuit package 702 and thus the second integrated circuit 718 can be electrically connected to the package inner package with the package inner package connector 726 (such as solder bump or solder ball) Piece lead 724. The package inner package leads 724 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統700較佳地包含封裝件內封裝件封裝膠體728。該封裝件內封裝件封裝膠體728可提供結構上的完整與保護給該第一積體電路封裝件702、該第二積體電路718、該第二連接器722、該封裝件內封裝件連接器726、以及該封裝件內封裝件引線724之部分。該第一封裝膠體表面706可與藉由封裝件內封裝件封裝膠體728之封裝件內封裝件安裝表面730以及封裝件內封裝件引線724之封裝件內封裝件引線表面732所形成之平面實質上共面。The integrated circuit package inner package system 700 preferably includes an in-package package encapsulant 728. The package inner package encapsulant 728 can provide structural integrity and protection to the first integrated circuit package 702, the second integrated circuit 718, the second connector 722, and the package inner package. The device 726, and portions of the package leads 724 within the package. The first encapsulant surface 706 can be planar with the encapsulation mounting surface 730 of the package by the encapsulation encapsulant 728 of the package and the encapsulation lead surface 732 of the package within the package. On the surface.

現在參考第8圖，顯示本發明之第六實施例中積體電路封裝件內封裝件系統800之剖面圖。該積體電路封裝件內封裝件系統800較佳地包含具有封裝件封裝膠體804之積體電路封裝件802。該積體電路封裝件802之封裝件封裝膠體804可包含較佳地形成具有實質上平面表面之封裝件封裝膠體表面806。Referring now to Fig. 8, there is shown a cross-sectional view of a package system 800 in an integrated circuit package of a sixth embodiment of the present invention. The integrated circuit package inner package system 800 preferably includes an integrated circuit package 802 having a package encapsulant 804. The package encapsulant 804 of the integrated circuit package 802 can include a package encapsulation surface 806 that preferably forms a substantially planar surface.

該封裝件封裝膠體表面806可形成於封裝件積體電路808、封裝件晶片墊810、以及封裝件引線812上。封裝件積體電路808可隨著封裝件安裝層814(如黏著劑層)安裝於該封裝件晶片墊810上。該封裝件積體電路808可隨著封裝件連接器816(如結合導線)電性連接至該封裝件引線812。The package encapsulation surface 806 can be formed on the package integrated circuit 808, the package wafer pad 810, and the package leads 812. The package integrator circuit 808 can be mounted on the package wafer pad 810 with a package mounting layer 814, such as an adhesive layer. The package integrated circuit 808 can be electrically coupled to the package lead 812 along with the package connector 816 (eg, bonding wires).

互連線818(如結合導線)可連接兩個或更多個積體電路封裝件802。該互連線818可提供於兩個或更多個積體電路封裝件802間的電性連接或經由一個或多個積體電路 封裝件802的電性連接。Interconnect lines 818 (eg, bonding wires) may connect two or more integrated circuit packages 802. The interconnect 818 can be provided for electrical connection between two or more integrated circuit packages 802 or via one or more integrated circuits The electrical connection of the package 802.

對於無黏性封裝件固接來說，該積體電路封裝件802可較佳地固接於該積體電路封裝件內封裝件系統800而不需要黏著劑。該積體電路封裝件802可隨著封裝件內封裝件連接器822(如結合導線)電性地連接至封裝件內封裝件引線820。該封裝件內封裝件引線820較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For non-adhesive package attachment, the integrated circuit package 802 can be preferably secured to the package circuit system 800 within the integrated circuit package without the need for an adhesive. The integrated circuit package 802 can be electrically coupled to the package inner package leads 820 with the package inner package connector 822 (eg, bonding wires). The package inner package leads 820 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統800較佳地包含封裝件內封裝件封裝膠體824。該封裝件內封裝件封裝膠體824可提供結構上的完整與保護給該積體電路封裝件802、該互連線818、該封裝件內封裝件連接器822、以及該封裝件內封裝件引線820之部分。該封裝件封裝膠體表面806可與藉由封裝件內封裝件封裝膠體824之封裝件內封裝件安裝表面826以及封裝件內封裝件引線820之封裝件內封裝件引線表面828所形成之平面實質上共面。The integrated circuit package inner package system 800 preferably includes an in-package package encapsulant 824. The package inner package encapsulant 824 can provide structural integrity and protection to the integrated circuit package 802, the interconnect 818, the package inner package connector 822, and the package lead within the package. Part of 820. The package encapsulation surface 806 can be planar with the encapsulation mounting surface 826 of the package encapsulation colloid 824 within the package and the package lead surface 828 of the package within the package. On the surface.

雖然了解到可使用任何數量的積體電路封裝件802，但為了描述的目的，該積體電路封裝件內封裝件顯示具有兩個積體電路封裝件802。Although it is understood that any number of integrated circuit packages 802 can be used, the package within the integrated circuit package is shown to have two integrated circuit packages 802 for purposes of description.

現在參考第9圖，顯示本發明之第七實施例中積體電路封裝件內封裝件系統900之剖面圖。類似於該積體電路封裝件內封裝件系統800，該積體電路封裝件內封裝件系統900較佳地包含具有封裝件封裝膠體904之積體電路封裝件902。該積體電路封裝件902之封裝件封裝膠體904可包含較佳地形成具有實質上平面表面之封裝件封裝膠體 表面906。Referring now to Fig. 9, there is shown a cross-sectional view of a package system 900 in an integrated circuit package in a seventh embodiment of the present invention. Similar to the integrated circuit package inner package system 800, the integrated circuit package inner package system 900 preferably includes an integrated circuit package 902 having a package encapsulant 904. The package encapsulant 904 of the integrated circuit package 902 can comprise a package encapsulant that preferably forms a substantially planar surface Surface 906.

該封裝件封裝膠體表面906可形成於封裝件積體電路908以及封裝件引線912上。對於無黏性封裝件固接來說，封裝件積體電路908可安裝鄰近於該封裝件引線912而不需黏著劑。該封裝件積體電路908可隨著封裝件連接器916(如結合導線)電性地連接至該封裝件引線912。The package encapsulation surface 906 can be formed on the package integrated circuit 908 and the package leads 912. For non-adhesive package attachment, package integrated circuit 908 can be mounted adjacent to package lead 912 without the need for an adhesive. The package integrated circuit 908 can be electrically connected to the package lead 912 along with the package connector 916 (eg, bonding wires).

互連線918(如結合導線)可連接兩個或更多個積體電路封裝件902。該互連線918可提供於兩個或更多個積體電路封裝件902間的電性連接或經由一個或多個積體電路封裝件902的電性連接。Interconnect lines 918 (eg, bonding wires) may connect two or more integrated circuit packages 902. The interconnect 918 can be provided for electrical connection between two or more integrated circuit packages 902 or for electrical connection via one or more integrated circuit packages 902.

對於無黏性封裝件固接來說，該積體電路封裝件902可較佳地固接於該積體電路封裝件內封裝件系統900而不需要黏著劑。該積體電路封裝件902可隨著封裝件內封裝件連接器922(如結合導線)電性地連接至封裝件內封裝件引線920。該封裝件內封裝件引線920較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package attachment, the integrated circuit package 902 can be preferably secured to the package circuit system 900 within the integrated circuit package without the need for an adhesive. The integrated circuit package 902 can be electrically coupled to the package inner package leads 920 with the package inner package connector 922 (eg, bonding wires). The package inner package leads 920 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統900較佳地包含封裝件內封裝件封裝膠體924。該封裝件內封裝件封裝膠體924可提供結構上的完整與保護給該積體電路封裝件902、該互連線918、該封裝件內封裝件連接器922、以及該封裝件內封裝件引線920之部分。該封裝件封裝膠體表面906可與藉由封裝件內封裝件封裝膠體924之封裝件內封裝件安裝表面926以及封裝件內封裝件引線920之封裝件內封裝件引線表面928所形成之平面實質上共面。The integrated circuit package inner package system 900 preferably includes an in-package package encapsulant 924. The package inner package encapsulant 924 can provide structural integrity and protection to the integrated circuit package 902, the interconnect 918, the package inner package connector 922, and the package lead within the package. Part of 920. The package encapsulation surface 906 can be planar with the encapsulation mounting surface 926 of the encapsulation within the package encapsulation colloid 924 and the package lead surface 928 within the encapsulation lead 920 of the package. On the surface.

雖然了解到可使用任何數量的積體電路封裝件902，但為了描述的目的，該積體電路封裝件內封裝件顯示具有兩個積體電路封裝件902。Although it is understood that any number of integrated circuit packages 902 can be used, the package within the integrated circuit package is shown to have two integrated circuit packages 902 for purposes of description.

現在參考第10圖，顯示於覆蓋(coverlay)應用面中之積體電路封裝件內封裝件系統800之剖面圖。覆蓋層1002(如覆蓋帶)實施於該封裝件內封裝件引線820之兩個或更多個封裝件內封裝件引線表面828上。該覆蓋層1002提供與藉由兩個或更多個封裝件內封裝件引線表面828形成的表面實質上平面之覆蓋安裝表面1004。Referring now to Figure 10, there is shown a cross-sectional view of a package system 800 in an integrated circuit package in a coverlay application surface. A cover layer 1002, such as a cover tape, is implemented on the package lead surface 828 within two or more packages of the package leads 820 within the package. The cover layer 1002 provides a substantially planar coverage of the mounting surface 1004 with a surface formed by the package lead surface 828 in two or more packages.

現在參考第11圖，顯示於無黏性封裝件固接面中之積體電路封裝件內封裝件系統800之剖面圖。兩個積體電路封裝件802安裝於該覆蓋層1002之覆蓋安裝表面1004上。該積體電路封裝件802之封裝件封裝膠體表面806與藉由該封裝件內封裝件引線820之兩個或更多個封裝件內封裝件引線表面828形成的表面實質上平面。Referring now to Figure 11, a cross-sectional view of package system 800 in an integrated circuit package shown in a non-adhesive package attachment surface is shown. Two integrated circuit packages 802 are mounted on the cover mounting surface 1004 of the cover layer 1002. The package encapsulation surface 806 of the integrated circuit package 802 is substantially planar with the surface formed by the package lead surface 828 in the package or two of the package leads 820.

現在參考第12圖，顯示於電性連接面中之積體電路封裝件內封裝件系統800之剖面圖。該互連線818可將該積體電路封裝件802電性地連接至另一積體電路封裝件802。該封裝件內封裝件822可較佳地將一個或多個積體電路封裝件802連接至該覆蓋層1002上之封裝件內封裝件引線820。Referring now to Figure 12, there is shown a cross-sectional view of a package system 800 in an integrated circuit package in an electrical connection surface. The interconnect 818 can electrically connect the integrated circuit package 802 to another integrated circuit package 802. The package inner package 822 can preferably connect one or more integrated circuit packages 802 to the package inner package leads 820 on the cover layer 1002.

現在參考第13圖，顯示於封裝件內封裝件封裝膠體面中之積體電路封裝件內封裝件系統800之剖面圖。該封裝件內封裝件封裝膠體824可較佳地實施於該積體電路封裝 件802、該互連線818、以及該封裝件內封裝件引線820上作為蓋子及用於保護。該封裝件內封裝件封裝膠體824可實施於該封裝件內封裝件引線820之部分以及該覆蓋層1002之覆蓋安裝表面1004上。Referring now to Figure 13, a cross-sectional view of the package system 800 in an integrated circuit package in a package encapsulation face within a package is shown. The package inner package encapsulant 824 can be preferably implemented in the integrated circuit package The member 802, the interconnect 818, and the package lead 820 within the package serve as a cover and for protection. The package inner package encapsulant 824 can be implemented on portions of the package leads 820 within the package and over the cover mounting surface 1004 of the cover layer 1002.

現在參考第14圖，顯示於覆蓋移除面中之積體電路封裝件內封裝件系統800之剖面圖。該覆蓋層1002可從該積體電路封裝件802、該封裝件內封裝件引線820、以及該封裝件內封裝件封裝膠體824移除。該積體電路封裝件802之封裝件封裝膠體表面806、該封裝件內封裝件引線820之封裝件內封裝件引線表面828、以及該封裝件內封裝件封裝膠體824之封裝件內封裝件安裝表面826形成積體電路封裝件內封裝件系統800的實質上平面之表面。行尾(End of line, EOL)製程可實施於該積體電路封裝件內封裝件系統800。Referring now to Figure 14, a cross-sectional view of package system 800 is shown in an integrated circuit package that covers the removal surface. The cover layer 1002 can be removed from the integrated circuit package 802, the package inner package leads 820, and the package inner package encapsulant 824. The package encapsulation surface 806 of the integrated circuit package 802, the package inner package lead surface 828 of the package inner package lead 820, and the package inner package mounting of the package inner package encapsulant 824 Surface 826 forms a substantially planar surface of package system 800 within the integrated circuit package. An End of Line (EOL) process can be implemented in the package circuit system 800 within the integrated circuit package.

現在參考第15圖，顯示本發明之第八實施例中積體電路封裝件內封裝件系統1500之剖面圖。該積體電路封裝件內封裝件系統1500較佳地包含具有第一封裝膠體1504之第一積體電路封裝件1502。該第一積體電路封裝件1502之第一封裝膠體1504可包含較佳地形成具有實質上平面表面之第一封裝膠體表面1506。Referring now to Fig. 15, there is shown a cross-sectional view of a package system 1500 in an integrated circuit package in an eighth embodiment of the present invention. The integrated circuit package inner package system 1500 preferably includes a first integrated circuit package 1502 having a first encapsulant 1504. The first encapsulant 1504 of the first integrated circuit package 1502 can comprise a first encapsulant surface 1506 that preferably forms a substantially planar surface.

該第一封裝膠體表面1506可形成於第一封裝件積體電路1508、第一封裝件晶片墊1510、以及第一封裝件引線1512上。第一封裝件積體電路1508可隨著第一封裝件安裝層1514(如黏著劑層)安裝於該第一封裝件晶片墊1510 上。該第一封裝件積體電路1508可隨著第一封裝件連接器1516(如結合導線)電性連接至該第一封裝件引線1512。The first encapsulant surface 1506 can be formed on the first package integrated circuit 1508, the first package wafer pad 1510, and the first package leads 1512. The first package integrated circuit 1508 can be mounted to the first package wafer pad 1510 along with the first package mounting layer 1514 (eg, an adhesive layer) on. The first package integrated circuit 1508 can be electrically connected to the first package lead 1512 along with the first package connector 1516 (eg, bonding wires).

該積體電路封裝件內封裝件系統1500也較佳地包含第二積體電路1518。該第二積體電路1518可安裝鄰近於該第一積體電路封裝件1502而不需安裝層(如黏著劑)。晶片隱藏器1520可實施於該第二積體電路1518。該第二積體電路1518可隨著第二連接器1522(如結合導線)電性地連接至該第一積體電路封裝件1502。The integrated circuit package inner package system 1500 also preferably includes a second integrated circuit 1518. The second integrated circuit 1518 can be mounted adjacent to the first integrated circuit package 1502 without mounting a layer (such as an adhesive). The wafer concealer 1520 can be implemented in the second integrated circuit 1518. The second integrated circuit 1518 can be electrically connected to the first integrated circuit package 1502 along with the second connector 1522 (eg, a bonding wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件1502可較佳地固接於該積體電路封裝件內封裝件系統1500而不需要黏著劑。該第一積體電路封裝件1502以及該第二積體電路1518可隨著封裝件內封裝件連接器1526(如結合導線)電性地連接至封裝件內封裝件引線724(如彎頭(J-bend))。該封裝件內封裝件引線1524較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package fixing, the first integrated circuit package 1502 can be preferably fixed to the package circuit system 1500 within the integrated circuit package without requiring an adhesive. The first integrated circuit package 1502 and the second integrated circuit 1518 can be electrically connected to the package inner package lead 724 (such as an elbow) along the package inner package connector 1526 (such as a bonding wire). J-bend)). The package inner package leads 1524 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統1500較佳地包含封裝件內封裝件封裝膠體1528。該封裝件內封裝件封裝膠體1528可提供結構上的完整與保護給該第一積體電路封裝件1502、該第二積體電路1518、該第二連接器1522、該封裝件內封裝件連接器1526、以及該封裝件內封裝件引線1524之部分。該第一封裝膠體表面1506以及相對於該第二積體電路1518之晶片隱藏器1520的表面可與藉由封裝件內封裝件封裝膠體1528之封裝件內封裝件較低表面1530以及 封裝件內封裝件引線1524之封裝件內封裝件引線表面1532所形成之平面實質上共面。The integrated circuit package inner package system 1500 preferably includes an in-package package encapsulant 1528. The package inner package encapsulant 1528 can provide structural integrity and protection to the first integrated circuit package 1502, the second integrated circuit 1518, the second connector 1522, and the package package. The device 1526, and portions of the package leads 1524 within the package. The first encapsulant surface 1506 and the surface of the wafer concealer 1520 relative to the second integrator circuit 1518 can be compared to the lower surface 1530 of the package in the package by the encapsulation within the package 1528 and The plane formed by the package lead surface 1532 within the package of the package lead 1524 within the package is substantially coplanar.

雖然了解到可使用任何數量的第一積體電路封裝件1502，但為了描述的目的，該積體電路封裝件內封裝件系統1500顯示具有一個第一積體電路封裝件1502。對於本技術領域中具有通常知識者將很明顯，該積體電路封裝件內封裝件系統1500之任何實施例可包含封裝件內封裝件引線1524(如彎頭)。Although it is understood that any number of first integrated circuit packages 1502 can be used, the integrated circuit package inner package system 1500 is shown with a first integrated circuit package 1502 for purposes of description. It will be apparent to those of ordinary skill in the art that any embodiment of the integrated circuit package inner package system 1500 can include package inner package leads 1524 (e.g., elbows).

現在參考第16圖，顯示本發明之第九實施例中積體電路封裝件內封裝件系統1600之剖面圖。該積體電路封裝件內封裝件系統1600較佳地包含具有第一封裝膠體1604之第一積體電路封裝件1602。該第一積體電路封裝件1602之第一封裝膠體1604可包含較佳地形成具有實質上平面表面之第一封裝膠體表面1606。Referring now to Fig. 16, there is shown a cross-sectional view of a package system 1600 for an integrated circuit package in a ninth embodiment of the present invention. The integrated circuit package inner package system 1600 preferably includes a first integrated circuit package 1602 having a first encapsulant 1604. The first encapsulant 1604 of the first integrated circuit package 1602 can comprise a first encapsulant surface 1606 that preferably forms a substantially planar surface.

該第一封裝膠體表面1606可形成於第一封裝件積體電路1608、第一封裝件晶片墊1610、以及第一封裝件引線1612上。第一封裝件積體電路1608可隨著第一封裝件安裝層1614(如黏著劑層)安裝於該第一封裝件晶片墊1610上。該第一封裝件積體電路1608可隨著第一封裝件連接器1616(如結合導線)電性連接至該第一封裝件引線1612。The first encapsulant surface 1606 can be formed on the first package integrated circuit 1608, the first package wafer pad 1610, and the first package leads 1612. The first package integrated circuit 1608 can be mounted on the first package wafer pad 1610 along with a first package mounting layer 1614 (eg, an adhesive layer). The first package integrated circuit 1608 can be electrically connected to the first package lead 1612 along with the first package connector 1616 (eg, bonding wires).

該積體電路封裝件內封裝件系統1600也較佳地包含第二積體電路1618。該第二積體電路1618可安裝鄰近於該第一積體電路封裝件1602而不需安裝層(如黏著劑)。晶片隱藏器1620可實施於該第二積體電路1618。該第二積 體電路1618可隨著第二連接器1622(如結合導線)電性地連接至該第一積體電路封裝件1602。The integrated circuit package inner package system 1600 also preferably includes a second integrated circuit 1618. The second integrated circuit 1618 can be mounted adjacent to the first integrated circuit package 1602 without mounting a layer (such as an adhesive). The wafer concealer 1620 can be implemented in the second integrated circuit 1618. The second product The body circuit 1618 can be electrically coupled to the first integrated circuit package 1602 along with the second connector 1622 (eg, in conjunction with a wire).

對於無黏性封裝件固接來說，該第一積體電路封裝件1602可較佳地固接於該積體電路封裝件內封裝件系統1600而不需要黏著劑。該第一積體電路封裝件1602以及該第二積體電路1618可隨著封裝件內封裝件連接器1626(如結合導線)電性地連接至封裝件內封裝件引線1624(如具有上端與下端之可堆疊引線)。該封裝件內封裝件引線1624較佳地提供連接點給下一層級的系統(如另一封裝件或印刷電路板)。For the non-adhesive package fixing, the first integrated circuit package 1602 can be preferably fixed to the package circuit system 1600 within the integrated circuit package without the need for an adhesive. The first integrated circuit package 1602 and the second integrated circuit 1618 can be electrically connected to the package inner package lead 1624 along with the package inner package connector 1626 (eg, bonding wires) (eg, having an upper end and Stackable leads at the bottom). The package inner package leads 1624 preferably provide a connection point to the next level of the system (such as another package or printed circuit board).

該積體電路封裝件內封裝件系統1600較佳地包含封裝件內封裝件封裝膠體1628。該封裝件內封裝件封裝膠體1628可提供結構上的完整與保護給該第一積體電路封裝件1602、該第二積體電路1618、該第二連接器1622、該封裝件內封裝件連接器1626、以及該封裝件內封裝件引線1624之部分。該第一封裝膠體表面1606以及相對於該第二積體電路1618之晶片隱藏器1620的表面可與藉由封裝件內封裝件封裝膠體1628之封裝件內封裝件安裝表面1630以及封裝件內封裝件引線1624之封裝件內封裝件引線表面1632所形成之平面實質上共面。The integrated circuit package inner package system 1600 preferably includes an in-package package encapsulation colloid 1628. The package inner package encapsulant 1628 can provide structural integrity and protection to the first integrated circuit package 1602, the second integrated circuit 1618, the second connector 1622, and the package package. The device 1626, and portions of the package leads 1624 within the package. The first encapsulant surface 1606 and the surface of the wafer concealer 1620 relative to the second integrator circuit 1618 can be mounted with the package in-package mounting surface 1630 and the in-package package by the in-package encapsulation package 1628. The plane formed by the package lead surface 1632 within the package of the lead 1624 is substantially coplanar.

雖然了解到可使用任何數量的第一積體電路封裝件1602，但為了描述的目的，該積體電路封裝件內封裝件系統1600顯示具有一個第一積體電路封裝件1602。對於本技術領域中具有通常知識者將很明顯，該積體電路封裝件 內封裝件系統1600之任何實施例可包含封裝件內封裝件引線1624(如具有上端與下端之可堆疊引線)。Although it is understood that any number of first integrated circuit packages 1602 can be used, the integrated circuit package inner package system 1600 is shown with a first integrated circuit package 1602 for purposes of description. It will be apparent to those of ordinary skill in the art that the integrated circuit package Any of the embodiments of the inner package system 1600 can include package inner package leads 1624 (eg, stackable leads having upper and lower ends).

現在參考第17圖，顯示本發明之實施例中用於製作積體電路封裝件內封裝件系統100之積體電路封裝件內封裝方法1700之流程圖。該方法1700包含於方塊1702中提供具有實質上平面的封裝件內封裝件引線表面之封裝件內封裝件引線；於方塊1704中固接與該封裝件內封裝件引線表面實質上共面之具有第一封裝膠體表面之第一積體電路封裝件；於方塊1706中固接鄰近該第一積體電路封裝件之第二積體電路封裝件；以及，於方塊1708中於第一積體電路封裝件與第二積體電路上方形成封裝件內封裝件封裝膠體。Referring now to Figure 17, a flow diagram of an integrated circuit package encapsulation method 1700 for fabricating a package system 100 in an integrated circuit package in accordance with an embodiment of the present invention is shown. The method 1700 includes, in block 1702, providing an in-package package lead having a substantially planar package inner lead surface; in block 1704, securing is substantially coplanar with the package inner lead surface of the package a first integrated circuit package of the first encapsulation surface; a second integrated circuit package adjacent to the first integrated circuit package is secured in block 1706; and, in block 1708, the first integrated circuit A package encapsulant colloid is formed over the package and the second integrated circuit.

更詳細說明，於本發明之實施例中，一種用以提供積體電路封裝件內封裝件系統100的方法與設備之系統係呈現如下：In more detail, in an embodiment of the present invention, a system for providing a method and apparatus for a package system 100 in an integrated circuit package is as follows:

1.形成具有與另一封裝件內封裝件引線呈實質上平面的封裝件內封裝件引線表面之封裝件內封裝件引線。1. Forming an in-package package lead having a package lead surface in a package that is substantially planar with the package leads within another package.

2.安裝具有與該封裝件內封裝件引線表面以及另一封裝件內封裝件引線表面實質上共面之第一封裝膠體表面的第一積體電路封裝件。2. Mounting a first integrated circuit package having a first encapsulant surface that is substantially coplanar with the package lead surface within the package and the package lead surface within the other package.

3.隨著第二連接器將第二積體電路連接至該第一積體電路封裝件。3. Connect the second integrated circuit to the first integrated circuit package as the second connector.

4.將封裝件內封裝件封裝膠體實施於該第一積體電路封裝件與該第二積體電路上，該封裝件內封裝件封裝膠體 具有與該第一封裝膠體表面以及該封裝件內封裝件引線表面實質上共面之封裝件內封裝件安裝表面的平面。4. The package inner package encapsulant is implemented on the first integrated circuit package and the second integrated circuit, and the package encapsulant colloid A plane having a package mounting surface within the package that is substantially coplanar with the first encapsulant surface and the package lead surface within the package.

因此，已發現本發明之積體電路封裝件系統方法與設備提供重要的與迄今為止不了解且無法獲得的解決方案、能力與功能性態樣。所產生的製程與配置係簡單明確的、具成本效益的、不複雜的、高性能、準確、敏感以及有效率，且能藉由採用習知元件來實施用於預備好、有效率與經濟之製造、應用與利用。Accordingly, it has been discovered that the integrated circuit package system method and apparatus of the present invention provides important, yet unrecognized, and unobtainable solutions, capabilities, and functional aspects. The resulting processes and configurations are simple, cost-effective, uncomplicated, high-performance, accurate, sensitive, and efficient, and can be implemented, prepared, efficient, and economical by using conventional components. Manufacturing, application and utilization.

雖然本發明係以特定的最佳模式而描述，但應了解到鑑於前述說明，對於熟悉此項技藝的人士而言眾多替代的、修改的及各種變化將是顯而易見的。據此，本發明係傾向包含所有落在申請專利範圍之範疇內的這類替代的、修改的及各種變化。在此提出或顯示於附圖中的所有事項係為示範之說明而非用於限制。Although the present invention has been described in terms of a particular preferred embodiment, it is understood that many modifications, modifications and Accordingly, the present invention is intended to embrace such alternatives, modifications and All matters presented or shown in the drawings are for purposes of illustration and not limitation.

100、300、400、500、600、700、800、900、1500、1600‧‧‧積體電路封裝件內封裝件系統100, 300, 400, 500, 600, 700, 800, 900, 1500, 1600‧ ‧ ‧ integrated circuit package package system

102、302、402、502、602、702、1502、1602‧‧‧第一積體電路封裝件102, 302, 402, 502, 602, 702, 1502, 1602‧‧‧ first integrated circuit package

104、304、404、504、604、704、1504、1604‧‧‧第一封裝膠體104, 304, 404, 504, 604, 704, 1504, 1604‧‧‧ first encapsulant

106、306、406、506、606、706、1506、1606‧‧‧第一封裝膠體表面106, 306, 406, 506, 606, 706, 1506, 1606‧‧‧ first encapsulant surface

108、308、408、508、608、708、1508、1608‧‧‧第一封裝件積體電路108, 308, 408, 508, 608, 708, 1508, 1608‧‧‧ first package integrated circuit

110、310、410、510、610、710、1510、1610‧‧‧第一封裝件晶片墊110, 310, 410, 510, 610, 710, 1510, 1610‧‧‧ first package wafer pad

112、312、412、512、612、712、1512、1612‧‧‧第一封裝件引線112, 312, 412, 512, 612, 712, 1512, 1612‧‧‧ first package leads

114、314、414、514、614、714、1514、1614‧‧‧第一封裝件安裝層114, 314, 414, 514, 614, 714, 1514, 1614‧‧‧ first package mounting layer

116、316、416、516、616、716、1516、1616‧‧‧第一封裝件連接器116, 316, 416, 516, 616, 716, 1516, 1616‧‧‧ first package connector

118、318、418、518、618、718、1518、1618‧‧‧第二積體電路118, 318, 418, 518, 618, 718, 1518, 1618‧‧‧ second integrated circuit

120、320、520、720‧‧‧第二安裝層120, 320, 520, 720‧‧‧ second installation layer

122、322、422、522、622、722、1522、1622‧‧‧第二連接器122, 322, 422, 522, 622, 722, 1522, 1622‧‧‧ second connector

124、324、424、536、636、724、820、920、1524、1624‧‧‧封裝件內封裝件引線124, 324, 424, 536, 636, 724, 820, 920, 1524, 1624‧ ‧ ‧ package leads

126、326、426、538、638、726、822、922、1526、1626‧‧‧ 封裝件內封裝件連接器126, 326, 426, 538, 638, 726, 822, 922, 1526, 1626‧‧ Package inner package connector

128、328、428、540、640、728、824、924、1528、1628‧‧‧封裝件內封裝件封裝膠體128, 328, 428, 540, 640, 728, 824, 924, 1528, 1628‧‧‧ Package encapsulation colloid

130、330、430、542、642、730、826、926‧‧‧封裝件內封裝件安裝表面130, 330, 430, 542, 642, 730, 826, 926 ‧ ‧ ‧ package mounting surface

132、332、432、544、644、732、828、928、1532、1632‧‧‧封裝件內封裝件引線表面132, 332, 432, 544, 644, 732, 828, 928, 1532, 1632‧ ‧ ‧ package lead surface

202‧‧‧暴露部分202‧‧‧Exposed part

420、620、1520、1620‧‧‧晶片隱藏器420, 620, 1520, 1620‧‧‧ wafer hidden devices

524、624‧‧‧第三積體電路524, 624‧‧‧ third integrated circuit

526、626‧‧‧第四積體電路526, 626‧‧‧ fourth integrated circuit

528、628‧‧‧第三安裝層528, 628‧‧‧ third installation layer

530、630‧‧‧第四安裝層530, 630‧‧‧ fourth installation layer

532、632‧‧‧第三連接器532, 632‧‧‧ third connector

534、634‧‧‧第四連接器534, 634‧‧ Fourth connector

802、902‧‧‧積體電路封裝件802, 902‧‧‧ integrated circuit package

804、904‧‧‧封裝件封裝膠體804, 904‧‧‧Package encapsulant

806、906‧‧‧封裝件封裝膠體表面806, 906‧‧‧Package encapsulation colloidal surface

808、908‧‧‧封裝件積體電路808, 908‧‧‧Package integrated circuit

810‧‧‧封裝件晶片墊810‧‧‧Package wafer pad

812、912‧‧‧封裝件引線812, 912‧‧‧Package leads

814‧‧‧封裝件安裝層814‧‧‧Package mounting layer

816、916‧‧‧封裝件連接器816, 916‧‧‧Package connector

818、918‧‧‧互連線818, 918‧‧‧ interconnection lines

1002‧‧‧覆蓋層1002‧‧‧ Coverage

1004‧‧‧覆蓋安裝表面1004‧‧‧covering the mounting surface

1530、1630‧‧‧封裝件內封裝件較低表面1530, 1630‧‧‧The lower surface of the package

1700‧‧‧積體電路封裝件內封裝方法1700‧‧‧Integrated circuit package encapsulation method

1702、1704、1706、1708‧‧‧流程方塊1702, 1704, 1706, 1708‧‧‧ flow blocks

第1圖是本發明之實施例中沿著第2圖的線1-1之積體電路封裝件內封裝件系統之剖面圖；第2圖是積體電路封裝件內封裝件系統之上平面視圖；第3圖是本發明之第一實施例中積體電路封裝件內封裝件系統之剖面圖；第4圖是本發明之第二實施例中積體電路封裝件內封裝件系統之剖面圖；第5圖是本發明之第三實施例中積體電路封裝件內封裝件系統之剖面圖； 第6圖是本發明之第四實施例中積體電路封裝件內封裝件系統之剖面圖；第7圖是本發明之第五實施例中積體電路封裝件內封裝件系統之剖面圖；第8圖是本發明之第六實施例中積體電路封裝件內封裝件系統之剖面圖；第9圖是本發明之第七實施例中積體電路封裝件內封裝件系統之剖面圖；第10圖是於覆蓋應用面中之積體電路封裝件內封裝件系統之剖面圖；第11圖是於無黏性封裝件固接面中之積體電路封裝件內封裝件系統之剖面圖；第12圖是於電性連接面中之積體電路封裝件內封裝件系統之剖面圖；第13圖是於封裝件內封裝件封裝膠體面中之積體電路封裝件內封裝件系統之剖面圖；第14圖是於覆蓋移除面中之積體電路封裝件內封裝件系統之剖面圖；第15圖是本發明之第八實施例中積體電路封裝件內封裝件系統之剖面圖；第16圖是本發明之第九實施例中積體電路封裝件內封裝件系統之剖面圖；以及第17圖是本發明之實施例中用於製作積體電路封裝件內封裝件系統之積體電路封裝件內封裝方法之流程圖。1 is a cross-sectional view of the package system of the integrated circuit package along the line 1-1 of FIG. 2 in the embodiment of the present invention; and FIG. 2 is a plan view of the package system in the integrated circuit package. 3 is a cross-sectional view of a package system in an integrated circuit package according to a first embodiment of the present invention; and FIG. 4 is a cross-sectional view of a package system in an integrated circuit package according to a second embodiment of the present invention; Figure 5 is a cross-sectional view showing the package system of the integrated circuit package in the third embodiment of the present invention; 6 is a cross-sectional view showing a package system of an integrated circuit package in a fourth embodiment of the present invention; and FIG. 7 is a cross-sectional view showing a package system in an integrated circuit package according to a fifth embodiment of the present invention; Figure 8 is a cross-sectional view showing a package system of an integrated circuit package in a sixth embodiment of the present invention; and Figure 9 is a cross-sectional view showing a package system in an integrated circuit package according to a seventh embodiment of the present invention; Figure 10 is a cross-sectional view of the package system in the integrated circuit package covering the application surface; Figure 11 is a cross-sectional view of the package system in the integrated circuit package in the non-adhesive package fixing surface Figure 12 is a cross-sectional view of the package system in the integrated circuit package in the electrical connection surface; Figure 13 is the package system in the integrated circuit package in the package encapsulation surface of the package FIG. 14 is a cross-sectional view of the package system in the integrated circuit package covering the removal surface; FIG. 15 is a cross-sectional view of the package system in the integrated circuit package in the eighth embodiment of the present invention; Figure 16 is a diagram showing the body of the ninth embodiment of the present invention. Sectional view of an inner package of the package system; and FIG. 17 is a flowchart of the integrated circuit package produced within the integrated circuit package of the package system of the embodiment of the packaging method of the present invention is used.

100‧‧‧積體電路封裝件內封裝件系統100‧‧‧Integrated circuit package package system

102‧‧‧第一積體電路封裝件102‧‧‧First integrated circuit package

104‧‧‧第一封裝膠體104‧‧‧First encapsulant

106‧‧‧第一封裝膠體表面106‧‧‧First encapsulant surface

108‧‧‧第一封裝件積體電路108‧‧‧First package integrated circuit

110‧‧‧第一封裝件晶片墊110‧‧‧First package wafer pad

112‧‧‧第一封裝件引線112‧‧‧First package leads

114‧‧‧第一封裝件安裝層114‧‧‧First package mounting layer

116‧‧‧第一封裝件連接器116‧‧‧First package connector

118‧‧‧第二積體電路118‧‧‧Second integrated circuit

120‧‧‧第二安裝層120‧‧‧Second installation layer

122‧‧‧第二連接器122‧‧‧Second connector

124‧‧‧封裝件內封裝件引線124‧‧‧Package lead in package

126‧‧‧封裝件內封裝件連接器126‧‧‧Package connector package

128‧‧‧封裝件內封裝件封裝膠體128‧‧‧Package encapsulation colloid

130‧‧‧封裝件內封裝件安裝表面130‧‧‧Package mounting surface in package

132‧‧‧封裝件內封裝件引線表面132‧‧‧Package lead surface in package

Claims (10)

一種積體電路封裝件內封裝方法(1700)，包括：提供封裝件內封裝引線(124)，其具有實質上為平面之封裝件內封裝件引線表面(132)；固接第一積體電路封裝件(102)，其具有第一封裝件引線(112)以及與該封裝件內封裝件引線表面(132)實質上共面之具有第一封裝膠體表面(106)的第一封裝膠體(104)，該第一封裝件引線(112)突出於該第一封裝膠體(104)；固接鄰近該第一積體電路封裝件(102)之第二積體電路(118)；以及於該第一積體電路封裝件(102)與該第二積體電路(118)上方，形成封裝件內封裝件封裝膠體(128)。 An integrated circuit package package method (1700), comprising: providing a package package lead (124) having a substantially planar package inner package lead surface (132); fixing the first integrated circuit A package (102) having a first package lead (112) and a first encapsulant (104) having a first encapsulant surface (106) substantially coplanar with the package lead surface (132) within the package The first package lead (112) protrudes from the first encapsulant (104); the second integrated circuit (118) adjacent to the first integrated circuit package (102) is fixed; An integrated circuit package (102) and the second integrated circuit (118) are formed to form a package encapsulant (128) in the package. 如申請專利範圍第1項之方法(1700)，其中，固接該第一積體電路封裝件(102)包含將該第一積體電路封裝件(102)電性連接至該封裝件內封裝件引線(124)。 The method of claim 1 (1700), wherein the fixing the first integrated circuit package (102) comprises electrically connecting the first integrated circuit package (102) to the package. Piece lead (124). 如申請專利範圍第1項之方法(1700)，其中，固接該第二積體電路(718)包含將該第二積體電路(718)固接於該第一積體電路封裝件(702)上方。 The method of claim 1 (1700), wherein the fixing the second integrated circuit (718) comprises fixing the second integrated circuit (718) to the first integrated circuit package (702) ) above. 如申請專利範圍第1項之方法(1700)，其中，固接該第二積體電路(318)包含將該第二積體電路(318)固接於鄰近該第一積體電路封裝件(302)。 The method of claim 1 (1700), wherein the fixing the second integrated circuit (318) comprises fixing the second integrated circuit (318) adjacent to the first integrated circuit package ( 302). 如申請專利範圍第1項之方法(1700)，其中，固接該第二積體電路(808)包含將具有該第二積體電路(808)之 第二積體電路封裝件(802)固接於鄰近該第一積體電路封裝件(802)。 The method of claim 1 (1700), wherein the second integrated circuit (808) is fixed to include the second integrated circuit (808) The second integrated circuit package (802) is fixed adjacent to the first integrated circuit package (802). 一種積體電路封裝件內封裝件系統(100)，包括：封裝件內封裝件引線(124)，係具有實質上為平面之封裝件內封裝件引線表面(132)；第一積體電路封裝件(102)，具有第一封裝件引線(112)以及具有與該封裝件內封裝件引線表面(132)實質上共面之第一封裝膠體表面(106)的第一封裝膠體(104)，該第一封裝件引線(112)突出於該第一封裝膠體(104)；第二積體電路(118)，係鄰近於該第一積體電路封裝件(102)；以及封裝件內封裝件封裝膠體(128)，係位於該第一積體電路封裝件(102)與該第二積體電路(118)上方。 An integrated circuit package inner package system (100) comprising: a package inner package lead (124) having a substantially planar package inner package lead surface (132); a first integrated circuit package Piece (102) having a first package lead (112) and a first encapsulant (104) having a first encapsulant surface (106) substantially coplanar with the package lead surface (132), The first package lead (112) protrudes from the first encapsulant (104); the second integrated circuit (118) is adjacent to the first integrated circuit package (102); and the package in the package The encapsulant (128) is located above the first integrated circuit package (102) and the second integrated circuit (118). 如申請專利範圍第6項之系統(100)，其中，該第一積體電路封裝件(102)包含電性連接於該封裝件內封裝件引線(124)之該第一積體電路封裝件(102)。 The system (100) of claim 6, wherein the first integrated circuit package (102) comprises the first integrated circuit package electrically connected to the package leads (124) in the package. (102). 如申請專利範圍第6項之系統(700)，其中，該第二積體電路(718)包含位於該第一積體電路封裝件(702)上方之該第二積體電路(718)。 The system (700) of claim 6, wherein the second integrated circuit (718) comprises the second integrated circuit (718) above the first integrated circuit package (702). 如申請專利範圍第6項之系統(300)，其中，該第二積體電路(318)包含鄰近於該第一積體電路封裝件(302)之該第二積體電路(318)。 The system (300) of claim 6, wherein the second integrated circuit (318) comprises the second integrated circuit (318) adjacent to the first integrated circuit package (302). 如申請專利範圍第6項之系統(800)，其中，該第二積 體電路(808)包含具有鄰近於該第一積體電路封裝件(802)之該第二積體電路(808)之第二積體電路封裝件(802)。 For example, the system (800) of claim 6 of the patent scope, wherein the second product The bulk circuit (808) includes a second integrated circuit package (802) having the second integrated circuit (808) adjacent to the first integrated circuit package (802).
TW097120150A 2007-06-27 2008-05-30 Integrated circuit package in package system with adhesiveless package attach and method of forming the same TWI495080B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/769,691 US8203214B2 (en) 2007-06-27 2007-06-27 Integrated circuit package in package system with adhesiveless package attach

Publications (2)

Publication Number Publication Date
TW200905857A TW200905857A (en) 2009-02-01
TWI495080B true TWI495080B (en) 2015-08-01

Family

ID=40159401

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097120150A TWI495080B (en) 2007-06-27 2008-05-30 Integrated circuit package in package system with adhesiveless package attach and method of forming the same

Country Status (4)

Country Link
US (1) US8203214B2 (en)
KR (1) KR101530688B1 (en)
SG (1) SG148928A1 (en)
TW (1) TWI495080B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8334584B2 (en) * 2009-09-18 2012-12-18 Stats Chippac Ltd. Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US9466413B2 (en) 2013-06-28 2016-10-11 Freescale Semiconductor, Inc. Die-to-die inductive communication devices and methods
US9160423B2 (en) 2013-12-12 2015-10-13 Freescale Semiconductor, Inc. Die-to-die inductive communication devices and methods
US10992346B2 (en) 2014-03-26 2021-04-27 Nxp Usa, Inc. Systems and devices with common mode noise suppression structures and methods
US9219028B1 (en) 2014-12-17 2015-12-22 Freescale Semiconductor, Inc. Die-to-die inductive communication devices and methods
US9911629B2 (en) * 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US11328984B2 (en) * 2017-12-29 2022-05-10 Texas Instruments Incorporated Multi-die integrated circuit packages and methods of manufacturing the same
US20190267525A1 (en) 2018-02-26 2019-08-29 Semicon Light Co., Ltd. Semiconductor Light Emitting Devices And Method Of Manufacturing The Same
US10553563B2 (en) 2018-05-30 2020-02-04 Epistar Corporation Electronic device
US20220270997A1 (en) * 2021-02-22 2022-08-25 Mediatek Inc. Semiconductor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781243B1 (en) * 2003-01-22 2004-08-24 National Semiconductor Corporation Leadless leadframe package substitute and stack package

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5366933A (en) * 1993-10-13 1994-11-22 Intel Corporation Method for constructing a dual sided, wire bonded integrated circuit chip package
KR0137826B1 (en) * 1994-11-15 1998-04-28 문정환 Package method and device package
JP2972096B2 (en) * 1994-11-25 1999-11-08 シャープ株式会社 Resin-sealed semiconductor device
JP3359846B2 (en) * 1997-07-18 2002-12-24 シャープ株式会社 Semiconductor device
KR100302593B1 (en) * 1998-10-24 2001-09-22 김영환 Semiconductor package and fabricating method thereof
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
JP2001127246A (en) * 1999-10-29 2001-05-11 Fujitsu Ltd Semiconductor device
US6344687B1 (en) * 1999-12-22 2002-02-05 Chih-Kung Huang Dual-chip packaging
US6661084B1 (en) 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
JP2002040095A (en) * 2000-07-26 2002-02-06 Nec Corp Semiconductor device and mounting method thereof
US6559539B2 (en) * 2001-01-24 2003-05-06 Hsiu Wen Tu Stacked package structure of image sensor
KR100415281B1 (en) * 2001-06-29 2004-01-16 삼성전자주식회사 Double-side Mounting Circuit Board and Multi Chip Package including the Such a Circuit Board
JP2003273317A (en) * 2002-03-19 2003-09-26 Nec Electronics Corp Semiconductor device and its manufacturing method
JP4157715B2 (en) * 2002-03-20 2008-10-01 富士通株式会社 Manufacturing method of semiconductor device
US6821817B1 (en) * 2002-09-03 2004-11-23 Asat Ltd. Premolded cavity IC package
EP1556895A4 (en) 2002-10-08 2009-12-30 Chippac Inc Semiconductor stacked multi-package module having inverted second package
US7071545B1 (en) * 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
US6879028B2 (en) * 2003-02-21 2005-04-12 Freescale Semiconductor, Inc. Multi-die semiconductor package
TWI256091B (en) * 2004-08-02 2006-06-01 Siliconware Precision Industries Co Ltd A semiconductor package having stacked chip package and a method
TWI250592B (en) * 2004-11-16 2006-03-01 Siliconware Precision Industries Co Ltd Multi-chip semiconductor package and fabrication method thereof
JP2006216911A (en) * 2005-02-07 2006-08-17 Renesas Technology Corp Semiconductor device and encapsulated semiconductor package
US8698294B2 (en) * 2006-01-24 2014-04-15 Stats Chippac Ltd. Integrated circuit package system including wide flange leadframe
US7298038B2 (en) * 2006-02-25 2007-11-20 Stats Chippac Ltd. Integrated circuit package system including die stacking
US7531383B2 (en) * 2006-10-31 2009-05-12 Freescale Semiconductor, Inc. Array quad flat no-lead package and method of forming same
US8258614B2 (en) * 2007-11-12 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with package integration
US8722457B2 (en) * 2007-12-27 2014-05-13 Stats Chippac, Ltd. System and apparatus for wafer level integration of components

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781243B1 (en) * 2003-01-22 2004-08-24 National Semiconductor Corporation Leadless leadframe package substitute and stack package

Also Published As

Publication number Publication date
US8203214B2 (en) 2012-06-19
KR20080114621A (en) 2008-12-31
TW200905857A (en) 2009-02-01
KR101530688B1 (en) 2015-06-22
US20090001563A1 (en) 2009-01-01
SG148928A1 (en) 2009-01-29

Similar Documents

Publication Publication Date Title
TWI495080B (en) Integrated circuit package in package system with adhesiveless package attach and method of forming the same
KR100618892B1 (en) Semiconductor package accomplishing a fan-out structure through wire bonding
US6861288B2 (en) Stacked semiconductor packages and method for the fabrication thereof
US8030783B2 (en) Integrated circuit package with open substrate
TWI394236B (en) Mountable integrated circuit package-in-package system with adhesive spacing structures
JP5441313B2 (en) Method and integrated circuit package system for manufacturing an integrated circuit package system having a die on a base package
US20100038781A1 (en) Integrated circuit packaging system having a cavity
US8513542B2 (en) Integrated circuit leaded stacked package system
TW200939361A (en) Integrated circuit package system with interposer
SG189741A1 (en) Integrated circuit packaging system with package-on-package stacking and method of manufacture thereof
KR101440933B1 (en) Integrated circuit package system employing bump technology
JP2016219837A (en) Stack device and manufacturing method for stack device
US20080315406A1 (en) Integrated circuit package system with cavity substrate
TWI425615B (en) Integrated circuit package system with offset stacked die
US20070052082A1 (en) Multi-chip package structure
KR20090018949A (en) Integrated circuit package system with offset stacked die
US8148208B2 (en) Integrated circuit package system with leaded package and method for manufacturing thereof
US20140097530A1 (en) Integrated circuit package
US20070085184A1 (en) Stacked die packaging system
US8148825B2 (en) Integrated circuit package system with leadfinger
TW473967B (en) Ball grid array package device having chip size substrate and the packaging method thereof
KR20100065787A (en) Substrate, semiconductor package using the substrate, and methods of fabricating the substrate
KR20080092728A (en) Semiconductor package having a recess in a printed circuit board and method of fabricating the same
KR20090098074A (en) Method of fabricating stack package
KR20020028475A (en) Stack package