TWI488246B - Method for integrating testing resources and ic testing - Google Patents

Description

Resource integration and wafer test methods

The present invention relates to a wafer test method for a semiconductor process, and more particularly to a wafer test method having a resource integration function for improving wafer test efficiency.

The Integrated Circuit (IC) industry is basically a high-tech industry consisting of four major systems: integrated circuit design, wafer fabrication, wafer testing and wafer packaging. After the manufacturing process is completed, a series of tests must be performed to ensure that the off-line production of the wafer can meet the requirements of the application target, and the process of the integrated circuit can be corrected by these test results. In addition, many wafer testing steps are typically performed after wafer fabrication is complete. If after testing, it is found that the line on the wafer is defective or does not meet the requirements, a laser repair process is usually performed to repair the defects of the wafer. Semiconductor testing of integrated circuit chips is necessary at different stages of the semiconductor process. Each IC wafer must be tested in both wafer and package form to ensure its electrical function. The demand for test products comes from two factors: the new design of the wafer and the increase in unit yield. As wafer functions become more complex and complex, high-speed and precise test requirements are even more important.

The Parametric Test for wafer testing can be divided into three parts: Wafer spec, Test spec and Limit spec. In the wafer specification, the circuit is fabricated into a test wafer module to verify the correctness of the circuit, and then a test program is written for testing specifications. Verify the correctness of the test chip circuit, and finally output the test data as a parameter to the supply limit specification to mass-produce the wafer. Wafer Acceptance Testing (WAT) is a test method for verifying the correctness of circuits on a wafer. The purpose is to find out the defects and corrections on the wafers to ensure the wafers produced. Quality. The instrument used in the wafer acceptance test already has a main program to test the various characteristics of the components on the wafer, which is measured around the die to be measured on the wafer. A plurality of test keys are formed on the Scribe line between the dies, and the contact pads (Pad) are electrically connected to the outside. Then, a module test button is selected to measure different wafer characteristics and read signals, such as threshold voltage VTH (threshold voltage) or saturation current IDSAT (saturation current). Then, the operator or tester must write a link program that links the main program to the database. The programmer or tester begins to write the program, and the operator must understand and be familiar with the meaning of the programming language and various parameters. Finally, the control mode of the human-machine interface is used to control the voltage to be applied on the test button, and the current signal to be measured is read.

However, there is no correlation between the specifications in the parametric test. When the test chip or program is wrong, it is impossible to quickly find the problem by testing the cooperation between the chip and the program. The tester will write a test program for testing the wafer test when the test wafer is sent to the machine to test the correctness of the circuit. When the test chip is sent to the machine for testing, it is often only possible to find out that the circuit of the chip may have a problem by measuring the current signal, and it is impossible to find out the problem. For example, testers spend a few days writing a link master The connection between the program and the database does not guarantee that the test program is completely correct. If the test chip is verified by the wrong test program, unintended test results will be obtained. For example, testers often check the test program's algorithm after time-consuming, and then can not find the problem, and then check the test chip and pin information of the test chip, and find that the problem occurs in the wafer missing part of the chip component or test program. Parameter input such as pin information is incorrect.

In addition, the tester must pre-designate the required test resources when writing the test program, which may result in improper resource allocation and untestable conditions. All of the above will have a considerable impact on the efficiency of wafer testing, often increasing the time and cost of wafer testing.

In view of the above, the present invention provides a resource integration and wafer testing method, in addition to establishing a test chip and a test program through a basic component group to improve the efficiency of the wafer test, and at the same time, according to the test resources and channels required for the wafer test. According to the purpose of effectively using test resources and channels.

The present invention provides a resource integration and wafer testing method. The method includes the following steps: First, a basic component group having a plurality of basic components, wherein each basic component has a basic parameter table, is provided. Next, a test wafer is created using this basic component set, in which a plurality of test components are included in the test wafer, and each test component corresponds to a basic component. And based on the test components and Each test component corresponds to a basic parameter table of the basic component, and a test program for testing the test wafer is established. According to the test program, the test resources required for each test component are determined, and the test resources are obtained according to the test resource configuration rules. If all the test resources required are obtained, the test required for each test resource is linked according to the test channel configuration rule. aisle. If the above test channel can be obtained, the test component is tested for circuit characteristics by using the test resource and the test channel.

In an embodiment of the invention, the basic parameter table records physical parameters and pin information of the basic components.

In an embodiment of the present invention, after the test program for testing the test wafer is established according to the test component and the basic parameter table of the basic component corresponding to each test component, it further includes determining whether each test component of the test wafer is The test components used to build this test program are the same. If they are different, the resource integration and wafer test methods are stopped and a warning signal is generated.

In an embodiment of the invention, it is determined whether each test component of the test chip is the same as the test component used to establish the test program, and further includes determining whether a category and a set value of each test component of the test chip are established. The type and setting of each test component used in this test program are the same. If the two are the same, it is judged that each test component of the test chip is the same as the test component used to establish the test program.

In an embodiment of the present invention, after the test program for testing the test chip is established according to the basic parameter table of the test component and the basic component corresponding to each test component, the test is further performed according to the basic parameter table to obtain each test. The setting parameters and setting values of the category corresponding to the component. Then, according to this The parameter and the set value are set to set the test program, and it is determined whether the set parameter and the set value corresponding to the test object of the test program meet the set parameter and the set value of the type corresponding to the test component used for the test chip. If the two are different, the resource integration and the wafer test method are stopped and a warning signal is generated; if the two are the same, the test resource and the test channel are used for the circuit characteristic test.

In an embodiment of the invention, the test resource configuration rule includes selecting the test resource with the lowest rank among the categories corresponding to each test component.

In an embodiment of the invention, the test resource configuration rule includes a test channel that meets the requirements of the test resource but has the lowest rank.

In an embodiment of the present invention, after obtaining the test resource according to the test resource configuration rule, the method further includes stopping the resource integration and the chip test method and generating a warning signal if all the test resources are not available.

In an embodiment of the present invention, after the test channel required for linking each test resource according to the test channel configuration rule, and further including if all the test channels required are not obtained, the resource integration and the wafer test method are stopped and generated. Warning signal.

In an embodiment of the invention, wherein the basic element is an electronic component.

In an embodiment of the invention, wherein the base element comprises a functional circuit comprised of a plurality of electronic components.

The invention utilizes a basic component group to establish a test wafer and a test program, thereby establishing a certain correlation between the two, thereby improving the reliability and efficiency of the wafer test. In addition, the present invention is also based on a test program. The test resources and test channels required for the wafer test are judged and allocated according to the test resources and the types of channels, so as to optimize the resource allocation.

The above described features and advantages of the present invention will be more apparent from the following description.

In general, if the relationship between the test chip and the test program can be established during wafer testing, it will inevitably save the debugging time required in the event of an error in the wafer test process. In addition, if the test resources can be effectively managed and only the required test resources are allocated for wafer testing, unnecessary resource waste will be reduced. The invention is based on the above viewpoint and further provides a resource integration and wafer testing method capable of improving wafer testing efficiency and effectively using test resources. In order to clarify the content of the present invention, the following specific examples are given as examples in which the present invention can be implemented.

1 is a flow chart of a resource integration and wafer testing method in accordance with a preferred embodiment of the present invention. Referring to FIG. 1, first, as shown in step 100, a basic component group including a plurality of basic components is provided. In this embodiment, the basic element is, for example, a minimum electronic component constituting a wafer or component, a functional circuit composed of a plurality of electronic components and having a basic function (for example, a logic gate, an amplifier, a flip-flop or an adder), and the like. Etc., the scope is not limited herein.

Each of the basic components in the basic component group has a basic parameter list. Information about enough to identify and represent this basic component is recorded in the basic parameter table, such as the category of the basic component, physical parameters, and pin information. Among them, the physical parameters include the aspect ratio of the basic component, the driving voltage of the basic component, or the pin information of the basic component. Among them, the pin information records the number or number of each pin used by the basic component. 2 is a schematic diagram of a basic parameter table in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, in the present embodiment, the basic components corresponding to the basic parameter table 200 are of the CMOS type, and information such as the aspect ratio of the basic components, the driving voltage, and the pin information are recorded in the basic parameter table 200.

Next, as shown in step 110, the test chip is built using the basic component set. In this embodiment, the test wafer includes a plurality of test elements, and each test element can correspond to a basic element in the basic element set, respectively. That is, the test component can be a collection of more than one basic component, or a functional circuit further comprising a plurality of electronic components and having a basic function. When establishing test components on the test wafer, it is necessary to simultaneously set the set values of the respective basic components corresponding to the test components. For example, when building a test component corresponding to a basic component such as CMOS, the aspect ratio, drive voltage, and pin information must be set.

In step 120, a test program for testing the test wafer is established based on the basic parameter table of the basic component corresponding to each test component and the previously set value. Among them, the crystal is listed in the test program. The test requirements and test methods of the chip test are based on testing the information of each basic component on the test chip (for example, basic component type, physical parameters and pin information) and circuit characteristics.

However, prior to testing the test wafer through the test program, first, as shown in step 123, it must be determined whether each test component in the test wafer is identical to all of the virtual test components of the test test wafer in the test program. Since the test components on the test wafer and the virtual test components of the test test wafer in the test program are composed of the basic components in the basic component group, it is only necessary to check the types, the number of basic components of the two components, and the coupling of the basic components. The relationship can determine whether the two are the same. For example, suppose the test program tests the test component of CMOS. At this time, it is necessary to check whether there is a test component of the CMOS type on the test wafer, and check whether the set values of the two are the same, thereby determining each test in the test wafer. The component is the same as all the test components used in building the test program. If the judgment result shows that the two are not the same, it means that the test chip may be missing some test components, or the test program is written incorrectly. At step 170, the whole wafer test process is stopped and a warning signal is issued to remind the test. personnel. After receiving the warning signal, the tester can correct the error of the test chip or the test program by checking whether the test chip is correct or whether the test component is complete, to re-expand the wafer test action.

After determining that each test component in the test wafer is identical to the virtual test component used to simulate the test wafer when the test program is established, the determination of the set value of the basic component corresponding to the test component on the test wafer is started. In this embodiment, for example, the category, the setting parameter, and the setting value corresponding to each test component are obtained according to the basic parameter table, and the physical characteristics of each basic component and the required components of the driving component can be referred to through the basic parameter table. The lowest voltage, as well as the function of each pin.

Next, in step 125, the test program is set according to the setting parameters and the set values of each test component, and the setting parameters of the analog basic components used for the test object (ie, the test wafer) simulated by the test program are determined accordingly. Whether the set value is the same as the set parameter of the basic component used in the test wafer and the corresponding set value. If the two are different, as shown in step 170, the wafer test action is stopped and a warning signal is issued to alert the tester.

In one embodiment, it is assumed that the test component in the test chip is a corresponding component of the CMOS, and the four pins D, G, S, and B are numbered 1, 2, 3, and 4, respectively. At this time, for example, the basic parameter table can be consulted to find the value of the set value of the test component corresponding to the basic component of the CMOS on the test wafer, thereby verifying whether the setting parameters of the test program are correct. If the setting parameters found in the basic parameter table include D, G, S, B, it means that the setting parameters of the test program are the same as the setting parameters of the test components of the test chip. The next wafer test step can now be performed.

After the above-mentioned check is passed, in step 130, according to the test program, which test resources are required for each test component on the test wafer, and as shown in step 140, the test components are sequentially obtained according to the test resource configuration rule. The test resources needed. In this embodiment, test resources have been previously classified into various categories, such as current Current-Voltage Unit (IVU), Capacitance Measurement Unit (CMU), Pulse Generation Unit (PGU), and the like. Test resources belonging to the same category can be subdivided into several different levels. Therefore, each time the test resource required for the test component is selected, for example, the lowest level test resource can be selected for the wafer test in the category corresponding to each test component. This not only improves the flexibility of the distribution method of test resources, but also avoids the waste of test resources, so as to achieve the purpose of testing multiple wafers simultaneously.

Next, as shown in step 150, it is determined whether the test resources required for each test component on the test wafer have been successfully obtained. If the required test resources are occupied by others (such as other wafer test processes), the wafer test operation cannot be continued. As shown in step 170, a warning signal is issued to alert the tester and stop the wafer test.

If all the required test resources have been successfully obtained, as shown in step 160, the test resources are linked to the required test channels according to the test channel configuration rules. The role of the test channel is to link the test resource to the point of measurement of the test object (ie, the test component). In this embodiment, the test channels are also pre-divided into different levels. Therefore, when the test channel connecting the test resources and the test object is selected, for example, the test channel that meets the test resource requirements, but the lowest level test channel can be selected first. Make a link.

In a test machine, there are usually many test channels for wafer testing. In the past, when testing a wafer, it was often necessary to wait for the test channel of the test machine to be completely idle before testing. for example, Assuming that a test component on the test chip has four pins of D, G, S, B, etc., the test can only be performed after the test channel corresponding to the four pins is free. If the test channel connected to one of the pins is occupied by other wafer test actions, the current test operation of the wafer cannot be performed. However, in the present invention, if the test channel required for the test component is occupied by other wafer test processes (ie, one of the test channels required for the wafer test is occupied and cannot be used), the test program attempts to search for the requirements of the test component and The idle test channel continues the wafer test without waiting for idle until all test channels are taken, thereby increasing the efficiency of the wafer test.

In step 180, it is determined whether the test channel required for each test resource has been successfully obtained. If the test channel is occupied and the link cannot be provided, then as shown in step 170, the wafer test action is stopped and a warning signal is generated to remind the test. personnel.

If the test channel required for each test resource has been successfully obtained, finally, as shown in step 190, using the obtained test resources and test channels, the test program performs circuit characteristic test on the test chip.

In summary, the resource integration and wafer testing method of the present invention uses a basic component group to construct a test wafer and a test program, and discriminates test resources required for wafer testing according to a test program for distribution. This method has at least the following advantages:

1. Using the basic component set to establish the connection between the test wafer and the test program, by comparing the test components on the test wafer and the test components of the test wafer simulated in the test program, according to which the test of the circuit characteristics is performed before Find errors in test wafers or test programs to make wafer testing more efficient.

2. By comparing the setting parameters of the test components in the test program and the setting parameters recorded in the basic parameter table of the basic components, it is possible to eliminate problems such as input parameter errors of the test program.

3. According to the requirements of each test component on the test chip, the test resources are effectively allocated to avoid the waste of test resources, thereby achieving the purpose of optimizing resource allocation.

4. Self-search for test channels that meet the test component requirements for wafer testing, without waiting for all test channels to be released, thus saving wafer test time.

5. Through the effective allocation of test resources and test channels, it is achieved by a single test machine to perform multiple wafer tests simultaneously.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100~190‧‧‧ steps of the resource integration and wafer testing method described in the preferred embodiment of the invention

200‧‧‧Basic Parameter Table

1 is a flow chart of a resource integration and wafer testing method in accordance with a preferred embodiment of the present invention.

2 is a schematic diagram of a basic parameter table according to another preferred embodiment of the present invention.

100~190‧‧‧ steps of the resource integration and wafer testing method described in the preferred embodiment of the invention

Claims (12)

A resource integration and wafer testing method, the method comprising the steps of: a. providing a basic component group having a plurality of basic components, wherein each of the basic components has a basic parameter table; b. using the basic component group to establish a Testing a wafer, wherein the test wafer includes a plurality of test elements, and each of the test elements respectively corresponds to one of the basic elements; c. according to the basic parameter list of the basic elements corresponding to each of the test elements Establishing a test program for testing the test chip; d. determining, according to the test program, that each of the test components requires one test resource; e. obtaining the test resource according to a test resource configuration rule; f. To obtain all the test resources required, one test channel required for each test resource is connected according to a test channel configuration rule; and g. if each test channel can be connected, the test resource and the test channel are used to The test program performs a circuit characteristic test on the test wafer. For example, the resource integration and wafer test method described in claim 1 wherein the basic parameter table records physical parameters and pin information of the basic component. The resource integration and wafer testing method described in claim 1 of the patent application, wherein after step c., further comprises: Determining whether each of the test elements of the test chip is the same as the test elements used to establish the test program; and if the two are different, stopping the resource integration and wafer test method and generating a warning signal. The resource integration and wafer testing method of claim 3, wherein determining whether each of the test components of the test chip is the same as the test components used to establish the test program further comprises: determining the test Whether a category and a set value of each of the test elements of the chip are the same as the category and the set value of each of the test elements used in establishing the test program; and if the two are the same, determining the test chip Each of the test elements is the same as the test elements used to create the test program. The method for resource integration and wafer testing according to claim 1, wherein after step c., further comprising: obtaining a setting parameter and a setting of one of each of the test elements according to the basic parameter table. Setting the test program according to the set parameter and the set value, and determining whether the set parameter corresponding to the test object of the test program and the set value meet the category corresponding to the test elements used by the test chip Setting parameters and the set values; and if the two are different, stopping the resource integration and the wafer test method and generating a warning signal. The resource integration and wafer test method as described in claim 1, wherein the test resource configuration rule comprises: In each of the corresponding test component categories, the test resource with the lowest rank is selected. The resource integration and wafer testing method described in claim 1, wherein the test channel configuration rule comprises: connecting the test channel that meets the requirements of the test resource but has the lowest level. For example, the resource integration and wafer test method described in claim 1 includes, after step e., if the test resources are not available, the resource integration and the wafer test method are stopped and a warning signal is generated. For example, the resource integration and wafer testing method described in claim 1 includes, after the step f., the resource integration and the wafer testing method are stopped and a warning signal is generated if all the test channels are not available. For example, the resource integration and wafer testing method described in claim 1 further includes: when the test component requires the test channel to be unusable, searching for other test channels that are idle for testing. The resource integration and wafer testing method of claim 1, wherein the basic component is an electronic component. The resource integration and wafer testing method of claim 1, wherein the basic component comprises a functional circuit composed of a plurality of electronic components.