TWI474450B - Package carrier and manufacturing method thereof - Google Patents

Description

Package carrier board and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package carrier and a method of fabricating the same.

The purpose of the chip package is to protect the exposed wafer, reduce the density of the wafer contacts, and provide good heat dissipation from the wafer. A common packaging method is that the wafer is mounted to a loading board by wire bonding or flip chip bonding so that the contacts on the wafer can be electrically connected to the package carrier. Therefore, the contact distribution of the wafer can be reconfigured by the package carrier to conform to the junction distribution of the external components of the next level.

In general, the package carrier is usually fabricated using a core dielectric layer as a core material and using a fully additive process, a semi-additive process, and a subtractive method ( Subtractive process or otherwise, the patterned circuit layer and the patterned dielectric layer are interleaved on the core dielectric layer. As a result, the core dielectric layer will occupy a considerable proportion of the overall thickness of the package carrier. Therefore, if the thickness of the core dielectric layer cannot be effectively reduced, it is bound to The package structure creates a significant obstacle to thickness reduction.

The present invention provides a package carrier board suitable for carrying a wafer, and a package structure using the package carrier board has a small package thickness.

The present invention provides a method of fabricating a package carrier for fabricating the package carrier described above.

The method of fabricating a package carrier of the present invention comprises the steps of first joining two base metal layers. Next, the two support layers are respectively pressed onto the two base metal layers. Thereafter, two release metal films are respectively disposed on the two support layers, wherein each of the release metal films includes a first metal foil layer and a second metal foil layer which are separable from each other. Next, two first patterned metal layers are respectively formed on the two release metal films. Each of the first patterned metal layers includes a pad pattern. Then, two dielectric layers are respectively formed on the two release metal films and cover the corresponding first patterned metal layers, and each of the dielectric layers has via holes respectively connected to the corresponding pad patterns. Next, two second patterned metal layers are formed on the two dielectric layers, respectively. Each of the second patterned metal layers covers at least the upper surface of the corresponding via. Thereafter, the two base metal layers are separated to form separate packaged carrier plates.

The package carrier of the present invention is adapted to carry a wafer comprising a support layer, a base metal layer, a release metal film, a first patterned metal layer, a dielectric layer and a second patterned metal layer. The support layer includes a first surface and a second surface opposite the first surface. The base metal layer is disposed on the first surface of the support layer. The release metal film is disposed on the second surface of the support layer. Release metal film includes And a first metal foil layer and a second metal foil layer, wherein the second metal foil layer is bonded to the support layer. The first patterned metal layer is disposed on the release metal film and includes at least one pad pattern. The dielectric layer is disposed on the release metal film and covers the first patterned metal layer. The dielectric layer has at least one via hole connected to the corresponding pad pattern. The second patterned metal layer is disposed on the dielectric layer and covers at least an upper surface of the corresponding via. The wafer is adapted to be disposed on and electrically connected to the second patterned metal layer.

Based on the above, the package carrier of the present invention performs the process of packaging the carrier on the two base metal layers bonded to each other in a symmetrical manner. Therefore, after forming the stacked structures on the two base metal layers respectively, the two substrates are bonded to each other. By separating the metal layers, two separate package carriers can be obtained at the same time, which saves process time and improves production efficiency. In addition, the present invention utilizes a method of pressing a dielectric layer on a support layer and forming via holes and a patterned metal layer on the dielectric layer to form a stacked structure of the carrier and the electrical connection wafer, and connecting the release metal film to Between the support layer and the patterned metal layer, the support layer is adapted to be easily removed by the separable properties of the release metal film. Thus, the package carrier of the present invention allows a subsequently completed package structure to have a thinner package thickness than conventional package carriers.

The above described features and advantages of the invention will be apparent from the following description.

10, 10a‧‧‧ package structure

100‧‧‧Package carrier

105‧‧‧ glue layer

110‧‧‧base metal layer

120‧‧‧Support layer

122‧‧‧ first surface

124‧‧‧ second surface

130‧‧‧ release metal film

132‧‧‧First metal foil layer

134‧‧‧Second metal foil layer

140‧‧‧etch stop layer

150‧‧‧First patterned metal layer

152‧‧‧push pattern

160‧‧‧ dielectric layer

162‧‧‧through holes

164‧‧‧through hole

166‧‧‧ Conductive layer

170‧‧‧Second patterned metal layer

172‧‧‧ surface treatment layer

174‧‧‧ wafer pads

176‧‧‧Joint pads

180‧‧‧ patterned solder mask

200‧‧‧ wafer

210‧‧‧Wire

220‧‧‧Package colloid

230‧‧‧ solder balls

1A to 1H are a system for packaging a carrier board according to an embodiment of the invention. A schematic cross-sectional view of the process steps.

2A-2C are cross-sectional views showing a process of carrying a wafer of the package carrier of FIG. 1H.

3 is a cross-sectional view of a package carrier carrying a wafer in accordance with another embodiment of the present invention.

1A-1H are schematic cross-sectional views showing a process of packaging a carrier board in accordance with an embodiment of the invention. In this embodiment, the method for fabricating the package carrier includes the following steps: First, referring to FIG. 1A, the two base metal layers 110 are bonded. In this embodiment, the two base metal layers 110 are respectively two copper foil layers, and the two base metal layers 110 are bonded to the two base metal layers by coating the adhesive layer 105 on the periphery of the two base metal layers 110. The periphery of the 110 forms a close-contact region to temporarily bond the two base metal layers 110 together to prevent the agent used in the subsequent process from penetrating between the two base metal layers 110.

Referring to FIG. 1B, the two support layers 120 are respectively pressed onto the two base metal layers 110. Then, two release metal films 130 are respectively disposed on the two support layers 120, wherein each of the release metal films 130 includes a first metal foil layer 132 and a second metal foil layer 134 that are separable from each other. In the present embodiment, the thickness of the second metal foil layer 134 is substantially greater than the thickness of the first metal foil layer 132. Specifically, the thickness of the second metal foil layer 134 is about 18 micrometers (μm), and the thickness of the first metal foil layer 132 is about 5 micrometers (μm). Of course, this embodiment is for illustrative purposes only and is not limited thereto.

Next, referring to FIG. 1C , two first patterned metal layers 150 are respectively formed on the two release metal films 130 , wherein each of the first patterned metal layers 150 includes at least one pad pattern 152 . Here, the first patterned metal layer 150 shown in FIG. 1C is for illustration only, and the number of the pad patterns 152 is not limited in this embodiment. The first patterned metal layer 150 can be formed by an additive process such as pattern plating. Of course, in other embodiments of the present invention, the patterned metal layer 150 can also be subjected to an etching process or the like. Process) formation.

In addition, in an embodiment of the present invention, two etch stop layers 140 as shown in FIG. 1C may be separately formed on the release metal film 130 before the patterned metal layer 150 is formed. The etch stop layer 140 is, for example, a nickel layer and can be formed on the release metal film 130 by electroplating.

Next, referring to FIG. 1D and FIG. 1E , two dielectric layers 160 are respectively formed on the two release metal films 130 , and the two dielectric layers 160 cover the corresponding first patterned metal layer 150 as shown in FIG. 1D . Next, as shown in FIG. 1E, at least one via 164 is formed on each dielectric layer 160, wherein each via 164 exposes a corresponding pad pattern 152. Then, a conductive layer 166 is formed in each of the via holes 164 to form at least one via hole 162 on each of the dielectric layers 160, so that each of the dielectric layers 160 has at least one via hole 162, which are respectively connected to corresponding vias. Pad pattern 152. In the present embodiment, the via 164 can be formed on the dielectric layer 160 by, for example, laser drilling, and the conductive layer 166 is formed in the via 164 by, for example, electroless plating. In addition, in other embodiments, the conductive layer 166 may also be filled in the via 164 by electroplating or the like. The present invention does not limit the manner in which the via holes 162 are formed.

Next, referring to FIG. 1F , two second patterned metal layers 170 are respectively formed on the two dielectric layers 160 , wherein each of the second patterned metal layers 170 covers at least the upper surface of the corresponding via 162 . In this embodiment, if each of the second patterned metal layers 170 has a width of between about 15 micrometers and 35 micrometers, that is, the second patterned metal layer 170 can be regarded as a fine line, the second patterned The formation of the metal layer 170 can be formed, for example, by an additive process such as pattern plating. In detail, the method for forming the second patterned metal layer 170 may include the following steps: first, forming two patterned photoresist layers on the two dielectric layers 160, and each patterned photoresist layer exposing a corresponding portion of the dielectric Layer 160 and corresponding vias 162. Then, the patterned photoresist layer is used as a plating mask, and the second patterned metal layer 170 is formed on the exposed portion of the dielectric layer 160 by electroplating. After that, the patterned photoresist layer can be removed.

In addition, in this embodiment, the two surface treatment layers 172 as shown in FIG. 1F may be respectively formed on the upper surfaces of the two second patterned metal layers 170 before the patterned photoresist layer is removed. In this embodiment, the surface treatment layer 172 may include an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel palladium layer, a nickel palladium layer or an organic solder resist. (organic solderability preservatives, OSP) layer, of course, this embodiment is not limited thereto. Thereafter, the patterned photoresist layer is removed to form a second patterned metal layer 170 and a surface treatment layer 172 on the dielectric layer 160 as shown in FIG. 1F.

Of course, in other embodiments, the second patterned metal layer 170 can also be formed by a subtractive process such as an etching process. In detail, if The method for forming the second patterned metal layer 170 may include, for example, the following steps: first, forming two second metal layers on the two dielectric layers 160, Each of the second metal layers comprehensively covers the corresponding dielectric layer 160, and then, respectively, two patterned photoresist layers are formed on the two second metal layers, and each of the patterned photoresist layers covers the corresponding portion of the second metal layer and The upper surface of the corresponding via hole 162, and then the portions of the two second metal layers not covered by the two patterned photoresist layers are removed to form the second patterned metal layer 170. Of course, the present invention does not limit the method of forming the second patterned metal layer 170 and its line width.

In addition, in this embodiment, the two surface treatment layers 172 may be separately formed on the second metal layer before the patterned photoresist layer is formed on the second metal layer. In this embodiment, the surface treatment layer 172 may include an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel palladium layer, a nickel palladium layer or an organic solder resist. (organic solderability preservatives, OSP) layer, of course, this embodiment is not limited thereto. Then, the second metal layer and the surface treatment layer 172 are further subjected to a subsequent patterning process to form a second patterned metal layer 170 and a surface treatment layer 172 on the dielectric layer 160 as shown in FIG. 1F.

Next, referring to FIG. 1G, two patterned solder mask layers 180 are respectively formed on the two dielectric layers 160, and each patterned solder resist layer 180 has a plurality of openings as shown in FIG. 1G to expose the corresponding second patterning. Metal layer 170. Next, as shown in FIG. 1H, the adhesion regions of the two base metal layers 110 are separated to separate the two base metal layers 110 to form separate package carriers 100. Thus, each package carrier 100 formed according to the above manufacturing method includes a support layer 120, a base metal layer 110, and a release gold. The film 130, a first patterned metal layer 150, a dielectric layer 160, and a second patterned metal layer 170. The support layer 120 includes a first surface 122 and a second surface 124 opposite the first surface 122. The base metal layer 110 is disposed on the first surface 122 of the support layer 120 , and the release metal film 130 is disposed on the second surface 124 of the support layer 120 . The release metal film 130 includes a first metal foil layer 132 and a second metal foil layer 134 that are separable from each other, wherein the second metal foil layer 134 is bonded to the support layer 120, and the first patterned metal layer 150 is disposed. On the first metal foil layer 132 of the release metal film 130 and including at least one pad pattern 152. The dielectric layer 160 is disposed on the release metal film 130 and covers the first patterned metal layer 150. The dielectric layer 160 has at least one via hole 162 connected to the corresponding pad pattern 152. The second patterned metal layer 170 is disposed on the dielectric layer 160 and covers at least the upper surface of the corresponding via hole 162.

It should be noted that the package carrier 100 of the present embodiment only describes a method for fabricating a stacked single-layer dielectric layer. Of course, the present invention does not limit the number of layers of the package carrier 100, and any one of the technical fields has Generally, the knowledgeer can change and adjust the number of layers of the package carrier 100 according to the requirements of the product. Moreover, since the embodiment performs the process of packaging the carrier in a symmetrical manner, after the board is removed (ie, after the two base metal layers 110 are separated), two independent package carriers can be obtained at the same time, which can effectively save. Process time and increase production efficiency.

2A-2C are cross-sectional views showing a process of carrying a wafer of the package carrier of FIG. 1H. Referring to FIG. 2A , in the embodiment, the package carrier 100 formed by the foregoing manufacturing method is suitable for carrying and electrically connecting a wafer 200 . In this embodiment, the wafer 200 is, for example, a single wafer or a wafer module. This embodiment The second patterned metal layer 170 may include at least one die pad 174 and a plurality of bond pads 176. The die 200 may be disposed on the die pad 174 through an adhesive layer, and the wafer 200 can be electrically connected to the bonding pads 176 of the second patterned metal layer 170 via at least one wire 210, for example. That is, the wafer 200 of the present embodiment is electrically connected to the second patterned metal layer 170 by wire bonding.

Next, as shown in FIG. 2B, a glue process is performed to form the encapsulant 220 on the package carrier 100, wherein the encapsulant 220 covers the wafer 200, the wires 210, and the upper surface of the package carrier 100. Thereafter, the first metal foil layer 132 and the second metal foil layer 134 are separated from each other to remove the support layer 120, and the release metal film 130 remaining on the dielectric layer 160 is removed through an etching process (for example, A metal foil layer 132) exposes the lower surface of the dielectric layer 160 and the first patterned metal layer 150.

Here, since the etch stop layer 140 is formed on the release metal film 130 before the first patterned metal layer 150 is formed in this embodiment, that is, the etch stop layer 140 is located at the first patterned metal layer 150 and away from Between the metal films 130. Therefore, when the residual release metal film 130 is removed through the etching process, the etching process stops at the etch stop layer 140 without damaging the first patterned metal layer 150. Finally, the etch stop layer 140 is removed to form the package structure 10 as shown in FIG. 2C.

3 is a cross-sectional view of a package carrier carrying a wafer in accordance with another embodiment of the present invention. It should be noted that the embodiment of FIG. 3 is similar to the package structure 10 of FIG. 2C, and thus the component numbers and parts of the foregoing embodiments are used, wherein The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Referring to FIG. 3, the package carrier of the present embodiment is adapted to carry a plurality of wafers 200 (shown as two). Accordingly, each of the first patterned metal layers 150 may include a plurality of pads corresponding to the wafer 200. The pattern 152, and the dielectric layer 160 correspondingly includes a plurality of vias 162 connected to the pad pattern 152, and the second patterned metal layer 170 also includes a plurality of wafer pads 174. The wafers 200 are respectively disposed on the wafer pads 174 and electrically connected to the plurality of bonding pads 176 of the second patterned metal layer 170 through the plurality of wires 210. Thereafter, the package structure 10a is further transmitted through the plurality of solder balls 230, for example. Electrically connected to external electronic components. In addition, the embodiment further selectively forms the patterned solder resist layer 180 on the dielectric layer 160, and each patterned solder resist layer 180 has a plurality of openings as shown in FIG. 3 to expose the corresponding second. The metal layer 170 is patterned, and the via hole 162 can be formed by micro-via on the dielectric layer 160 by laser drilling as shown in FIG. 3, and then formed into a micro-via through a method such as electroless plating. Inside. Alternatively, in other embodiments, the vias 162 may also form conductive posts, such as by electroplating or the like. Of course, the present invention does not limit the manner in which the vias 162 are formed, and the number of the carrier-carrying wafers is not limited.

In summary, the package carrier of the present invention performs the process of packaging the carrier on the two base metal layers bonded to each other in a symmetrical manner. Therefore, after the process of packaging the carrier is completed, the two base metals are bonded to each other. Layers, two separate package carriers can be obtained at the same time, which saves process time and improves production efficiency. In addition, the present invention utilizes a method of pressing a dielectric layer on a support layer and forming via holes and a patterned metal layer on the dielectric layer to form a stacked structure of the carrier and the electrical connection wafer, and connecting the release metal film to Between the support layer and the patterned metal layer, the support layer can be easily removed by the separation property of the release metal film after completing the sealing process of the wafer. Therefore, the package carrier of the present invention can make a subsequent completed package structure more than a conventional package carrier formed by stacking a plurality of patterned circuit layers and patterned dielectric layers on a core dielectric layer. Thin package thickness. Therefore, the package carrier of the present invention can not only effectively save process time, improve production efficiency, but also effectively reduce the package thickness of the package structure that is subsequently completed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Package carrier

110‧‧‧base metal layer

120‧‧‧Support layer

122‧‧‧ first surface

124‧‧‧ second surface

130‧‧‧ release metal film

140‧‧‧etch stop layer

150‧‧‧First patterned metal layer

152‧‧‧push pattern

160‧‧‧ dielectric layer

162‧‧‧through holes

170‧‧‧Second patterned metal layer

172‧‧‧ surface treatment layer

180‧‧‧ patterned solder mask

Claims (20)

A method for fabricating a package carrier includes: bonding two base metal layers; respectively pressing two support layers on the two base metal layers; respectively, disposing two release metal films on the two support layers, wherein each of the release metals The film includes a first metal foil layer and a second metal foil layer separated from each other; and two first patterned metal layers are respectively formed on the two release metal films, each of the first patterned metal layers including at least one connection a pad pattern; respectively forming two dielectric layers on the two release metal film and covering the corresponding first patterned metal layer, each of the dielectric layers having at least one via hole respectively connected to the corresponding pad pattern; respectively forming Two second patterned metal layers on the two dielectric layers, each of the second patterned metal layers covering at least one upper surface of the corresponding via hole; and separating the two base metal layers to form two independent packages Carrier board. The method of fabricating a package carrier according to claim 1, wherein the thickness of the second metal foil layer is substantially greater than the thickness of the first metal foil layer. The method for manufacturing a package carrier according to claim 1, wherein the step of each of the dielectric layers having at least one via hole further comprises: forming at least one via hole on each of the dielectric layers, wherein each of the via holes Exposing a corresponding pad pattern; and forming a conductive layer in each of the via holes to form the at least one via hole on each of the dielectric layers. The method for fabricating a package carrier according to claim 3, wherein the method of forming the conductive layer in each of the via holes comprises electroless plating or electroplating. The method for fabricating a package carrier according to the first aspect of the invention, wherein the forming the two second patterned metal layers on the two dielectric layers respectively comprises: forming two patterned photoresist layers on the two On the dielectric layer, each of the patterned photoresist layers exposes a corresponding portion of the dielectric layer and corresponding via holes; and the two patterned photoresist layers are used as masks to form the two second patterned metal layers respectively for exposure Portions of the two dielectric layers; and removing the two patterned photoresist layers. The method for fabricating a package carrier according to claim 5, wherein a width of each of the second patterned metal layers is substantially between 15 micrometers and 35 micrometers. The method for fabricating a package carrier according to claim 1, wherein the separately forming the two second patterned metal layers on the two dielectric layers comprises: forming two second metal layers respectively on the two dielectric layers On the electrical layer, two patterned photoresist layers are respectively formed on the two second metal layers, and each of the patterned photoresist layers covers a corresponding portion of the second metal layer and corresponding via holes; The portions of the second metal layer are covered by the patterned photoresist layer to form the two second patterned metal layers on the two dielectric layers. The method for fabricating a package carrier according to claim 7, wherein a width of each of the second patterned metal layers is substantially 35 μm or more. The method for manufacturing the package carrier as described in claim 1 of the patent application, And forming two etch stop layers on the two release metal films before forming the two first patterned metal layers on the two release metal films, respectively. The method of fabricating a package carrier according to claim 9, wherein the two etch stop layers comprise an electroplated nickel layer. The method for fabricating a package carrier according to claim 1, further comprising: forming two patterned solder masks respectively after forming the two second patterned metal layers on the two dielectric layers respectively The two dielectric layers are exposed and the corresponding second patterned metal layer is exposed. The method for fabricating a package carrier according to claim 1, further comprising: after forming the two second patterned metal layers on the two dielectric layers, respectively forming two surface treatment layers on the two Two patterned metal layers. The method for fabricating a package carrier according to claim 12, wherein each of the surface treatment layers comprises an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel palladium layer, and a nickel palladium layer. Layer or organic solderability preservatives (OSP) layer. A package carrier, which is adapted to carry a wafer, comprising: a support layer comprising a first surface and a second surface opposite to the first surface; a base metal layer disposed on the first surface of the support layer ; a release metal film disposed on the second surface of the support layer, the release metal film comprising a first metal foil layer and a second metal foil layer separated from each other, the second metal foil layer and the a first patterned metal layer is disposed on the release metal film and includes at least one pad pattern, wherein the first patterned metal layer is disposed on the first metal foil layer; a dielectric layer Providing on the release metal film and covering the first patterned metal layer, the dielectric layer having at least one via hole connected to the corresponding pad pattern; and a second patterned metal layer disposed on the dielectric layer An upper surface of the corresponding via hole is disposed on the layer, and the wafer is adapted to be disposed on the second patterned metal layer and electrically connected thereto. The package carrier of claim 14, wherein the thickness of the second metal foil layer is substantially greater than the thickness of the first metal foil layer. The package carrier of claim 14, further comprising an etch stop layer disposed between the release metal film and the patterned metal layer. The package carrier of claim 16, wherein the etch stop layer comprises an electroplated nickel layer. The package carrier of claim 14, further comprising a surface treatment layer covering an upper surface of the patterned metal layer. The package carrier according to claim 18, wherein the surface treatment layer comprises an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel palladium layer, a nickel palladium layer or an organic layer. An organic solderability preservatives (OSP) layer. The package carrier of claim 14, further comprising a solder mask disposed on the dielectric layer and exposing the second patterned metal layer.