TWI470699B - 具有超級介面之溝槽型功率電晶體元件及其製作方法 - Google Patents
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Description
本發明係關於一種溝槽型功率電晶體元件及其製作方法,尤指一種具有超級介面之溝槽型功率電晶體元件及其製作方法。
在功率電晶體元件中,汲極與源極間導通電阻RDS(on)的大小係與元件之功率消耗成正比,因此降低導通電阻RDS(on)的大小可減少功率電晶體元件所消耗之功率。於導通電阻RDS(on)中,用於耐壓之磊晶層所造成之電阻值所佔的比例係為最高。雖然增加磊晶層中導電物質之摻雜濃度可降低磊晶層之電阻值,但磊晶層的作用係為用於承受高電壓。若增加摻雜濃度會降低磊晶層之崩潰電壓,因而降低功率電晶體元件之耐壓能力。
為了維持或提升功率電晶體元件之耐壓能力,並降低磊晶層之電阻值,目前已發展出一種具有超級介面(super junction)之功率電晶體元件,以兼具高耐壓能力以及低導通電阻。於習知功率電晶體元件中,基底上係形成有沿著水平方向交替設置P型磊晶層與N型磊晶層,使P型磊晶層與N型磊晶層形成複數個PN接面,彼此平行且垂直於基底表面。習知製作功率電晶體元件之方法係利用蝕刻製程於N型磊晶層中形成複數個深溝槽,然後於深溝槽中填入P型磊晶層。然而,深溝槽之深寬比具有一定大小,且習知之蝕刻製程所製作出之溝槽的深寬比有一定的限制,因此P型磊晶層亦不易完整填充於溝槽中,而容易於其中產生空隙,使超級介面有缺陷。
有鑑於此,提供一種具有超級介面之功率電晶體元件及其製作方法,來避免形成有缺陷之超級介面實為業界努力之目標。
本發明之主要目的在於提供一種具有超級介面之溝槽型功率電晶體元件及其製作方法,以避免形成有缺陷之超級介面。
為達上述之目的,本發明提供一種具有超級介面之溝槽型功率電晶體元件之製作方法。首先,提供一基底,且基底具有一第一導電類型。然後,於基底上形成一磊晶層,且磊晶層具有不同於第一導電類型之一第二導電類型。接著,於磊晶層中形成至少一穿孔,貫穿磊晶層。隨後,於穿孔之二側的磊晶層中分別形成二汲極摻雜區,且汲極摻雜區從磊晶層之上表面延伸至與基底相接觸,其中汲極摻雜區具有第一導電類型。接著,於穿孔中填入一絕緣層,且絕緣層之上表面低於磊晶層之上表面。然後,於絕緣層上之穿孔之各側的磊晶層中分別形成一通道摻雜區,使位於絕緣層上之穿孔之各側的各汲極摻雜區轉變為各通道摻雜區,其中通道摻雜區具有第二導電類型。隨後,於絕緣層上之穿孔中形成一閘極結構。然後,於穿孔之各側的磊晶層中分別形成一源極摻雜區,且源極摻雜區具有第一導電類型。
為達上述之目的,本發明提供另一種具有超級介面之溝槽型功率電晶體元件之製作方法。首先,提供一基底,且基底具有一第一導電類型。然後,於基底上形成一第一磊晶層,且第一磊晶層具有不同於第一導電類型之一第二導電類型。接著,於第一磊晶層中形成至少一第一穿孔,貫穿第一磊晶層。其後,於第一穿孔之二側的第一磊晶層中分別形成二汲極摻雜區,且汲極摻雜區從第一磊晶層之上表面延伸至與基底相接觸,其中汲極摻雜區具有第一導電類型。之後,於第一穿孔中填滿一絕緣層。接著,於第一磊晶層與絕緣層上形成一第二磊晶層,且第二磊晶層具有第二導電類型。然後,於第二磊晶層中形成至少一第二穿孔,曝露出絕緣層。接著,於第二穿孔中形成一閘極結構。隨後,於第二穿孔之二側的第二磊晶層中分別形成二源極摻雜區,且源極摻雜區具有第一導電類型。
為達上述之目的,本發明提供一種具有超級介面之溝槽型功率電晶體元件,包括一基底、一第一磊晶層、至少二汲極摻雜區、一絕緣層、至少二通道摻雜區、一閘極結構以及至少二源極摻雜區。基底具有一第一導電類型。第一磊晶層設於基底上,且具有至少一穿孔,其中第一磊晶層具有不同於第一導電類型之一第二導電類型。汲極摻雜區設於穿孔二側之第一磊晶層中,且與基底相接觸,其中汲極摻雜區具有第一導電類型。絕緣層設於穿孔中,且絕緣層之上表面低於第一磊晶層之上表面。通道摻雜區分別設於汲極摻雜區上之第一磊晶層中,並分別與汲極摻雜區相接觸,其中通道摻雜區具有第二導電類型。閘極結構設於絕緣層上之穿孔中。源極摻雜區分別設於穿孔二側之第一磊晶層中,並分別與通道摻雜區相接觸,其中源極摻雜區具有第一導電類型。
為達上述之目的,本發明提供另一種具有超級介面之溝槽型功率電晶體元件,包括一基底、一第一磊晶層、至少二汲極摻雜區、一絕緣層、一第二磊晶層、一閘極結構以及至少二源極摻雜區。基底具有一第一導電類型。第一磊晶層設於基底上,且具有至少一第一穿孔,其中第一磊晶層具有不同於第一導電類型之一第二導電類型。汲極摻雜區設於第一穿孔二側之第一磊晶層中,且各汲極摻雜區從第一磊晶層之上表面延伸至與基底相接觸,其中汲極摻雜區具有第一導電類型。絕緣層填滿第一穿孔。第二磊晶層設於第一磊晶層上,並與汲極摻雜區相接觸,且第二磊晶層具有至少一第二穿孔,設於絕緣層上,其中第二磊晶層具有第二導電類型。閘極結構設於絕緣層上之第二穿孔中。源極摻雜區分別設於第二穿孔二側之第二磊晶層中,其中源極摻雜區具有第一導電類型。
本發明利用斜角度離子佈植製程或氣相摻雜製程於磊晶層中形成汲極摻雜區,使所形成之超級介面具有平整性。藉此,可避免在直接於磊晶層之穿孔中填入另一磊晶層之情況下因所填入之磊晶層產生空隙而造成超級介面有缺陷。
請參考第1圖至第9圖,第1圖至第9圖,第1圖至第9圖為本發明一第一較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖,其中第9圖為本發明第一較佳實施例之具有超級介面之溝槽型功率電晶體元件之剖面示意圖。如第1圖所示,首先提供一基底102,例如:矽晶圓,且基底102具有一第一導電類型。然後,利用一磊晶製程,例如:物理氣相沉積製程或化學氣相沉積製程,於基底102上形成一磊晶層104,且磊晶層104具有不同於第一導電類型之一第二導電類型。隨後,於磊晶層104上形成一襯墊層106。然後,利用一第二導電類型之離子佈植製程與一熱趨入製程,於磊晶層104中形成一井區108,且井區108具有第二導電類型。並且,本實施例之第一導電類型與第二導電類型分別為N型與P型,但不限於此,亦可互換。於本發明之其他實施例中,襯墊層106亦可選擇性地未形成於磊晶層104上,且井區108亦可選擇性地未形成於磊晶層104中。
如第2圖所示,進行一沉積製程,於襯墊層106上形成一第一硬遮罩層110,例如:氮化矽。然後,進行另一沉積製程,於第一硬遮罩層110上形成一第二硬遮罩層112,例如:氧化矽。接著,圖案化第二硬遮罩層112、第一硬遮罩層110以及襯墊層106,以形成一開口,曝露出P型磊晶層104。然後,以第二硬遮罩層112為遮罩,進行一蝕刻製程,於P型磊晶層104中形成複數個穿孔104a,分別貫穿P型磊晶層104,且曝露出N型基底102。各穿孔104a可進一步延伸至N型基底102,但不限於此。此外,本發明之穿孔104a之數量不限為複數個,亦可僅為單一個。
如第3圖所示,接著,於各穿孔104a之二側的P型磊晶層104與P型井區108中分別植入複數個N型離子。於本實施例中,於P型磊晶層104與P型井區108中植入N型離子之步驟可利用一N型斜角度離子佈植製程(tilt angle ion implantation process)或一N型氣相摻雜製程(vapor phase doping process),但不限於此。然後,進行一熱趨入製程,於各穿孔104a之二側的P型磊晶層104與P型井區108中分別形成二N型汲極摻雜區114,且N型汲極摻雜區114從P型磊晶層104之上表面延伸至與N型基底102相接觸。藉此,N型汲極摻雜區114可與P型磊晶層104相接觸而形成一PN接面,亦即超級介面,從P型磊晶層104延伸至N型基底102,且PN接面係約略垂直N型基底102。隨後,進行另一況積製程,於第二硬遮罩層112上形成一絕緣材料層113,例如:氧化矽,且絕緣材料層113填滿於各穿孔104a中。值得注意的是,本實施例利用斜角度離子佈植製程或氣相摻雜製程將N型離子植入P型磊晶層104中,然後在藉由熱趨入製程擴散N型離子而形成N型汲極摻雜區114,使所形成之超級介面具有平整性,進而避免在直接於穿孔104a中填入N型磊晶層之情況下因N型磊晶層產生空隙而造成超級介面有缺陷。
如第4圖所示,然後,移除位於各穿孔104a外之絕緣材料層113與第二硬遮罩層112。由於本實施例之絕緣材料層113與第二硬遮罩層112係由相同材料所構成,因此移除位於各穿孔104a外之絕緣
材料層與第二硬遮罩層112之步驟可利用進行一研磨製程來完成,但本發明不以此為限。接著,進行另一蝕刻製程,移除各穿孔104a中之部分絕緣材料層113,以形成一絕緣層116,且絕緣層116之上表面低於P型磊晶層104之上表面。並且,P型井區108之底部約略與絕緣層116之上表面位於同一平面,但不限於此。
如第5圖所示,接著,於絕緣層116上之各穿孔104a之各側的P型井區108中植入複數個P型離子。於本實施例中,於P型井區108中植入P型離子之步驟可利用一P型斜角度離子佈植製程或一P型氣相摻雜製程,但不限於此。然後,進行一熱趨入製程,於絕緣層116上之各穿孔104a之各側的P型井區108中形成一P型通道摻雜區118,且此P型通道摻雜區118係利用前述之P型摻雜轉變絕緣層116上之各穿孔104a之各N型汲極摻雜區114,使各P型通道摻雜區118分別與其下方之各N型汲極摻雜區114相接觸。隨後,移除第一硬遮罩層110以及襯墊層106,以曝露出P型磊晶層104之上表面。本實施例之P型通道摻雜區118可作為溝槽型功率電晶體元件100之通道區。於本發明之其他實施例中,植入N型離子之步驟與形成絕緣層之116步驟之間並不需進行熱趨入製程,且N型汲極摻雜區114可與P型通道摻雜區118利用同一熱趨入製程來形成。
如第6圖所示,接下來,於絕緣層116上之各穿孔104a中形成一閘極結構120。並且,閘極結構120包括一閘極絕緣層122與一
閘極導電層124,且閘極絕緣層122設於閘極導電層124與P型井區108之間。於本實施例中,形成閘極結構120之步驟可先進行一熱氧化製程,於曝露出之P型井區108之上表面以及絕緣層116上之各穿孔104a之側壁上形成一閘極絕緣層122。然後,進行另一沉積製程,於閘極絕緣層122上形成一閘極導電層124,例如:多晶矽,且閘極導電層124填滿絕緣層116上之各穿孔104a。接著,進行一研磨製程以及一回蝕刻製程,移除位於各穿孔104a外之閘極導電層124,以於各穿孔104a中形成閘極結構120。本實施例之閘極導電層124係作為溝槽型功率電晶體元件之閘極。
如第7圖所示,然後,進行一微影製程及一N型離子佈植製程,於閘極導電層124之周圍P型通道摻雜區118之上方形成一N型摻雜區,然後,再經由一熱趨入製程以於各P型通道摻雜區118上形成一N型源極摻雜區126,作為溝槽型功率電晶體元件之源極,且各N型源極摻雜區126與各P型通道摻雜區118相接觸。
如第8圖所示,接著,於閘極絕緣層122以及閘極導電層124上覆蓋一介電層128。接著,進行一微影暨蝕刻製程,於介電層128與閘極絕緣層122中形成複數個接觸洞128a,以暴露出P型磊晶層104以及N型源極摻雜區126。於本發明之其他實施例中,於形成接觸洞128a之後,另可進行另一P型離子佈植製程與另一熱趨入製程,於各接觸洞128a所曝露之P型磊晶層104中形成一P型接觸摻雜區,以降低接觸電阻,且P型接觸摻雜區與N型源極摻雜區126
與P型井區108相接觸。
如第9圖所示,隨後,於介電層128上與接觸洞128a中形成一源極金屬層130。並且,於N型基底102下形成一汲極金屬層132。於本實施例中,形成源極金屬層130與汲極金屬層132之步驟可包含進行電漿濺鍍或電子束沉積等製程,且源極金屬層130可包括鈦、氮化鈦、鋁、鎢等金屬或金屬化合物,但不限於此。至此已完成本實施例之溝槽型功率電晶體元件100。於本發明之其他實施例中,於形成源極金屬層130之前亦可先於接觸洞128a中形成接觸插塞,或先於接觸洞128a底部之P型井區108上形成一阻障層。
本發明之溝槽型功率電晶體元件及其製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形,然為了簡化說明並突顯各實施例或變化形之間的差異,下文中使用相同標號標注相同元件,並不再對重覆部分作贅述。
請參考第10圖與第11圖,且一併參考第1圖至第4圖以及第5圖至第9圖。第10圖與第11圖為本發明一第二較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖。為了方便說明起見,與第一實施例相同之部分元件將使用相同標號標註。如第1圖至第4圖所示,本實施例之製作方法於形成絕緣層之前的步驟係與第一實施例相同,因此在此不再贅述。如第10圖所示,相較於第一實施例,本實施例之製作方法係於形成絕緣
層之步驟之後另進行一熱氧化製程,以於絕緣層116上之各穿孔104a之二側壁上分別形成二氧化層134,並且在熱氧化製程中被曝露出之各N型汲極摻雜區114的矽會與氧反應,因此鄰近各穿孔104a之各N型汲極摻雜區114之一部分轉變為各氧化層134之一部分。然後,如第11圖所示,進行一濕式蝕刻製程,以移除氧化層134。值得注意的是,由於N型汲極摻雜區114係藉由植入N型離子與熱趨入製程所形成,因此在接近各穿孔104a之側壁的N型汲極摻雜區114會具有較高之摻雜濃度。本實施例係利用熱氧化製程將具有較高摻雜濃度之N型汲極摻雜區114轉變為氧化層134,接著利用蝕刻製程移除氧化層134,以移除具有較高摻雜濃度之N型汲極摻雜區114,藉此在後續形成P型通道摻雜區118之步驟中,可避免為了中和較高濃度之N型汲極摻雜區114而調高佈植P型離子之濃度,進而可有效控制P型通道摻雜區118之摻雜濃度。如第5圖至第9圖所示,由於本實施例之製作方法中形成P型通道摻雜區118之後的步驟係與第一實施例之製作方法相同,且所完成之功率電晶體元件100之結構亦相同,如第9圖所示,因此不再在此贅述。
請參考第12圖至第15圖,第12圖與第15圖為本發明一第三較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖,其中第15圖為本發明第三較佳實施例之具有超級介面之溝槽型功率電晶體元件之剖面示意圖。如第12圖所示,相較於第一實施
例,本實施例之製作方法於提供N型基底102之後,於N型基底102上形成一P型第一磊晶層202,並於P型第一磊晶層202上形成一第一硬遮罩層204。然後,圖案化第一硬遮罩層204,以曝露出P型第一磊晶層202。接著,以第一硬遮罩層204為遮罩,蝕刻P型第一磊晶層202,以於P型第一磊晶層202中形成複數個第一穿孔202a,分別貫穿P型第一磊晶層202。
如第13圖所示,接著,於各第一穿孔202a之二側的P型第一磊晶層202中分別植入複數個N型離子。於本實施例中,於P型第一磊晶層202中植入N型離子之步驟可利用一N型斜角度離子佈植製程或一N型氣相摻雜製程,但不限於此。然後,進行一熱趨入製程,於各第一穿孔202a之二側的P型第一磊晶層202中分別形成二N型汲極摻雜區114,且N型汲極摻雜區114從P型第一磊晶層202之上表面延伸至與N型基底102相接觸。藉此,N型汲極摻雜區114可與P型第一磊晶層202相接觸而形成一PN接面,亦即超級介面,從P型第一磊晶層202延伸至N型基底102,且PN接面係約略垂直N型基底102。接著,於第一硬遮罩層204上形成一絕緣材料層206,例如:氧化矽,且絕緣材料層206填滿於各第一穿孔202a中。
如第14圖所示,然後,移除位於各第一穿孔202a外之絕緣材料層206與第一硬遮罩層204,以曝露出P型第一磊晶層202,並於各第一穿孔202a中填滿絕緣層208。由於本實施例之絕緣材料層206與第一硬遮罩層204係由相同材料所構成,因此移除位於各第一穿
孔202a外之絕緣材料層206與第一硬遮罩層204之步驟可利用進行一研磨製程來完成,但本發明不以此為限。接著,於絕緣層208與P型第一磊晶層202上形成一P型第二磊晶層210。然後,於P型第二磊晶層210上形成一第二硬遮罩層212,並圖案化第二硬遮罩層212。隨後,以第二硬遮罩層212為遮罩,於P型第二磊晶層210中形成複數個第二穿孔210a,分別對應各第一穿孔202a,以曝露出絕緣層208。接著,於各第二穿孔210a之二側的P型第二磊晶層210中分別植入複數個P型離子。於本實施例中,於P型第二磊晶層210中植入P型離子之步驟可利用一P型斜角度離子佈植製程或一P型氣相摻雜製程,但不限於此。然後,進行一熱趨入製程,於各第二穿孔210a之二側的P型第二磊晶層210中分別形成二P型通道摻雜區118,且各P型通道摻雜區118從P型第二磊晶層210之上表面延伸至與各N型汲極摻雜區114相接觸。於本發明之其他實施例中,植入N型離子之步驟與形成絕緣層208之步驟之間並不需進行熱趨入製程,且N型汲極摻雜區114可與P型通道摻雜區118於同一熱趨入製程中同時形成。
如第15圖所示,接下來,移除第二硬遮罩層212,以曝露出P型第二磊晶層210之上表面。隨後,於各第二穿孔210a中形成一閘極結構120,其中閘極結構120包括一閘極絕緣層122與一閘極導電層124,且閘極絕緣層122設於閘極導電層124與P型第二磊晶層210之間,並延伸至P型第二磊晶層210上。然後,於各第二穿孔210a之二側的P型第二磊晶層210中分別形成二N型源極摻雜
區126。藉此,各P型通道摻雜區118位於各N型源極摻雜區126與各N型汲極摻雜區114之間。由於後續步驟與第一實施例相同,在此不再贅述。藉此,可完成本實施例之溝槽型功率電晶體元件200。此外,本發明之第一穿孔202a與第二穿孔210a之數量不限分別為複數個,亦可分別僅為單一個。
值得注意的是,本實施例之製作方法利用斜角度離子佈植製程或氣相摻雜製程先於P型第一磊晶層202中形成N型汲極摻雜區114,使所形成之超級介面具有平整性。藉此,可避免在直接於第一穿孔202a中填入N型磊晶層之情況下因N型磊晶層產生空隙而造成超級介面有缺陷。
綜上所述,本發明利用斜角度離子佈植製程或氣相摻雜製程於磊晶層中形成汲極摻雜區,使所形成之超級介面具有平整性。藉此,可避免在直接於磊晶層之穿孔中填入另一磊晶層之情況下因所填入之磊晶層產生空隙而造成超級介面有缺陷。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100‧‧‧溝槽型功率電晶體元件
102‧‧‧基底
104‧‧‧磊晶層
104a‧‧‧穿孔
106‧‧‧襯墊層
108‧‧‧井區
110‧‧‧第一硬遮罩層
112‧‧‧第二硬遮罩層
113‧‧‧絕緣材料層
114‧‧‧汲極摻雜區
116‧‧‧絕緣層
118‧‧‧通道摻雜區
120‧‧‧閘極結構
122‧‧‧閘極絕緣層
124‧‧‧閘極導電層
126‧‧‧源極摻雜區
128‧‧‧介電層
128a‧‧‧接觸洞
130‧‧‧源極金屬層
132‧‧‧汲極金屬層
134‧‧‧氧化層
200‧‧‧溝槽型功率電晶體元件
202‧‧‧第一磊晶層
202a‧‧‧第一穿孔
204‧‧‧第一硬遮罩層
206‧‧‧絕緣材料層
208‧‧‧絕緣層
210‧‧‧第二磊晶層
210a‧‧‧第二穿孔
第1圖至第9圖為本發明一第一較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖。
第10圖與第11圖為本發明一第二較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖。
第12圖與第15圖為本發明一第三較佳實施例之具有超級介面之溝槽型功率電晶體元件之製作方法示意圖。
100...溝槽型功率電晶體元件
102...基底
104...磊晶層
104a...穿孔
108...井區
114...汲極摻雜區
116...絕緣層
118...通道摻雜區
122...閘極絕緣層
124...閘極導電層
126...源極摻雜區
128...介電層
128a...接觸洞
130...源極金屬層
132...汲極金屬層
Claims (20)
- 一種具有超級介面之溝槽型功率電晶體元件之製作方法,包括:提供一基底,且該基底具有一第一導電類型;於該基底上形成一磊晶層,且該磊晶層具有不同於該第一導電類型之一第二導電類型;於該磊晶層中形成至少一穿孔,貫穿該磊晶層;於該穿孔之二側的該磊晶層中分別形成二汲極摻雜區,且該等汲極摻雜區從該磊晶層之上表面延伸至與該基底相接觸,其中該等汲極摻雜區具有該第一導電類型;於該穿孔中填入一絕緣層,且該絕緣層之上表面低於該磊晶層之上表面;於該絕緣層上之該穿孔之各該側的該磊晶層中分別形成一通道摻雜區,其中該等通道摻雜區具有該第二導電類型;於該絕緣層上之該穿孔中形成一閘極結構;以及於各該通道摻雜區上分別形成一源極摻雜區,且該等源極摻雜區具有該第一導電類型。
- 如請求項1所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該磊晶層之步驟與形成該穿孔之步驟之間,該製作方法另包括:於該磊晶層上依序形成一第一硬遮罩層以及一第二硬遮罩層;以及圖案化該第二硬遮罩層以及該第一硬遮罩層,以曝露出該磊晶 層。
- 如請求項2所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該磊晶層之步驟與形成該第一硬遮罩層之步驟之間,該製作方法另包括:於該磊晶層上形成一襯墊層;以及於該磊晶層中形成一井區,且該井區具有該第二導電類型。
- 如請求項2所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該絕緣層之步驟包括:於該第二硬遮罩層上形成一絕緣材料層,且該絕緣材料層填滿該穿孔;進行一研磨製程,移除位於該穿孔外之該絕緣材料層與該第二硬遮罩層;以及進行一蝕刻製程,移除該穿孔中之部分該絕緣材料層,以形成該絕緣層。
- 如請求項1所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該等汲極摻雜區之步驟包括一斜角度離子佈植製程或一氣相摻雜製程。
- 如請求項1所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中於形成該絕緣層之步驟與形成該等通道摻雜區之步驟 之間,該製作方法另包括:於該絕緣層上之該穿孔之二側壁上分別形成二氧化層,其中鄰近該穿孔之各該汲極摻雜區之一部分轉變為各該氧化層之一部分;以及進行一濕式蝕刻製程,移除該等氧化層。
- 如請求項1所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該等通道摻雜區之步驟包括一斜角度離子佈植製程或一氣相摻雜製程。
- 如請求項1所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中於形成該等通道摻雜區之步驟與形成該閘極結構之步驟之間,該製作方法另包括移除該第一硬遮罩層以及該襯墊層。
- 一種具有超級介面之溝槽型功率電晶體元件之製作方法,包括:提供一基底,且該基底具有一第一導電類型;於該基底上形成一第一磊晶層,且該第一磊晶層具有不同於該第一導電類型之一第二導電類型;於該第一磊晶層中形成至少一第一穿孔,貫穿該第一磊晶層;於該第一穿孔之二側的該第一磊晶層中分別形成二汲極摻雜區,且該等汲極摻雜區從該第一磊晶層之上表面延伸至與該基底相接觸,其中該等汲極摻雜區具有該第一導電類型;於該第一穿孔中填滿一絕緣層; 於該第一磊晶層與該絕緣層上形成一第二磊晶層,且該第二磊晶層具有該第二導電類型;於該第二磊晶層中形成至少一第二穿孔,曝露出該絕緣層;於該第二穿孔中形成一閘極結構;以及於該第二穿孔之二側的該第二磊晶層中分別形成二源極摻雜區,且該等源極摻雜區具有該第一導電類型。
- 如請求項9所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該第一磊晶層之步驟與形成該第一穿孔之步驟之間,該製作方法另包括:於該第一磊晶層上形成一硬遮罩層;以及圖案化該硬遮罩層,以曝露出該第一磊晶層。
- 如請求項10所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該絕緣層之步驟包括:於該硬遮罩層上形成一絕緣材料層,且該絕緣材料層填滿該第一穿孔;以及移除位於該第一穿孔外之該絕緣材料層與該硬遮罩層,以於該第一穿孔中形成該絕緣層。
- 如請求項9所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該等汲極摻雜區之步驟包括一斜角度離子佈植製程或一氣相摻雜製程。
- 如請求項9所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中於形成該第二穿孔之步驟與形成該閘極結構之步驟之間,該製作方法另包括於該第二穿孔之各該側之該第二磊晶層中分別形成一通道摻雜區。
- 如請求項13所述之具有超級介面之溝槽型功率電晶體元件之製作方法,其中形成該等通道摻雜區之步驟包括一斜角度離子佈植製程或一氣相摻雜製程。
- 一種具有超級介面之溝槽型功率電晶體元件,包括:一基底,具有一第一導電類型;一第一磊晶層,設於該基底上,且具有至少一穿孔,其中該第一磊晶層具有不同於該第一導電類型之一第二導電類型;至少二汲極摻雜區,設於該穿孔二側之該第一磊晶層中,且與該基底相接觸,其中該等汲極摻雜區具有該第一導電類型,該等汲極摻雜區與該第一磊晶層相接觸;一絕緣層,設於該穿孔中,且該絕緣層之上表面低於該第一磊晶層之上表面;至少二通道摻雜區,分別設於該等汲極摻雜區上之該第一磊晶層中,並分別與該等汲極摻雜區相接觸,其中該等通道摻雜區具有該第二導電類型;一閘極結構,設於該絕緣層上之該穿孔中;以及 至少二源極摻雜區,分別設於該穿孔之該等側之該第一磊晶層中,並分別與該等通道摻雜區相接觸,其中該等源極摻雜區具有該第一導電類型。
- 如請求項15所述之具有超級介面之溝槽型功率電晶體元件,另包括一井區,設於該絕緣層上之該第一磊晶層中,且具有該第二導電類型,其中該等通道摻雜區與該等源極摻雜區設於該井區中。
- 如請求項15所述之具有超級介面之溝槽型功率電晶體元件,其中該閘極結構包括一閘極導電層與一閘極絕緣層,且該閘極絕緣層設於該閘極導電層與該第一磊晶層之間。
- 一種具有超級介面之溝槽型功率電晶體元件,包括:一基底,具有一第一導電類型;一第一磊晶層,設於該基底上,且具有至少一第一穿孔,其中該第一磊晶層具有不同於該第一導電類型之一第二導電類型;至少二汲極摻雜區,設於該第一穿孔二側之該第一磊晶層中,且各該汲極摻雜區從該第一磊晶層之上表面延伸至與該基底相接觸,其中該等汲極摻雜區具有該第一導電類型,該等汲極摻雜區與該第一磊晶層相接觸;一絕緣層,填滿該第一穿孔;一第二磊晶層,設於該第一磊晶層上,並與該等汲極摻雜區相接觸,且該第二磊晶層具有至少一第二穿孔,設於該絕緣層上, 其中該第二磊晶層具有該第二導電類型;一閘極結構,設於該絕緣層上之該第二穿孔中;以及至少二源極摻雜區,分別設於該第二穿孔二側之該第二磊晶層中,其中該等源極摻雜區具有該第一導電類型。
- 如請求項18所述之具有超級介面之溝槽型功率電晶體元件,其中該閘極結構包括一閘極導電層與一閘極絕緣層,且該閘極絕緣層設於該閘極導電層與該第二磊晶層之間。
- 如請求項18所述之具有超級介面之溝槽型功率電晶體元件,另包括至少二通道摻雜區,分別設於各該汲極摻雜區與各該源極摻雜區之間的該第二磊晶層中,其中該等通道摻雜區具有該第二導電類型。
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CN103531481B (zh) * | 2013-09-30 | 2015-11-18 | 桂林斯壮微电子有限责任公司 | 基于沟槽方式的通道分压场效应管及生产方法 |
CN106158629B (zh) * | 2015-03-23 | 2019-03-19 | 北大方正集团有限公司 | Mosfet器件的制作方法 |
US10147785B2 (en) * | 2017-01-26 | 2018-12-04 | Semiconductor Components Industries, Llc | High-voltage superjunction field effect transistor |
US10608079B2 (en) * | 2018-02-06 | 2020-03-31 | General Electric Company | High energy ion implantation for junction isolation in silicon carbide devices |
CN109346523A (zh) * | 2018-09-28 | 2019-02-15 | 张帅 | 具有超级结结构的沟槽栅场效应晶体管及其制造方法 |
JP7249269B2 (ja) * | 2019-12-27 | 2023-03-30 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN113140463B (zh) * | 2021-04-02 | 2024-09-27 | 上海维安半导体有限公司 | 一种耗尽型场效应晶体管器件及其制备方法 |
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GB9826041D0 (en) * | 1998-11-28 | 1999-01-20 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and their manufacture |
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KR100731141B1 (ko) * | 2005-12-29 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 반도체소자 및 그의 제조방법 |
JP5011881B2 (ja) * | 2006-08-11 | 2012-08-29 | 株式会社デンソー | 半導体装置の製造方法 |
JP2010153622A (ja) | 2008-12-25 | 2010-07-08 | Toshiba Corp | 半導体素子 |
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JP5659558B2 (ja) * | 2010-05-20 | 2015-01-28 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
CN102244030B (zh) * | 2011-06-30 | 2014-10-15 | 中国科学院微电子研究所 | 一种绝缘体上硅二极管器件及其制造方法 |
TWI469351B (zh) | 2011-11-29 | 2015-01-11 | Anpec Electronics Corp | 具有超級介面之功率電晶體元件及其製作方法 |
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US20080160702A1 (en) * | 2006-12-28 | 2008-07-03 | Yoshito Nakazawa | Method of manufacturing semiconductor device |
TW201010058A (en) * | 2008-08-20 | 2010-03-01 | Alpha & Omega Semiconductor | Configurations and methods for manufacturing charge balanced devices |
US20110053326A1 (en) * | 2009-08-27 | 2011-03-03 | Vishay-Siliconix | Super junction trench power mosfet device fabrication |
US20110049614A1 (en) * | 2009-08-27 | 2011-03-03 | Vishay-Siliconix | Super junction trench power mosfet devices |
TWM409532U (en) * | 2011-02-15 | 2011-08-11 | Taiwan Semiconductor Co Ltd | Super junction metal-oxide semiconductor field-effect transistor structure |
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CN103187301A (zh) | 2013-07-03 |
CN103187301B (zh) | 2016-01-20 |
US20140099762A1 (en) | 2014-04-10 |
US8940607B2 (en) | 2015-01-27 |
US20130153994A1 (en) | 2013-06-20 |
TW201327686A (zh) | 2013-07-01 |
US8928070B2 (en) | 2015-01-06 |
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