TWI454811B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel that can compensate for the effects of signal lines of different lengths.

In general, flat panel displays can be classified into non-self-illuminating displays as well as self-illuminating displays. A liquid crystal display (LCD) is a type of non-self-luminous display. The self-luminous display includes a plasma display panel (PDP), a field emission display (FED), an electroluminescent (EL) display, and an organic light emitting diode display (organic light emitting diode display; OLED).

Regardless of the non-self-illuminating display and the self-illuminating display, the display panel can be generally divided into a display area and a non-display area. As shown, the non-display area 110 has at least one drive circuit 120. The driving circuit 120 can be a driving IC. The driving circuit 120 charges and discharges the pixels P ₁₁ to P _mn in the display area 140 through the signal line module 130. As shown in the figure, the signal line module 130 is coupled to the driving circuit 120 and the pixels P ₁₁ to P _{mn in} a fan-out manner.

However, the fan-out structure causes the lengths of the signal lines in the signal line module 130 to be different, thereby causing the charging and discharging speed of the pixels to be different. For example, the length of the signal line 131 is greater than the length of the signal line 133. Therefore, when the driving circuit 120 supplies the same signals to the signal lines 131 and 133, the charging/discharging speed of the pixels P ₁₁ to P _1n of the first line (vertical direction) may be slower than the third line (vertical direction). The charging/discharging speed of the pixels P ₃₁ to P _3n causes the luminances exhibited by the pixels P ₁₁ to P _{1n to} be different from those exhibited by the pixels P ₃₁ to P _3n .

The invention provides a display panel comprising a display area, a non-display area and at least one compensation module. The display area has a plurality of pixels. The non-display area is disposed outside the display area and includes a first near terminal area. The first near terminal region has a plurality of signal lines. The signal line extends toward the display area. A first driving circuit charges and discharges the pixels through the signal lines in the display area and the first near terminal area. The compensation module is coupled to one of the first signal lines of the signal line for compensating for the influence of the first signal line on the charging and discharging action. When the non-display area further includes a reverse terminal area, the compensation module is disposed in at least one of the display area and the reverse terminal area. When the signal line extends from the display area to the second near-terminal area, a second driving circuit transmits and discharges the pixels through the second near-terminal area and the signal line in the display area, and the compensation module is disposed on the display. In the area.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Figure 2 is a possible embodiment of the display panel of the present invention. As shown, the display panel 200 has a display area (Active Area; AA) 250, a non-display area, and at least one compensation module (eg, 261-272). The invention does not limit the type of display panel 200. In one possible embodiment, display panel 200 is a liquid crystal display (LCD) panel.

The display area 250 is used to present an image and has a plurality of signal lines and a plurality of pixels. For convenience of explanation, FIG. 2 only shows signal lines A to D and pixels P _A1 to P _D6 . Each pixel is coupled to a corresponding signal line. For example, pixels P _A1 ~ P _{A6 are} coupled to signal line A. Since the circuit structures in the pixels P _A1 to P _D6 are well known to those skilled in the art, they will not be described again.

In the present embodiment, the signal lines A to D are composed of a conductive material such as a metal. Further, the present invention does not limit the type of signal line. In a possible embodiment, the signal lines A to D are scan electrodes for transmitting a scan signal. In other possible embodiments, the signal lines A to D may be data electrodes or common electrodes for transmitting a data signal or a common voltage.

Areas other than the display area 250 are referred to as non-display areas. In the embodiment, the non-display area includes a near terminal area 210 and a reverse terminal area 231 to 233. The near terminal region 210 has a plurality of signal lines. For convenience of explanation, FIG. 2 shows only four signal lines A to D.

The signal lines A to D extend to the display area 250 for transmitting the driving signals provided by a driving circuit to the pixels P _A1 P P _{D6 in the} display area 250. In the present embodiment, an area having a signal line segment in which a drive signal is transmitted from a driver to a display area is referred to as a near terminal area (such as 210) of the signal line, and an area having such a signal line line segment is referred to as the signal. The reverse terminal area of the line (such as 231~233).

The driving circuit 211 in the near terminal region 210 passes through the signal lines A to D in the near terminal region 210 and the display region 250 to perform a charge and discharge operation on the pixels P _A1 to P _D6 . In this embodiment, a chip on glass (COG) integrated driving circuit 211 is used to provide driving signal sub-signal lines A to D for charging and discharging pixels P _A1 to P _A6 . action. In another possible embodiment, a Tape Automatic Bonding (TAB) and a Chip On Film (COF) integrated driving circuit 211 can be utilized to provide a driving signal sub-signal line A. ~D.

The invention does not limit the number and type of drive circuits. In a possible embodiment, when the signal lines A to D are scan electrodes, the driving circuit 211 is a scan driver for providing a plurality of scanning signals to the pixels P _A1 to P _D6 to start Perform charging or discharging action. In another possible embodiment, when the signal lines A to D are data electrodes, the driving circuit 211 is a data driver for providing a plurality of data signals to the pixels P _A1 to P _D6 to make a picture. The capacitors in the prime P _A1 ~ P _D6 store the corresponding charges.

If a signal line segment in a non-display area (such as area 210) (such as a line segment in which signal line A~D is located in area 210) is used to transmit a signal of the driving circuit to the display area (such as 250), then this non-display The area is referred to as the near terminal area of the signal line. If the non-display area (such as areas 231 to 233) does not include a signal line segment that transmits a drive signal to the display area, it is collectively referred to as the reverse terminal area of the signal line.

For example, if a scan driver supplies a scan signal to the display area only from the right side of the display area (such as area 231), then in the case of the scan electrode, the non-display area on the right side of the display area is the near terminal area of the scan electrode. Regardless of whether the scan electrode extends from the display area into the non-display area on the left side (such as area 233), the non-display area on the left side is the reverse terminal area of the scan electrode. Assuming that the scanning signal is provided to the display area by both sides of the display area, the non-display areas on both sides are the near terminal areas of the scan electrodes.

Similarly, suppose a data drive is only from the upper side of the display area (such as the area) 232) transmitting the data signal to the display area, and a scan driver transmits the scan signal to the display area only from the right side of the display area (such as area 231), and the non-display area on the upper side of the display is the near terminal area of the data electrode, and Is the counter terminal area of the scan electrode. Similarly, the non-display area on the right side of the display is the near terminal area of the scan electrode and is the reverse terminal area of the data electrode.

In this embodiment, the signal lines A to D are arranged in a fan-out manner for transmitting signals provided by the driving circuit 211 to the pixels P _A1 to P _D6 . Therefore, the lengths of the signal lines A to D are not the same. (In particular, the lengths of the line segments located in the near terminal area 210 are not the same). Since the lengths of the signal lines A~D will affect the charging and discharging speed of the pixels P _A1 to P _D6 , in order to uniformize the charging and discharging speed of the pixels on each signal line, the compensation modules 261 to 272 are coupled to the corresponding signals. Lines (such as A~D) are used to compensate for the different lengths of signal lines A~D and affect the charging and discharging action of pixels.

In this embodiment, the signal line D does not have a compensation module, and the signal line A has compensation modules 261-266, the signal line B has compensation modules 267-269, and the signal line C has compensation modules 270-272. Since the lengths of the signal lines A to D are different, different compensation levels are required for different signal lines. For example, the length of the signal line A is shorter than the signal line B, so the total compensation degree of the compensation modules 261-266 is greater than the total compensation degree of the compensation modules 267-269.

The invention does not limit the number of compensation modules on each signal line. In a possible embodiment, the number of compensation modules depends on the length of the corresponding signal line and the compensation capability of the compensation module. For example, when the compensation capability of each compensation module is the same, the shorter the signal line, the more compensation modules are needed, or the shorter signal lines, the compensation compensation is larger. Reimbursing the module, and in the longer signal line, setting a compensation module with less compensation capability.

The invention does not limit the way in which the compensation module is arranged. In a possible embodiment, each pixel on the same signal line is configured with a compensation module. For example, the pixels P _A1 ~ P _A6 on the signal line A are each configured with a compensation module (such as 261~266). In another possible embodiment, a compensation module may be configured every N pixels, as indicated by signal lines B and C. In the case of the signal line B, a compensation module is arranged every other pixel. In other embodiments, a compensation module is provided at every fixed distance.

In this embodiment, although the number of compensation modules of the signal lines B and C is the same (both have three compensation modules), the compensation capability is not the same. For example, since the length of the signal line B is shorter than the length of the signal line C, the compensation capability of the compensation modules 267-269 is greater than the compensation capability of the compensation modules 270-272, so that the signal lines B and C can be equalized. The effect of different lengths (charge and discharge speed).

In addition, the compensation capabilities of the compensation modules on the same signal line may be different, the same or partially the same. In a possible embodiment, the compensation capability of the compensation module on the same signal line may gradually decrease or gradually increase. In another possible embodiment, the compensation function of the compensation module closer to the center of the signal line is higher.

In this embodiment, the number of compensation modules of the signal lines B and C is the same, but different from the number of compensation modules coupled to the signal line A. In other embodiments, the number of compensation modules of different signal lines may be the same, different or partially the same, and the other parts are different. As long as the number of compensation modules and the compensation capacity of the compensation module are properly adjusted, different lengths can be compensated The effect of signal lines A~D.

The present invention does not limit the structure of the compensation modules 261 to 272. In this embodiment, the compensation modules 261 to 272 are capacitors C _A1 to C _{C5 , respectively} . In a possible embodiment, the capacitors C _A1 C C _C5 may be Metal-Insulator-Metal (MIM) structures or cascade metal-insulated metal structures (cascade MIM). In other possible embodiments, the partial capacitors of capacitors C _A1 -C _C5 are MIM structures, while the other capacitors are series MIM structures.

The capacitance of each capacitor can be appropriately controlled as long as the area of the metal structure of each capacitor is appropriately controlled. In this embodiment, the metal structure of each capacitor receives a voltage level. The present invention does not limit the magnitude of the voltage level, and can supply a capacitor as long as it does not affect the level of image quality.

FIG. 3A is a schematic diagram showing the possible structure of one of the compensation modules of the present invention. For convenience of explanation, FIG. 3A only shows a layout diagram of the compensation module and a part of the display area. In this embodiment, the signal lines A to D are the data electrodes DE _A to DE _{D , respectively} . The pixels P _A1 ~ P _D1 are coupled to the scan electrodes SE in addition to the data electrodes DE _A ~ DE _D , respectively. Since the structures of the pixels P _A1 to P _D1 are well known to those skilled in the art, they will not be described again.

As shown in FIG. 3A, the scan electrode SE extends in the direction D1, and the data electrode DE extends in the direction D2, wherein the direction D1 is perpendicular to the direction D2. In addition to the scan electrode SE extending in the direction D1, the scan electrode SE has an extension region 310 _A to 310 _C .

In order to compensate for the influence of the different lengths of the data electrodes DE _A ~ DE _D , the extension regions 310 _A - 310 _C extend in the direction D2 and overlap the data electrodes DE _A ~ DE _D . The capacitors C _A1 , C _{B1 ,} and C _C1 can be defined by the regions where the extension regions 310 _A to 310 _C overlap with the data electrodes DE _A to DE _C .

By controlling the size of the overlap region between the extension regions 310 _A to 310 _C and the data electrodes DE _A to DE _C , the capacitance values of the capacitors C _A1 , C _{B1 ,} and C _C1 can be controlled, and the degree of compensation can be adjusted. For example, the overlap region of the extension region 310 _A and the data electrode DE _{A is} the largest, and the overlap region between the extension region 310 _C and the data electrode DE _{C is} the smallest, so the capacitance of the capacitor C _A1 is greater than the capacitance of the capacitor C _C1 . Therefore, the compensation capability of the capacitor C _A1 is greater than the compensation capability of the capacitor C _C1 .

In addition, the present invention does not limit the shape of the extension regions 310 _A to 310 _C , and the design principle is not to damage the aperture ratio of the display region. In the present embodiment, the extension regions 310 _A to 310 _C have the same shape and are elongated. In other embodiments, the extensions 310 _A - 310 _C have different shapes and may be of any shape.

Furthermore, the present invention does not limit the types of electrodes constituting the capacitors C _A1 , C _{B1 ,} and C _C1 . In order to compensate the data electrodes DE _A to DE _C , in the present embodiment, the capacitors C _A1 , C _B1 and C _C1 are composed of the data electrodes DE _A to DE _C and the scanning electrodes SE. In other possible embodiments, the capacitors C _A1 , C _{B1 ,} and C _C1 may be formed by the data electrodes DE _A to DE _C and a compensation electrode, wherein the compensation electrode may be a common electrode or an additional electrode.

In a possible embodiment, the compensation capacitors on the same signal line may be composed of different electrode layers. For example, in the capacitor C _A1 in FIG. 3A, the data electrode DE _A and the scan electrode extension 310 _A are formed, but the same applies. Another capacitor (such as C _A2 ) that compensates for the data electrode DE _A may be located by a common electrode (not shown) and the data electrode DE _A ; and another capacitor (such as C _A3 ) that compensates the data electrode DE _A may also It consists of an additional electrode and a data electrode DE _A.

In a possible embodiment, the additionally added electrode and the scan electrode SE are formed by the same process, and the additionally added electrode has the same material as the scan electrode SE. In another possible embodiment, the additionally added electrodes and the pixel electrodes P _A1 -P _D1 are formed by the same yellow light process and have the same material as the pixel electrodes P _A1 -P _D .

The invention does not limit the voltage level of the additionally added electrode. The additional electrode may be electrically connected to the scan electrode SE or receive a common voltage (Vcom), a ground voltage (GND), and other possible voltages. The compensation effect can be achieved by appropriately designing the sizes of the capacitors C _A1 , C _{B1 ,} and C _C1 .

In other embodiments, the capacitor may be formed by a scan electrode and a compensation electrode if the effect of the different lengths of the scan electrodes in the display region is to be compensated for. The invention does not limit the type of the compensation electrode. In a possible embodiment, the compensation capacitor can be constructed by using other electrodes (such as data electrodes or common electrodes) already existing in the display area, or by additionally adding a conductive layer.

Similarly, to compensate for the effects of different lengths of the common electrode, the compensation capacitor can be formed by a common electrode and a compensation electrode (such as a scan electrode, a data electrode, or an additional electrode).

Although the capacitors C _A1 , C _{B1 ,} and C _{C1 are} disposed in the display area 250, the degree of compensation can be controlled by adjusting the size of the overlapping area. Moreover, the capacitor is designed to avoid the open area (for example, disposed under the black matrix layer of the panel), and therefore does not affect the aperture ratio of the display panel. Capacitors C _A1 , C _{B1 ,} and C _{C1 are} formed by the original electrodes (such as the data electrodes, the source electrodes, and the common electrodes), so that the use rate of the electrodes can be improved without increasing the manufacturing cost.

FIG. 3B is another schematic structural diagram of the compensation module of the present invention. For convenience of explanation, FIG. 3B only shows the structure of the capacitor C _A1 . In Fig. 3A, the capacitor C _A1 is constituted by the extension 310 _{A of the} scan electrode SE and the data electrode DE _A . However, in FIG. 3B, the capacitor C _A1 330 _A system constituted by a scanning electrode SE DE _A-extension of the electrode material. In further embodiments, the compensating device may constitute a corresponding (e.g., capacitance) data using the extension of the electrodes 330 _A and DE _A further compensation electrode (electrode of the common electrode or additionally added).

FIG. 3C is another schematic structural diagram of the compensation module of the present invention. In this embodiment, both the scan electrode SE and the data electrode DE _A have an extension region for defining a capacitor. As shown in FIG. 3C, the scan electrode SE has an extension 310 _A and the data electrode DE _A has an extension 330 _A . Capacitor C _A1 formed in the extension region 310 _A and 330 _A overlap-extension place.

In the present embodiment, the extension area 310 _A and the extension area 330 _{A have} the same shape and area, but are not intended to limit the present invention. In other embodiments, the shape of the extension 310 _A may be different from the shape of the extension 330 _A , or the area of the extension 310 _A may be different from the area of the extension 330 _A.

FIG. 3D is another schematic structural diagram of the compensation module of the present invention. In the present embodiment, the capacitor C _A1 is a serial MIM structure. As shown, the capacitor C _A1 is composed of an extension 310 _{A of the} scan electrode SE, a data electrode DE _{A ,} and a compensation electrode CE _A .

In the present embodiment, the capacitor C _A1 is located in the display area. In another possible embodiment, capacitor C _A1 may be located in the non-display area, such as in the near terminal area or in the reverse terminal area. In other embodiments, portions of capacitor C _A1 are located in the display area while other portions are located in the non-display area.

For example, the overlapping area of the extension 310 _A and the data electrode DE _A (or the data electrode DE _A and the compensation electrode CE _A ) is located in the display area, and the data electrode DE _A and the compensation electrode CE _A (or the extension area) The overlapping area of 310 _A with the data electrode DE _A ) is located in the non-display area. In other embodiments, the partial overlap region of the extension 310 _A with the data electrode DE _A (or the data electrode DE _A and the compensation electrode CE _A ) is located in the display region, and the extension 310 _A and the data electrode DE _A (or Other overlapping regions that are the data electrode DE _A and the compensation electrode CE _A ) are located in the non-display area.

In addition, the present invention does not limit the overlapping area of the extension region 310 _A with the data electrode DE _A and the data electrode DE _A and the compensation electrode CE _A . In one possible embodiment, the area of overlap region 310 _A and DE _A data electrode extending region may be equal to, less than or greater than the area of the data electrode DE _A and the overlapping area of the compensating electrode CE _A.

In order to control the voltage level of the compensation electrode CE _A , in the present embodiment, the compensation electrode CE _A has a contact hole for electrically connecting the scan electrode SE. By connecting the MIM (metal insulator metal) structure, the capacitance of the capacitor C _A1 can be increased in a limited space, thereby increasing the compensation capability.

In a possible embodiment, the material of the compensation electrode CE _A and the pixel electrode PE is a Transparent Conducting Oxide (TCO). Therefore, the compensation electrode CE _A and the pixel electrode PE can be formed by the same mask process without additional steps of the process.

In the 3D diagram, the capacitor C _A1 is composed of the extension 310 _{A of the} scan electrode SE, the data electrode DE _A and the compensation electrode CE _A , but is not intended to limit the present invention. In other possible embodiments, the capacitor C _A1 is composed of a first conductive layer, a second conductive layer and a third conductive layer, and the three conductive layers are separated from each other by an insulating layer, wherein the second conductive layer For C _A1-based compensation capacitor electrode, and the first, third conductive layer has a function of substantially all of the compensating electrode, and are located at the first side of the second conductive layer, and a second side. For example, in FIG. 3D, the data electrode DE _A and the compensation electrode CE _A are respectively located on the first side and the second side (upper and lower sides) of the scan electrode SE and are used to compensate the scan electrode SE, wherein the compensation electrode CE _A , The data electrode DE _A and the scan electrode SE are each separated by an insulating layer, and the data electrode DE _A and the compensation electrode CE _A are electrically connected through a connection hole to improve the charging time of the scan electrode due to the uneven length in the near terminal region. The problem of unevenness.

For example, if the capacitor C _{A1 is to} compensate for the influence of different lengths of the data electrodes, the second conductive layer is a data electrode. Similarly, the capacitor C _{A1 is} intended to compensate for the effects of different lengths of the scan electrode or the common electrode, and the second conductive layer is a scan electrode or a common electrode.

In a possible embodiment, the first and third conductive layers may be additionally added or electrodes that do not require compensation in the display region. For example, if the data electrode is to be compensated, the first or third conductive layer may be an electrode (such as a scan electrode or a common electrode) that does not need compensation in the display area, or an additional electrode.

If the existing electrode in the display area is used as the compensation electrode, the use of the electrode can be increased. In addition, if an additional electrode is formed by an existing process, the compensation effect can be achieved without increasing the process. For example, an additional electrode may be formed together to form one or more corresponding electrodes while forming a scan electrode, a data electrode, a common electrode, and a pixel electrode.

In a possible embodiment, one of the first and third conductive layers may The system and the pixel electrodes are formed by the same yellow light process. Furthermore, the material of one of the first and third conductive layers may be the same as the pixel electrode. In other embodiments, the first and third conductive layers may be electrically connected to a common voltage source, such as a common voltage (Vcom) or a ground voltage (GND), or the first to third conductive layers are electrically non-electrical to each other. Connected, each receiving a corresponding voltage.

Similarly, the capacitors formed by the first to third conductive layers may be disposed in the display region or the non-display region, such as in the near terminal region or the reverse terminal region. Additionally, a portion of the electrodes of at least one of the first to third conductive layers are located in the reverse terminal region. For example, the overlapping regions of the first and second conductive layers may be located in the display region, and the overlapping regions of the second and third conductive layers are located in the non-display region.

Figure 4 is another possible embodiment of the display panel of the present invention. Fig. 4 is similar to Fig. 2, except that the compensation modules 261 to 272 of Fig. 2 are disposed in the display area 250, and the compensation modules 461 to 463 of Fig. 4 are disposed in the non-display area. The reverse terminal area 432 is connected to the tail end of the corresponding signal line A~C.

In this embodiment, the compensation modules 461-463 are respectively capacitors C _A to C _C , one end of which is respectively coupled to the signal lines A to C, and the other end receives a voltage level V _CM . In one possible embodiment, the voltage level V _CM is the same as the level of the scan electrodes in display area 450, but is not intended to limit the invention. In other embodiments, the voltage level V _{CM is} different from the level of the scan electrodes.

In addition, while making a pixel electrode (such as the PE of FIG. 3D) in the display area 450, a compensation electrode (such as CE _{A of} FIG. 3D) can be formed. Therefore, the formation of the compensation electrode does not increase the manufacturing step. In the present embodiment, the overlapping regions of the compensation electrode and the signal lines A to C have capacitors 461 to 463. By controlling the voltage levels of the compensation electrode and the signal lines A to C, the capacitors C _A to C _C can be compensated.

When the space of the display area 250 is insufficient, the compensation modules 461 to 463 may be disposed in at least one of the opposite terminal areas 431 to 433. Furthermore, since the reverse terminal regions 431 to 433 are not provided with a driving circuit, a large space can be used, and a capacitor having a large capacitance can be designed.

The invention does not limit the installation position of the compensation module. In a possible embodiment, not only the anti-terminal area 432 has compensation modules 461-463, but the display area 450 also has a compensation module. In addition, if both ends of a signal line extend into the non-display area and are connected to the driving circuit (ie, the non-display area on both sides of the signal line is a near terminal area), the compensation module coupled to the signal line is coupled. It is only disposed in the display area 450. In other possible embodiments, in addition to the display area 450 and the reverse terminal areas 431 433 433 , a compensation module may also be disposed in the near terminal area 410 .

Since the setting position of the compensation module is quite flexible, a higher compensation efficiency can be achieved, and the influence of the signal lines of different lengths (the charging and discharging time of the pixels) can be uniformized. In addition, in other embodiments, when the compensation module is sufficient to homogenize the problem caused by the signal lines of different lengths, the signal line can adopt a sheet-like structure without using a serpentine (z-shaped) structure, so the reduction can be reduced. The area of the substrate occupied by the signal line can narrow the border of the near terminal areas 210 and 410.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 400‧‧‧ display panels

110‧‧‧Non-display area

120, 211, 411‧‧‧ drive circuit

130‧‧‧Signal Line Module

131, 133, A~D‧‧‧ signal lines

140, 250, 450‧‧‧ display area

210, 410‧‧‧ Near terminal area

231~233, 431~433‧‧‧anti-terminal area

261~272, 461~463‧‧‧compensation module

310 _A ~310 _C , 330 _A ‧‧‧Extension

P ₁₁ ~P _mn , P _A1 ~P _D6 ‧‧‧ pixels

C _A1 ~ C _C5 , C _A ~ C _C ‧ ‧ capacitor

SE, DE _A ~DE _D , PE, CE _A ‧‧‧electrode

Figure 1 is a schematic view of a conventional display panel.

2 and 4 are possible embodiments of the display panel of the present invention.

3A~3D are schematic diagrams of possible structures of one of the compensation modules of the present invention.

200‧‧‧ display panel

210‧‧‧ Near terminal area

211‧‧‧ drive circuit

231~233‧‧‧Anti-terminal area

250‧‧‧ display area

261~272‧‧‧compensation module

A~D‧‧‧ signal line

C _A1 ~ C _C5 ‧‧‧ capacitor

P _A1 ~P _D6 ‧‧‧ pixels

Claims (20)

A display panel includes: a display area having a plurality of pixels; a non-display area disposed outside the display area and including a first near terminal area, the first near terminal area having a plurality of signal lines, and the like The signal line extends toward the display area, and a first driving circuit transmits a charging and discharging action to the pixels through the first near-terminal area and the signal lines in the display area; and at least one compensation module coupled And connecting one of the signal lines to compensate for the influence of the first signal line on the charging and discharging action; wherein when the non-display area further includes an anti-terminal area, the compensation module is disposed at And at least one of the display area and the reverse terminal area, when the signal lines extend from the display area to a second near terminal area, a second driving circuit transmits the second near terminal area and the display area The signal lines therein perform the charging and discharging operation on the pixels, and the compensation module is disposed in the display area. The display panel of claim 1, wherein the compensation module is connected between the first signal line and a compensation electrode. The display panel of claim 2, wherein the first signal line is a data electrode, and the compensation electrode is a scan electrode. The display panel of claim 2, wherein the first signal line is a data electrode, and the compensation electrode is a common electrode. The display panel of claim 2, wherein the first signal line is a scan electrode, and the compensation electrode is a data electrode. The display panel of claim 2, wherein the display area further comprises a plurality of pixel electrodes, and the material of the pixel electrodes and the compensation electrode are both a Transparent Conducting Oxide (TCO). And the pixel electrodes and the compensation electrode are insulated from each other. The display panel of claim 1, wherein the compensation module comprises a first conductive layer disposed on a first side of the first signal line, and a second conductive layer disposed on the first signal One of the second sides of the line. The display panel of claim 7, wherein the first conductive layer is electrically connected to the second conductive layer. The display panel of claim 7, wherein the display area further comprises a plurality of pixel electrodes, and the pixel electrodes and the first conductive layer are formed by the same yellow light process. The display panel of claim 1, the compensation module includes a first capacitor and a second capacitor, the first capacitor is composed of a first compensation electrode and the first signal line, the first The two capacitors are composed of the first signal line and a second compensation electrode. The display panel of claim 10, wherein a capacitance of the first capacitor is different from a capacitance of the second capacitor. The display panel of claim 10, wherein the first and second compensation electrodes are electrically connected. The display panel of claim 12, wherein the first capacitor is located in the non-display area, and the second capacitor is located in the display area. The display panel of claim 13, wherein the first capacitor is located in the opposite terminal region. The display panel of claim 10, wherein a portion of at least one of the first compensation electrode and the second compensation electrode is located in a reverse terminal region. The display panel of claim 10, wherein the display area further comprises a plurality of pixel electrodes, and the first compensation electrode and the pixel electrodes are formed by the same yellow light process. The display panel of claim 16, wherein the first compensation electrode and the pixel electrodes are made of the same material. The display panel of claim 16, wherein the first signal line is a data electrode, the second compensation electrode is a scan electrode, and the first compensation electrode material is the same material as the pixel electrodes. . The display panel of claim 18, wherein the first compensation electrode is located in the non-display area. The display panel of claim 19, wherein the first compensation electrode is located in the opposite terminal region.