TWI447851B - Multilayer connection structure and making method - Google Patents

Description

Multi-layer connection structure and manufacturing method

SUMMARY OF THE INVENTION The present invention is generally directed to a high density integrated circuit device, and more particularly to an interconnect structure for a multilayer three dimensional stacked device.

In the manufacture of high-density memory devices, the amount of data per unit area on an integrated circuit can be a key factor. Therefore, when the critical size of the memory device reaches the limit of the lithography technology, a technique for stacking a plurality of memory cells has been proposed in order to achieve higher storage density and lower cost per bit.

For example, in Lai et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, and Jung et al. "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, the application of thin film transistor technology Charge trapping memory.

In addition, in Johnson et al., "512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells", IEEE J. of Solid-State Circuits, vol. 38, no. 11, Nov. 2003 Among them, cross-point array technology has been applied to anti-fuse memory. At the same time, reference is made to the case of Cleeves, entitled "Three-Dimensional Memory", U.S. Patent No. 7,081,377.

Another structure that provides a vertical inverse (NAND) cell in charge trapping memory technology is described in Kim et al., "Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE", 2008 Symposium on VLSI Technology Digest of Technical Papers; 17-19 June 2008; pages 122-123 in the literature.

In a three-dimensional stacked memory device, conductive interconnects pass through the upper layer of the memory cell to couple the lower layer of the memory cell to the decoding circuit and its similar circuitry. The cost of implementing interconnects will increase with the number of lithographic steps required. A method for reducing the number of lithography steps is described in Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 June 2007, Pages: 14-15 in the literature.

However, one of the disadvantages of conventional three-dimensional stacked memory devices is that separate masks are typically used for each contact layer. Thus, if there are, for example, 20 contact layers, typically 20 different masks are required, each of which requires the creation of a mask for this layer, as well as an etching step for this layer.

An example of a method for a three-dimensional stacked integrated circuit device having a stack of at least four contact layers in an interconnect region for generating a plurality of interconnect contact regions, the interconnect contact regions Aligning with a plurality of landing areas of the contact layers and exposing the landing areas to the contact layers. Each of the contact layers includes a conductive layer and an insulating layer. At least a portion of any of the upper layers disposed on the interconnect region is removed to expose a first contact layer and create contact openings for each of the contact layers. A set of N etch masks are selected to generate a plurality of interconnect contact layer layers at the stack of the contact layers, N being an integer at least equal to two. The N etch masks are used to etch the contact openings up to and including 2 N-th contact layers. The N mask use steps include using a first mask to etch one of the contact layers for the effective half of the contact openings and using a second mask to etch two for the effective half of the contact openings These contact layers. The removing, the selecting, and the using step are performed such that the contact openings extend to the 2 N-th contact layers. A plurality of electrical conductors are formed through the contact openings to contact the landing regions of the contact layers. In some examples, the removal step is performed using an additional mask. In some examples, the first mask using step includes etching the contact layer with every other one of the contact openings using the first mask, and the second mask using step includes using the second mask to at least one The third and fourth contact openings of the first to fourth of the set of contact openings etch two of the contact layers. In some examples, the N masking steps further include using a third mask to etch four of the contact layers for the effective half of the contact openings, and using a fourth mask to effectively Half of the contact openings etch eight of the contact layers. In some examples, the third mask using step includes etching the four contact layers by using the third mask to the fifth to the eighth contact openings of the at least one of the first to eighth contact openings And the fourth mask using step includes etching the eight contact layers using the fourth mask to the ninth to the sixteenth contact openings of the at least one of the first to sixteenth contact openings. In some examples, a ground contact opening is formed through the contact layers, and a ground conductor is formed through the ground contact opening to electrically contact a plurality of the conductive layers of the contact layers. In some examples, the ground contact opening has a ground contact opening sidewall and is removed from a portion of the insulating layer sidewall of the ground contact opening before the ground conductor forming step, so the ground conductor enhances the ground conductor Electrical contact with a plurality of the conductive layers of the contact layers.

Another example of a method for a three-dimensional stacked integrated circuit device provides a plurality of plurality of landing regions electrically coupled to a stack of a plurality of contact layers located within the interconnect region. The integrated circuit device is of a type including an interconnect region. The interconnect region includes an upper layer having a stack of the contact layers under the upper layer. Each of the contact layers includes a conductive layer and an insulating layer. At least a portion of any of the upper layers disposed on the interconnect region is removed to expose a first contact layer and create contact openings for each of the contact layers. A set of N etch masks are selected to create a plurality of interconnect contact layer layers at the stack of the contact layers, N being an integer at least equal to two. The N etch masks are used to etch the contact openings up to and including 2 N-th contact layers. The N mask use steps include using a first mask to etch one of the contact openings for the effective half of the contact openings, and using a second mask to etch two for the effective half of the contact openings These contact layers. The removing, the selecting, and the using step are performed such that the contact openings extend to the 2 N-th contact layers. A dielectric layer is formed on the plurality of sidewalls. Forming a plurality of electrical conductors through the contact openings to the landing regions of the contact layers, the dielectric layers electrically insulating the electrical conductors to the sidewalls. In some examples, a ground contact opening is formed through the contact layers, and a ground conductor is formed through the ground contact opening to electrically contact a plurality of the conductive layers of the contact layers. In some examples, the ground contact opening has a ground contact opening sidewall, and the portion of the insulating layer removed from the sidewall of the ground contact opening is adjacent to the ground contact opening before the ground conductor forming step Portions of the plurality of conductive layers are exposed such that the ground conductor enhances electrical contact with a plurality of the conductive layers.

A first example of a three-dimensional stacked integrated circuit device includes at least one of the first, second, third, and fourth contact layers stacked in an interconnect region. Each of the contact layers includes a conductive layer and an insulating layer. The first, second, third, and fourth electrical conductors pass through a portion of the stack of contact layers. The first, second, third, and fourth conductive systems are in electrical contact with the first, second, third, and fourth conductive layers, respectively. A dielectric sidewall spacer surrounds the second, third, and fourth electrical conductors such that the second, third, and fourth electrical conductors only electrically contact the respective second, third, and fourth conductive layers . In some examples, the first, second, third, and fourth electrical conductors have a constant spacing. In some examples, the locations of the first, second, third, and fourth electrical conductors are determined by a common mask. In some examples, the stacked integrated circuit device further includes a portion of the grounding conductor passing through the stack of the contact layers, the grounding conductor electrically contacting the first, second, third, and fourth conductive portions. Floor.

A second example of a three-dimensional stacked integrated circuit device includes at least one of the first, second, third, and fourth contact layers stacked in an interconnect region. Each of the contact layers includes a conductive layer and an insulating layer. The first, second, third, and fourth electrical conductors pass through portions of the stack of the contact layers. The first, second, third, and fourth conductive systems are in electrical contact with the first, second, third, and fourth conductive layers, respectively. The first, second, third and fourth electrical conductors have a constant spacing. In some examples, the locations of the first, second, third, and fourth electrical conductors are determined by a common mask.

A third example of a three-dimensional stacked integrated circuit device includes at least one of the first, second, third, and fourth contact layers stacked in an interconnect region. Each of the contact layers includes a conductive layer and an insulating layer. The first, second, third, and fourth electrical conductors pass through portions of the stack of the contact layers. The first, second, third, and fourth conductive systems are in electrical contact with the first, second, third, and fourth conductive layers, respectively. A dielectric sidewall spacer surrounds the second, third, and fourth electrical conductors such that the second, third, and fourth electrical conductors only electrically contact the respective second, third, and fourth conductive layers . A grounding conductor passes through portions of the stack of the contact layers and electrically contacts the first, second, third, and fourth conductive layers. The first, second, third and fourth electrical conductors have a constant spacing. The positions of the first, second, third, and fourth electrical conductors and the grounding conductor are determined by a common mask.

Other aspects and advantages of the present invention are described with reference to the drawings, the embodiments, and the appended claims.

1 is a cross-sectional view of a device including a three-dimensional structure having an interconnect structure 190 having a small footprint, wherein the electrical conductor 180 extends to different contact layers 160-1 in the device. To 160-4. In the example shown, there are four contact layers 160-1 through 160-4. In general, the small interconnect structure 190 described herein can be implemented with a structure having contact layers 0 through N and N at least 2.

Electrical conductors 180 are disposed within interconnect structure 190 to contact landing areas on different contact layers 160-1 through 160-4. As described in more detail below, the electrical conductors 180 for each particular layer extend through openings in the layers disposed above to contact the landing regions 161-1a, 161-1b, 161-2a, 161-2b, 161- 3a, 161-3b, 161-4. In this example, the electrical conductors 180 are interconnects 185 for coupling the contact layers 160-1 through 160-4 into the wire layers, and the wire layers are disposed over the contact layers 160-1 through 160-4.

The landing area is part of the contact layers 160-1 to 160-4 for contact with the electrical conductor 180. The size of the landing zone is large enough to provide space to the electrical conductor 180 such that the electrical conductor 180 adequately couples the electrically conductive landing zone in the landing zone of the different contact layers 160-1 to 160-4 to the interconnecting line disposed above 185, simultaneously solving the problem of misalignment between the conductor 180 and the opening for the landing area disposed above one of the layers, for example, in different layers.

The size of the landing zone therefore depends on several factors, including the size and number of electrical conductors used, and will vary with various embodiments. Moreover, the number of electrical conductors 180 can vary for each landing zone.

In the illustrated example, contact layers 160-1 through 160-4 are comprised of respective planar conductive layers of material, such as doped polysilicon, with separate contact layers 160-1 through 160-4. Insulating material 165. Alternatively, the contact layers 160-1 through 160-4 need not be a layer of material that is planarly stacked, but rather a layer of material that can vary along the vertical dimension.

The conductors 180 contacting the different contact layers 160-1 to 160-4 are arranged along the direction in which the cross-section extends as shown in FIG. 1A. The direction defined by this arrangement of conductors 180 contacting different contact layers 160-1 through 160-4 is referred to herein as the "longitudinal" direction. The "lateral" direction is perpendicular to the longitudinal direction and is the paper feed surface and the paper exit surface direction of the cross section as shown in Fig. 1A. Both the longitudinal and lateral directions are considered to be "lateral dimensions", meaning the direction in the two-dimensional region of the plan view of the contact layers 160-1 to 160-4. The "length" or characteristic of the structure is its length in the longitudinal direction, and the "width" of the structure is its width in the lateral direction.

The contact layer 160-1 is the lowest of the plurality of contact layers 160-1 to 160-1. Contact layer 160-1 is over insulating layer 164.

The contact layer 160-1 includes first and second landing regions 161-1a, 161-1b for contacting the electrical conductor 180.

In FIG. 1, the contact layer 160-1 includes two landing areas 161-1a, 161-1b on opposite ends of the interconnect structure 190. In some other embodiments, one of the landing zones 161-1a, 161-1b is omitted.

FIG. 2A is a plan view showing a portion of the contact layer 160-1 including the landing regions 161-1a, 161-1b within the bottom area of the interconnect structure 190. The bottom area of the interconnect structure 190 can be close to the width of the via size for the electrical conductor and has a length that is longer than this width. As shown in FIG. 2A, the landing area 161-1a has a width 200 in the lateral direction and a length 201 in the longitudinal direction. The landing area 161-1b has a width 202 along the lateral direction and a length 203 along the longitudinal direction. In the embodiment of Fig. 2A, the landing areas 161-1a, 161-1b each have a rectangular cross section. In an embodiment, the landing areas 161-1a, 161-1b may each have a circular, elliptical, square, rectangular or some irregularly shaped cross section.

Since the contact layer 160-1 is the lowest contact layer, the conductor 180 does not need to pass through the contact layer 160-1 to the layer disposed below. Thus, in this example, contact layer 160-1 does not have an opening within inner interconnect structure 190.

Referring back to FIG. 1, the contact layer 160-2 is disposed above the contact layer 160-1. The contact layer 160-2 includes an opening 250 disposed above the landing region 161-1a on the contact layer 160-1. The opening 250 has a distal longitudinal side wall 251a and a proximal longitudinal side wall 251b defining a length 252 of the opening 250. The length 252 of the opening 250 is at least as long as the length 201 of the landing region 161-1a disposed below, such that the electrical conductor 180 for the landing region 161-1a can pass through the contact layer 160-2.

The contact layer 160-2 also includes an opening 255 disposed above the landing region 161-1b. The opening 255 has distal and proximal longitudinal side walls 256a, 256b defining a length 257 of the opening 255. The length 257 of the opening 255 is at least as long as the length 203 of the landing region 161-1b disposed below, such that the electrical conductor 180 for the landing region 161-1b can pass through the contact layer 160-2.

Contact layer 160-2 also includes first and second landing regions 161-2a, 161-2b that are adjacent to openings 250, 255, respectively. The first and second landing regions 161-2a, 161-2b are portions of the contact layer 160-2 for contacting the electrical conductor 180.

2B illustrates a plan view of a portion of contact layer 160-2, including first and second landing regions 161-2a, 161-2b and openings 250, 255 within interconnect structure 190.

As shown in FIG. 2B, the opening 250 has longitudinal side walls 251a, 251b defining a length 252 of the opening 250 and having lateral side walls 253a, 253b defining a width 254 of the opening 250. The width 254 is at least as wide as the width 200 of the landing region 161-1a disposed below, such that the electrical conductor 180 can pass through the opening 250.

The opening 255 has longitudinal side walls 256a, 256b defining a length 257 and having lateral side walls 258a, 258b defining a width 259. The width 259 is at least as wide as the width 202 of the landing region 161-1b disposed below, such that the electrical conductor 180 can pass through the opening 255.

In the plan view of Fig. 2B, the openings 250, 255 each have a rectangular cross section. In an embodiment, the openings 250, 255 may each have a circular, elliptical, square, rectangular or somewhat irregular cross-section depending on the shape of the mask used to form the openings.

As shown in FIG. 2B, the landing area 161-2a is adjacent to the opening 250 and has a width 204 in the lateral direction and a length 205 in the longitudinal direction. The landing area 161-2b is adjacent to the opening 255 and has a width 206 in the lateral direction and a length 207 in the longitudinal direction.

Referring back to Figure 1, contact layer 160-3 is disposed over contact layer 160-2. The contact layer 160-3 includes an opening 260 disposed above the landing region 161-1a on the contact layer 160-1 and the landing region 161-2a on the contact layer 160-2. The opening 260 has distal and proximal longitudinal side walls 261a, 261b defining a length 262 of the opening 260. The length 262 of the opening 260 is at least as long as the sum of the lengths 201 and 205 of the landing regions 161-1a and 161-2a disposed below, such that the conductors 180 for the landing regions 161-1a and 161-2a can pass through the contacts. Layer 160-3.

As shown in FIG. 1, the distal longitudinal side wall 261a of the opening 260 is vertically aligned with the distal longitudinal side wall 251a of the opening 250 disposed below. In a fabrication embodiment, described in more detail below, the opening in a single etch mask and an additional mask formed in the opening in the single etch mask can be used, as well as the process for etching the additional mask. The openings are formed without critical alignment steps, thereby resulting in openings having distal longitudinal sidewalls (261a, 251a, ...) formed along the perimeter of the vertically aligned single etch mask.

The contact layer 160-3 also includes an opening 265 disposed above the landing region 161-1b on the contact layer 160-1 and the landing region 161-2b on the contact layer 160-2. The opening 265 has outer and inner longitudinal side walls 266a, 266b defining a length 267 of the opening 265. The outer side longitudinal side wall 266a of the opening 265 is vertically aligned with the outer side longitudinal side wall 256a of the opening 255 provided below.

The length 267 of the opening 265 is at least as long as the sum of the lengths 203 and 207 of the landing regions 161-1b and 161-2b disposed below, so that the conductors 180 for the landing regions 161-1b and 161-2b can pass through the contacts. Layer 160-3.

Contact layer 160-3 also includes first and second landing regions 161-3a, 161-3b that are adjacent to openings 260, 265, respectively. The first and second landing areas 161-3a, 161-3b are portions of the contact layer 160-3 for contact with the conductor 180.

2C illustrates a plan view of a portion of contact layer 160-3, including first and second landing regions 161-3a, 161-3b and openings 260, 265 within interconnect structure 190.

As shown in FIG. 2C, the opening 260 has outer and inner longitudinal side walls 261a, 261b defining a length 262 of the opening 260 and having lateral side walls 263a, 263b defining a width 264a, 264b of the opening 260. The width 264a is at least as wide as the width 200 of the landing region 161-1a disposed below, and the width 264b is at least as wide as the width 204 of the landing region 161-2a disposed below, such that the electrical conductor 180 can pass through the opening 260.

In the illustrated embodiment, the widths 264a and 264b are substantially identical. Alternatively, the widths 264a and 264b may be different to accommodate landing areas having different widths.

The opening 265 has longitudinal side walls 266a, 266b defining a length 267 and having lateral side walls 268a, 268b defining a width 269a, 269b. The width 269a is at least as wide as the width 202 of the landing region 161-1b disposed below, and the width 269b is at least as wide as the width 206 of the landing region 161-2b disposed below, such that the electrical conductor 180 can pass through the opening 265.

As shown in FIG. 2C, the landing area 161-3a is adjacent to the opening 260 and has a width 214 in the lateral direction and a length 215 in the longitudinal direction. The landing area 161-3b is adjacent to the opening 265 and has a width 216 in the lateral direction and a length 217 in the longitudinal direction.

Referring back to Figure 1, contact layer 160-4 is disposed over contact layer 160-3. The contact layer 160-4 includes a landing region 161-1a disposed on the contact layer 160-1, a landing region 161-2a on the contact layer 160-2, and an opening above the landing region 161-3a on the contact layer 160-3. 270. The opening 270 has longitudinal side walls 271a, 271b defining a length 272 of the opening 270. The length 272 of the opening 270 is at least as long as the sum of the lengths 201, 205, and 215 of the landing areas 161-1a, 161-2a, and 161-3a disposed below, such that the landing areas 161-1a, 161-2a, and 161 are used. Conductor 180 of -3a can pass through contact layer 160-4. As shown in FIG. 1, the longitudinal side wall 271a of the opening 270 is vertically aligned with the longitudinal side wall 261a of the opening 260 provided below.

The contact layer 160-4 also includes a landing region 161-1b disposed on the contact layer 160-1, a landing region 161-2b on the contact layer 160-2, and a landing region 161-3b on the contact layer 160-3. Opening 275. The opening 275 has longitudinal side walls 276a, 276b defining a length 277 of the opening 275. The longitudinal side wall 276a of the opening 275 is vertically aligned with the longitudinal side wall 266a of the opening 265 disposed below.

The length 277 of the opening 275 is at least as long as the sum of the lengths 203, 207, and 217 of the landing areas 161-1b, 161-2b, and 161-3b disposed below, such that the landing areas 161-1b, 161-2b, and 161 are used. Conductor 180 of -3b can pass through contact layer 160-4.

Contact layer 160-4 also includes landing area 161-4 between openings 270,275. The landing zone 161-4 is part of the contact layer 160-4 for contact with the electrical conductor 180. In Fig. 1, the contact layer 160-4 has a landing area 161-4. Alternatively, contact layer 160-4 can include more than one landing area.

2D illustrates a plan view of a portion of contact layer 160-4, including landing regions 161-4a and openings 270, 275 within interconnect structure 190.

As shown in Fig. 2D, opening 270 has longitudinal side walls 271a, 271b defining a length 272 of opening 270 and having lateral side walls 273a, 273b defining a width 274a, 274b, 274c of opening 270. The widths 274a, 274b, 274c are at least as wide as the widths 200, 204, and 214 of the landing regions 161-1a, 161-2a, and 161-3a disposed below so that the electrical conductor 180 can pass through the opening 270.

The opening 275 has longitudinal side walls 276a, 276b defining a length 277 and having lateral side walls 278a, 278b defining a width 279a, 279b, 279c. The widths 279a, 279b, 279c are at least as wide as the widths 202, 206, and 216 of the landing regions 161-1b, 161-2b, and 161-3b disposed below so that the electrical conductor 180 can pass through the opening 275.

As shown in FIG. 2D, the landing area 161-4 is located between the openings 270, 275 and has a width 224 in the lateral direction and a length 225 in the longitudinal direction.

Referring back to FIG. 1, the distal longitudinal sidewalls 271a, 261a, and 251a of the openings 270, 260, and 250 are vertically aligned such that the openings 270, 260, and 250 differ in length due to the sidewalls 271b, 261b and The horizontal offset of 251b. As used herein, a component or feature "vertically aligned" is substantially flush with an imaginary plane that is perpendicular to both the lateral and longitudinal directions. The term "substantially flush" as used herein is intended to encompass manufacturing tolerances in the formation of openings wherein the opening is formed using openings in a single etched mask and the planarity of the sidewalls is utilized. Multiple etching treatment of variations.

As shown in Figure 1, the longitudinal side walls 276a, 266a and 256a of the openings 275, 265 and 255 are vertically aligned.

Similarly, the lateral sidewalls of the openings in the layer are also vertically aligned. Referring to Figures 2A through 2D, the lateral sidewalls 273a, 263a, and 253a of the openings 270, 260, and 250 are vertically aligned. Further, the lateral side walls 273b, 263b, and 253b are vertically aligned. For openings 275, 265, and 255, longitudinal sidewalls 276a, 266a, and 256a are vertically aligned, and lateral sidewalls 278b, 268b, and 258b are vertically aligned.

In the illustrated embodiment, the openings in the different contact layers 160-1 through 160-4 have substantially the same width in the lateral direction. Alternatively, to accommodate landing areas having different widths, the width of the opening may vary along the longitudinal direction, such as in a step-like fashion.

This technique for implementing the interconnect structure 190 as described herein can significantly reduce the area required for contact with the plurality of contact layers 160-1 through 160-4 or the prior art techniques The footprint. Therefore, there is more space in the different contact layers 160-1 to 160-4 to implement the memory circuit. This allows for a higher memory density and a lower cost per bit in the upper layer than in prior art techniques.

In the cross-sectional view of Figure 1, the openings in the interconnect structure 190 result in layers having similar step patterns on both sides of the landing region 161-4 on the contact layer 160-4. That is, the two openings in each layer are symmetrical about an axis perpendicular to the longitudinal direction and the lateral direction, and the two landing areas of the layers are also symmetrical about the axis. As used herein, the term "symmetric" is intended to encompass the manufacturing tolerances in the formation of openings that are formed using a single etched opening in the mask and using multiple etch processes that can cause variations in the dimensions of the opening. .

In other embodiments, each layer includes a single opening and a single landing zone that has a similar step pattern on only one side.

In the example shown, four contact layers 160-1 through 160-4 are shown. More generally, the small interconnect structure described herein can be implemented in layers 0 through N, where N is at least 2. In general, layer (i) is disposed above layer (i-1), wherein (i) is equal to 1 to N, and layer (i) has an opening adjacent to landing region (i) on layer (i) (i). The opening (i) extends above the landing zone (i-1) on the layer (i-1), and when (i) is greater than 1, the opening (i) extends beyond the adjacent opening of the layer (i-1) Above i-1). The opening (i) has a distal longitudinal side wall aligned with the distal longitudinal side wall of the opening (i-1) in layer (i) and has a proximal longitudinal side wall defining the length of the opening (i). The length of the opening (i), if any, is at least as long as the length of the landing zone (i-1) plus the length of the opening (i-1). When (i) is greater than 1, the opening (i) has a lateral side wall aligned with the lateral side wall of the opening (i-1) in the layer (i-1), and defines the width of the opening (i) at least with the landing area (i) -1) The width is the same width.

Other types of memory cells and configurations can be used in other embodiments. Other types of memory cells that can be used include, for example, dielectric charge trapping and floating gate memory cells. For example, in a layer of another device, a planar memory cell array separated by an insulating material can be implemented, and a thin film transistor or related technology is used within the layer to form an access device and an access line. Moreover, the interconnect structure described herein can be practiced with other types of three-dimensional stacked integrated circuit devices, wherein it is advantageous to have electrical conductors that extend into different layers in the device in a small bottom area.

3A is a cross-sectional view of a portion of a three-dimensional stacked integrated circuit device 100 that includes a memory array region 110 and a surrounding region 120 having an interconnect structure 190 as described herein.

In FIG. 3A, the memory array region 110 is implemented as a one-time programmable multi-layer memory cell as described in U.S. Patent Application Serial No. 12/430,290, the disclosure of which is assigned to Co-owned and used here as a reference. The integrated circuit structure described herein as being representative can be implemented in the three-dimensional interconnect structure described herein.

The memory array region 110 includes a memory cell access layer 112, and the memory cell access layer 112 includes horizontal field effect transistor access devices 131a, 131b. The horizontal field effect transistor access devices 131a, 131b have a source in the semiconductor substrate 130. Polar regions 132a, 132b and drain regions 134a, 134b. The substrate 130 may include a bulk silicon or a germanium layer on the insulating layer or other conventional structure for supporting the integrated circuit. The trench isolation structures 135a, 135b isolate regions in the substrate 130. The word lines (WL) 140a, 140b function as gates of the access devices 131a, 131b. Contact plugs 142a, 142b extend through the interlayer dielectric 144 to couple the drain regions 134a, 134b to the bit lines (BL) 150a, 150b.

Contact pads 152a, 152b are coupled to contact windows 146a, 146b disposed below and provide source regions 132a, 132b that are coupled to the access transistor. Contact pads 152a, 152b and bit lines 150a, 150b are located within interlayer dielectric 154.

In the illustrated example, the contact layers are comprised of respective planar conductive layers of material, such as doped polysilicon. Alternatively, such contact layers need not be a layer of material that is planarly stacked, but rather a layer of material that can vary along the vertical dimension.

The insulating layers 165-1 to 165-3 separate the contact layers 160-1 to 160-4 one by one. The insulating layer 166 is disposed over the contact layers 160-1 to 160-4 and the insulating layers 165-1 to 165-3.

A plurality of electrode pillars 171a, 171b are arranged on top of the memory cell access layer 112 and extend through the contact layers. In this figure, the first electrode post 171a includes a central conductive core layer 170a made, for example, of tungsten or other suitable electrode material, and surrounded by a polysilicon cap layer 172a. An antifuse material layer 174a, or other layer of programmable memory material, is formed between the polysilicon cap layer 172a and the plurality of contact layers 160-1 through 160-4. In this example, contact layers 160-1 through 160-4 include relatively highly doped n-type polysilicon, while polysilicon cap layer 172a includes relatively lightly doped p-type polysilicon. Preferably, the thickness of the polysilicon cap layer 172a is greater than the depth of the depletion region formed by the p-n junction. The depth of the depletion zone is determined in part by the relative doping concentration of the n-type and p-type polysilicon used to form the depletion zone. Contact layers 160-1 to 160-4 and cover layer 172a can also be implemented using amorphous germanium. In addition, other semiconducting materials can also be used.

The first electrode post 171a is coupled to the contact pad 152a. The second electrode post 171b includes a conductive core layer 170b, a polysilicon cap layer 172b, and an antifuse material layer 174b coupled to the contact pad 152b.

The interface region between the plurality of contact layers 160-1 to 160-4 and the electrode posts 171a, 171b includes a memory element including a programmable element in series with the rectifier, as will be explained in more detail below.

In the native state, the antifuse material layer 174a of the electrode post 171a has a high electrical resistance, and the antifuse material layer 174a may be cerium oxide, cerium oxynitride or other cerium oxide. Other antifuse materials such as tantalum nitride can be used. After being programmed by applying appropriate voltages to word line 140, bit line 150, and a plurality of contact layers 160-1 through 160-4, antifuse material layer 174a collapses and is adjacent to a corresponding layer. The active region within the anti-fuse material exhibits a low resistance state.

As shown in FIG. 3A, the plurality of conductive layers of the contact layers 160-1 through 160-4 extend into the peripheral region 120, where the circuitry for connecting to the plurality of contact layers 160-1 through 160-4 is supported and conductive. Body 180. Various devices are implemented in the surrounding area 120 to support the decoding logic and other circuits on the integrated circuit 100.

Electrical conductors 180 are arranged within interconnect structure 190 to contact landing areas on different contact layers 160-1 through 160-4. As discussed in more detail below, the electrical conductors 180 for each of the particular contact layers 160-1 through 160-4 extend through the openings of the layers disposed above to the layers of wires that include the conductive interconnects 185. Conductive interconnects 185 are provided as connections between the contact layers 160-1 through 160-4 and the decoding circuitry in the surrounding region 120.

As indicated by the dashed lines in Fig. 3A, the conductors 180 contacting the different contact layers 160-1 to 160-4 are arranged to extend in the longitudinal direction into the section shown in Fig. 3A.

FIG. 3B is a cross-sectional view through the inner connecting structure 190 of FIG. 3A along the 3B and 3B lines in the longitudinal direction, showing a view similar to the interconnecting structure 190 shown in FIG. 1. As can be seen in Figure 3B, the electrical conductors 180 for each particular contact layer extend through the openings of the layers disposed above to contact the landing zone.

In the example shown, four contact layers 160-1 through 160-4 are shown. More generally, the small interconnect structure described herein can be implemented in layers 0 through N, where N is at least 2.

Other types of memory cells and configurations can be used in other embodiments. For example, in a layer of another device, a planar memory cell array separated by an insulating material can be implemented, and a thin film transistor or related technology is used within the layer to form an access device and an access line. Moreover, the interconnect structure described herein can be practiced with other types of three-dimensional stacked integrated circuit devices, wherein it is advantageous to have electrical conductors that extend into different layers in the device in a small bottom area.

In Figures 3A and 3B, a single interconnect structure 190 is shown. A plurality of interconnect structures can be arranged at different locations in the device, such as around the memory array region 110 to provide a more even power distribution. 4 is a top plan view of a layout of an embodiment of apparatus 100 that includes two tandem interconnect structures including regions 190-1 and regions 190 in a surrounding region 120 on respective sides of the array. -2 series. 5 is a top view of the layout of an embodiment, the apparatus 100 comprising four serial interconnect structures comprising a series of 190-1, 190 in the surrounding area 120 on all four sides of the array. -2, 190-3 and 190-4. For example, the array size includes 1000 columns and 1000 rows of cells, and has 10 layers. The feature size F defines the word line width and the bit line width, and the size of the landing area on the layer. Approximately F, it can be seen that the length of the area occupied by an interconnect structure is about 2F times the number of layers or about 20F, and the distance between each word line is about 2F or more, so that the width of the array is about 2000F. . Thus, as shown in this example, about 100 interconnect structures can be formed in a string such as tandem 190-3 along the width of the array, and a similar number can be formed, such as in tandem 190 along the length of the array. 1 in the series

In still other embodiments, one or more interconnect structures may be implemented within the memory array region 110, in addition to or in lieu of the surrounding region 120 having an interconnect structure. Moreover, the interconnect structure may extend diagonally or in any other direction than parallel to one of the edges of the memory array region 110.

Figure 6 is a schematic illustration of a portion of a memory device incorporating the interconnect structure described herein. The first electrode post 171a is coupled to the access transistor 131a, and the access transistor 131a is selected using the bit line 150a and the word line 140a. A plurality of memory elements 544-1 to 544-4 are connected to the electrode column 171a. Each memory element includes a programmable element 548 in series with a rectifier 549. Even if the antifuse material layer is located at the p-n junction, this series arrangement still represents the structure as shown in Figs. 3A and 3B. The programmable element 548 is represented by a symbol commonly used to indicate an antifuse. However, it will be appreciated that other types of programmable resistive materials and structures can be used.

In addition, the rectifier 549 implemented by the p-n junction between the conductive plane and the polysilicon in the electrode column can also be replaced by other rectifiers. For example, a rectifier based on a solid electrolyte such as a telluride or other suitable material can be used to provide a rectifier. For other representative solid electrolyte materials, please refer to U.S. Patent No. 7,382,647.

Each memory element 544-1 through 544-4 is coupled to a corresponding conductive contact layer 160-1 through 160-4. Contact layers 160-1 through 160-4 are coupled to planar decoder 546 via electrical conductors 180 and interconnects 185. The planar decoder 546 is responsive to the address to apply a voltage, such as ground 547, to the selected layer to cause the rectifier in the memory device to be forward biased to conduct and apply a voltage to or to the floating non-selected layer. So that the rectifier in the memory element is reverse biased or non-conducting.

FIG. 7 illustrates a simplified block diagram of an integrated circuit device 300 that includes a three-dimensional memory array 360 having interconnect structures as described herein. Column decoder 361 is coupled to a plurality of word lines 140 arranged along columns in memory array 360. Row decoder 363 is coupled to a plurality of bit lines 150 arranged along rows in memory array 360 for reading and programming data from memory cells in array 360. Planar decoder 546 is coupled to a plurality of contact layers 160-1 through 160-4 in memory array 360 via electrical conductors 180 and interconnects 185. On the bus 365, the address is supplied to the row decoder 363, the column decoder 361, and the plane decoder 546. In this example, the sense amplifier and data input structures in block 366 are coupled to row decoder 363 via data bus 367. From the input/output port on the integrated circuit 300, the data is supplied to the data input structure in block 366 through the data input line 371. In the embodiment, the integrated circuit 300 includes other circuits 374, such as a general purpose processor or a special purpose application circuit, or a module providing a system-on-a-chip function. combination. From the sense amplifier in block 366, the data is supplied to the input/output ports on the integrated circuit 300 through the data output line 372, or to other data destinations internal or external to the integrated circuit 300.

The controller in this example is implemented using a biasing arrangement state machine 369 that controls the application of a supply voltage, such as a read voltage and a program, via a voltage supply or a bias generated or provided by a supply in block 368. Voltage. The controller can be implemented using special purpose logic circuitry as is known in the art. In other embodiments, the controller includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In still other embodiments, a combination of a special purpose logic circuit and a general purpose processor can be utilized with the implementation of the controller.

8A through 8C through 15 illustrate steps in an embodiment of a manufacturing process for fabricating an interconnect structure described herein and having a very small area of the bottom region.

8A and 8C are cross-sectional views showing the first step of the manufacturing process, and FIG. 8B is a top view showing the first step of the manufacturing process. For the purposes of this application, the first step involves forming a plurality of contact layers 160-1 through 160-4 disposed over the provided memory cell access layer 112. In the illustrated embodiment, the structures illustrated in Figures 8A through 8C are formed using the process described in U.S. Patent Application Serial No. 12/430,290, the entire disclosure of which is incorporated herein by reference. .

In other embodiments, the contact layer can be formed by standard processes as in the prior art, and can include access devices such as transistors and diodes, word lines, bit lines and source lines, and conductive plugs. The plug and the doped regions within the substrate, depending on the device, the interconnect structure described therein is practiced.

As noted above, other types of memory cells and configurations for the memory array region 110 can also be used in other embodiments.

Next, the first mask 800 having the opening 810 is formed on the structures shown in FIGS. 8A to 8C, and the structures shown in the upper view and the cross-sectional view of the 9A and 9B are respectively produced. The first mask 800 can be formed by depositing a layer for the first mask 800 and patterning the layer using lithography techniques to form the opening 810. The first mask may comprise, for example, a hard mask material such as tantalum nitride, niobium oxide or niobium oxynitride.

The opening 810 in the first mask 800 surrounds the perimeter of the combination of landing regions on the contact layers 160-1 through 160-4. Accordingly, the width 192 of the opening 810 is at least as wide as the width of the landing region on the contact layers 160-1 through 160-4 such that the subsequently formed electrical conductor 180 can pass through the opening in the contact layer. The length 194 of the opening 810 is at least as long as the sum of the lengths of the landing regions on the contact layers 160-1 through 160-4 such that the subsequently formed electrical conductor 180 can pass through the opening in the contact layer.

Next, the second etch mask 900 is formed on the structure shown in FIGS. 9A and 9B, and is included in the opening 810 to produce a structure in which the top view and the cross-sectional view of the 10A and 10B are respectively shown. As shown in the figures, the second etch mask 900 has a length 910 that is less than the length 194 of the opening 810, and the second etch mask 900 has a width that is at least as wide as the width 192 of the opening 810.

In the illustrated embodiment, the second etch mask 900 includes a material that is selectively etchable relative to the material of the first mask 800 such that the length of the second mask 900 within the opening 810 can be The subsequent process steps described are selectively reduced. In other words, for the process for reducing the length of the second mask 900, the material of the second mask 900 has an etch rate greater than the etch rate of the material of the first mask 800. For example, in this embodiment, the first mask 800 includes a hard mask material and the second mask may include a photoresist material.

Then, the first and second masks 800 and 900 are used as an etch mask, and the etching process is performed on the structures shown in FIGS. 10A and 10B, and the top view and the cross-sectional view of the 11A and 11B are respectively shown. The structure. The etching process can be performed using a single etch chemistry, such as timing mode etching. Alternatively, the etching process can be performed using a different etch chemistry to individually etch the insulating layer 166, the contact layer 160-4, the insulating material 165-3, and the contact layer 160-3.

This etch forms an opening 1000 through the contact layer 160-4 to expose a portion of the contact layer 160-3. The opening 1000 is disposed above the landing area 161-1a on the contact layer 160-1. The opening 1000 has a length 1002 that is at least as long as the length of the landing area 161-1a, and has a width 1004 that is at least as wide as the width of the landing area 161-1a.

This etch also forms an opening 1010 through the contact layer 160-4 to expose a portion of the contact layer 160-3. The opening 1010 is disposed above the landing area 161-1b on the contact layer 160-1. The opening 1010 has a length 1012 that is at least as long as the length of the landing area 161-1b and has a width 1004 that is at least as wide as the width of the landing area 161-1b.

Next, the length 910 of the mask 900 is reduced to form a reduced length mask 1100 having a length 1110 that produces the structure shown in the top and cross-sectional views of Figures 12A and 12B, respectively. In the illustrated embodiment, the mask 900 comprises a photoresist material, and may for example having CL ₂ or HBr as the base chemical reactive ion etching of the trim mask 900.

Next, using the first mask 800 and the reduced length mask 1100 as an etch mask, the etching process is performed on the structures shown in FIGS. 12A and 12B, and the top view and the cross-sectional view of the 13A and 13B are generated. The structure is shown separately.

The etch process extends openings 1000, 1010 through the contact layer 160-3 to expose portions disposed below the contact layer 160-2.

This etch also forms portions of openings 1200, 1210 through contact layer 160-4 that are no longer covered by mask 1100 due to the reduced length of mask 1100, thereby exposing portions of contact layer 160-3. The opening 1200 is formed adjacent to the opening 1000 and disposed above the landing area 161-2a on the contact layer 160-2. The opening 1200 has a length 1202 that is at least as long as the length of the landing region 161-2a and has a width 1204 that is at least as wide as the width of the landing region 161-2a.

The opening 1210 is formed adjacent to the opening 1010 and disposed above the landing area 161-2b on the contact layer 160-2. The opening 1210 has a length 1212 that is at least as long as the length of the landing region 161-2b and has a width 1204 that is at least as wide as the width of the landing region 161-2b.

Next, the length 1110 of the mask 1100 is reduced to form a reduced length mask 1300 having a length 1305. The first mask 800 and the mask 1300 are used as an etch mask to perform an etching process to produce a structure in which the top view and the cross-sectional view of the 14A and 14B are respectively shown.

Etching process extension openings 1000, 1010 pass through contact layer 160-2 to expose landing regions 161-1a, 161-1b on contact layer 160-1. The etch process also extends the openings 1200, 1210 through the contact layer 160-3 to expose the landing regions 161-2a, 161-2b on the contact layer 160-2.

This etching also forms portions of the openings 1310, 1320 through the contact layer 160-4, which are no longer covered by the reduction in the length of the mask 1300, thereby exposing the landing regions 161-3a, 161 on the contact layer 160-3. -3b.

Opening 1310 is formed adjacent to opening 1200. The opening 1310 has a length 1312 that is at least as long as the length of the landing region 161-3a and has a width 1314 that is at least as wide as the width of the landing region 161-3a.

Opening 1320 is formed adjacent to opening 1210. The opening 1320 has a length 1322 that is at least as long as the length of the landing region 161-3b and has a width 1324 that is at least as wide as the width of the landing region 161-3b.

Next, the insulating filling material 1400 is deposited on the structures shown in FIGS. 14A and 14B, and a planarization process such as Chemical Mechanical Polishing (CMP) is performed to remove the masks 800 and 1300 to produce the 15th. The structure shown in the cross-sectional view of the figure.

Next, a lithographic pattern is formed to define vias for the electrical conductors 180 and connected to the landing zone. Reactive ion etching may be applied to form high aspect ratio vias through the insulating fill material 1400 to provide vias for the electrical conductors 180. After the via hole is opened, the via hole is filled with tungsten or other conductive material to form the electrical conductor 180. A metallization process is then applied to form interconnects 185 to provide a connection between the electrical conductors 180 and the planar decoding circuitry on the device. Finally, the back end of line (BEOL) is applied to complete the integrated circuit, resulting in the structure shown in FIGS. 3A and 3B.

The opening for passing the electrical conductor through the landing region on the contact layer disposed under the different contact layers is formed by patterning the contact layer using the opening 810 in the single etching mask 800, and is used Process for etching additional masks without critical alignment steps. Thus, openings having vertically aligned sidewalls in different contact layers are formed in a self-aligned manner.

In the example shown above, the opening 810 in the mask 800 has a rectangular cross-section in a plan view. Thus, the openings in the different contact layers have substantially the same width along the lateral direction. Alternatively, depending on the shape of the landing zone of the different contact layers, the opening in the mask 800 can have a circular, elliptical, square, rectangular or somewhat irregular profile.

For example, to accommodate landing areas having different widths, the width of the opening in the mask 800 can vary along the longitudinal direction. Figure 16 illustrates a plan view of the opening 1510 in the mask 800, which has a varying width along the longitudinal direction in a step-like manner, thereby causing a variation in the width of the opening in the contact layer.

The invention will now be described primarily with reference to Figures 17 to 34A.

The following description will generally refer to embodiments and methods of specific structures. It should be understood that the invention is not intended to be limited to the details of the embodiments disclosed herein. The preferred embodiments are described to illustrate the invention and are not intended to limit the scope of the invention as defined by the scope of the claims. Those skilled in the art will recognize the various equivalent variations of the following description. In the different embodiments, the same elements are commonly referred to by the same element symbols.

17 to 34A are diagrams showing the structure and method of manufacturing an example of another three-dimensional stacked integrated circuit device, and like reference numerals correspond to similar structures. 17 and 17A are simplified side and top views of the interconnect region 17 of this example of the three-dimensional stacked integrated circuit device. In this example, interconnect region 17 includes four interconnect contact layers 18, labeled 18.1 to 18.4, four conductors 54, labeled 54.1 through 54.4, and a ground conductor 55. The electrical conductor 54 has a first portion 57 that passes through the contact layer 18 and has a second portion 59 that passes through the interlayer dielectric 52 and a Stopping Layer 27 to electrically connect to the conductive layer 34 of the contact layer 18 (labeled as One of the line contact areas 14 (labeled 14.1 to 14.4) within 34.1 to 34.4). The first portion 57 is surrounded by dielectric sidewall spacers 61 to electrically isolate the electrical conductors 54 from the conductive layer 34 such that the electrical conductors are not in electrical contact. In addition, the grounding conductor 55 is electrically connected to each of the conductive layers 34 of each of the contact layers 18.

Figures 18 and 18A illustrate the initial steps in the fabrication of the interconnect region 17. The contact opening 33 and the ground contact opening 35 are etched using the photoresist material 88, passing through the upper layer 24 to expose the conductive layer 34. 1 above the first contact layer 18.1, wherein the contact opening 33 is labeled as openings 33.1 to 33.4, and the ground contact opening 35 is drawn. Shown in Figure 18A. After etching of the contact opening 33, the photoresist material 88 is stripped and a first photoresist mask 89 is formed on the interconnect region 17, as shown in Figures 19 and 19A. The first mask 89 exposes every other opening 33, that is, the openings 33.2 and 33.4 in this example. As shown in Fig. 19A, the mask 89 also covers the ground contact opening 35. As can be seen by comparing FIGS. 17 and 18, the position of the contact opening 33 determines the position of the conductor 54, and the position of the ground contact opening 35 determines the position of the ground conductor 55. In this example, the electrical conductors 54 and the interconnect contact regions 14 have a constant spacing.

Figures 20 and 20A illustrate the etching results through a single contact layer 18.1 under exposed contact openings 33.2 and 33.4. The first mask 89 is then stripped, with the formation of a second photoresist mask 90 as shown in Figures 21 and 21A. The second mask 90 is used to expose the contact openings 33.3 and 33.4 while covering the contact openings 33.1 and 33.2 and the ground contact opening 35. Figure 21 illustrates the removal of the first mask 89 and the second mask 90 formed on the structure of Figure 20 such that the first and second contact openings 33.1 and 33.2 from the left are second. The mask is covered, while the third and fourth contact openings 33.3 and 33.4 are exposed.

22 and 22A illustrate the etching results of the two contact layers 18 passing through the third and fourth contact openings 33.3 and 33.4. That is, the contact layers 18.1 and 18.2 are etched through the contact opening 33.3, while the contact layers 18.2 and 18.3 are etched through the contact opening 33.4. 23 and 23A illustrate the structure after the second mask 90 of FIG. 22 is removed. It can be seen that the contact openings 33.1 to 33.4 extend down to the conductive layers 34.1 to 34.4 of the contact layers 18.1 to 18.4.

Figures 24 and 24A illustrate the structure of Figure 23 after the sidewall spacers 61 are formed on the sidewalls of the openings 33.1 to 33.4. The sidewall spacers 61 electrically insulate the contact openings 33.2, 33.3, and 33.4 from the conductive layer 34 of the contact layer 18 through which the contact opening passes.

25 and 25A are cross-sectional views showing the structure of Fig. 24 plus the ground contact opening 35 shown in Fig. 25. All of the contact openings 33 are covered by the photoresist material 92, and the ground contact openings 35 are exposed. FIGS. 26 and 26A illustrate the structure of FIG. 25 after the ground contact opening 35 is etched through the three contact layers 18 to expose the conductive layers 34.1 to 34.4 to the interior of the ground contact opening 35. 27 and 27A illustrate the structure after the photoresist material 92 is removed in FIG.

FIGS. 28 and 28A illustrate the structure after depositing the electrically conductive material 93 in FIG. 27. The electrically conductive material 93 is typically polycrystalline, thereby filling the contact opening 33 and the ground contact opening 35. The material 93 in the contact opening 33 and the ground contact opening 35 respectively form a conductor 54 and a ground conductor 55. If desired, portions of the insulating layer 36 on the sidewalls of the ground contact opening may be etched back or removed prior to forming the ground conductor 55 in the ground contact opening 35 to enhance the conductive layer of the ground conductor 55 and the contact layer 18. Electrical contact between 34. The insulating layer 36 surrounding the ground conductor 55 in Fig. 28 is indicated by a broken line.

Electrically conductive material 93 also covers dielectric layer 26 of upper layer 24. Thereafter, the structure of FIG. 28 is etched away to remove the electrically conductive material 93 covering the dielectric layer 26. This is illustrated in Figures 29 and 29A. The structure of Fig. 29 is subjected to, for example, chemical mechanical polishing down to the stop layer 27, resulting in the structure of Fig. 30.

31 and 31A illustrate the structure of the deposition stop layer 96 of FIG. 30 after depositing the interlayer dielectric 97 on the stop layer. The stop layer 96 is typically tantalum nitride. Next, the structure of FIG. 31 has an extension portion of the contact opening 33 and the ground contact opening 35, which is formed through the interlayer dielectric 97 and the stop layer 96 to the conductor 54 and the ground conductor 55. The conductor 54 is labeled 54.1. To 54.4. Referring to Figures 32 and 32A, the extension, such as tungsten, is then filled with a conductive material to produce conductor 54 and ground conductor 55. The electrical conductor 54 has a first portion 57 that extends across the contact layer 18 and a second portion 59 that extends through the upper layer 24.

In some examples, stop layer 96 is tantalum nitride and interlayer dielectric 97 is hafnium oxide. However, the stop layer 96 can be a layer of other dielectric material, such as ruthenium dioxide or other layers of ruthenium oxide and tantalum nitride. The sidewall spacers 61 may be tantalum nitride but may be other materials such as a plurality of layers of cerium oxide or oxygen/germanium nitride. Similarly, dielectric layer 25 is typically tantalum nitride but may also be, for example, hafnium oxide. The first portion 57 of the electrical conductor 54 is typically polycrystalline but may be other electrically conductive materials such as N+ polysilicon, tungsten, titanium nitride (TiN), and the like. Moreover, the overall length of the electrical conductors 54 can be the same material, such as tungsten.

Figure 33 is a graphical representation of a set of sixteen contact openings representing four different sets of contact openings 33, etched to sixteen different depths, using only four masks to provide access to sixteen contacts Layer 18.

Figures 34 and 34A are cross-sectional and plan views of a three-dimensional stacked integrated circuit device. Figure 34 is a diagram along line of word lines 94 that is electrically isolated by a layer 95, such as a stack of alternating dielectric and semiconductor layers. Layer 95 can be, for example, an alternating of yttrium oxide and tantalum nitride as a charge trapping layer.

The following example discusses a method of providing electrical connection to interconnect contact regions 14 that are located at a stack of contact layers 18 for the three-dimensionally stacked interconnect regions 17 of integrated circuit devices. In this example, the wiring region 17 includes an upper layer 24 having a stack of contact layers 18 underneath, and each of the contact layers includes a conductive layer 34 and an insulating layer 36. At least a portion of any upper layer 24 disposed on the wiring region 17 is removed to expose the first contact layer 18.1 and create contact openings 33 for the respective contact layers 18. This is shown in Figure 18.

A set of N etch masks is used to create a 2 ^N layer of interconnect contact regions 14 at the stack of contact layers 18, up to the number of layers and comprising 2 ^N . Although most of the illustrations are examples of four contact layers 18, the number of contact layers will increase to 16 contact layers in this example, so N=4. The discussion herein will also refer to Figure 33, which includes a graphical representation of the 16 contact openings 33. A mask is used to etch the contact openings 33 up to and including 2 ^N contact layers, in this case 16 contact layers. The steps are as follows.

Referring to Figure 19, a contact layer 18 is etched at every other opening using a first mask 89. The contact openings not covered by the first mask 89 are regarded as equivalent to the eight dot-line boxes surrounding the contact openings 33.2, 33.4, etc. as shown in Fig. 33. Next, referring to Fig. 21, the two contact layers 18 are etched using the second mask 90 in the third and fourth contact openings in the order of a set of first to fourth contact openings. The second mask 90 is considered to be equivalent to the four sets of short dashed boxes surrounding the two adjacent contact openings 33 among a set of four contact openings as shown in FIG. The third and fourth contact openings etched in this example are the first contact opening 33.1 to the third contact opening 33.4, the contact openings 33.3 and 33.4 of the group, the contact openings 33.5 to 33.8, the contact openings 33.7 and 33.8 of the group, etc. . As can be seen from Fig. 22, the use of the first and second masks 89, 90 provides contact openings 33 down to the four contact layers 18.1 to 18.4.

Next, with this example of 16 contact layers 18, four contact layers 18 are etched using a third mask (not shown) in fifth to eighth contact openings 33 in the order of a set of first through eighth contact openings. . This is indicated by the two long dashed boxes in Figure 33. The eight contact layers 18 are etched using a fourth mask (not shown) in the ninth to sixteenth contact openings 33 in the order of at least one set of first to sixteenth contact openings. This is indicated by a solid line box in Figure 33. Note that half of the contact openings are etched by the respective first, second, third and fourth masks.

Referring to Fig. 24, a dielectric layer 61 is formed on the sidewalls of the respective contact openings 33. The electrical conductor 54 is then formed to pass through the contact opening 33 to the inner contact contact region 14 of the contact layer 18, the dielectric layer electrically isolating the electrical conductor 54 from the conductive layer 34 along the sidewall.

As discussed above with reference to Figures 18 and 19, the ground contact opening 35 is typically formed in the same manner as the contact opening 33.1. However, referring to FIG. 24, before the formation of the conductor 54 in the contact opening 33, the ground contact opening 35 is arranged with sidewall spacers on both sides of the upper layer 24, and is etched through the contact layer 18, referring to FIG. An electrically conductive material is filled as shown in FIG. 28 to produce a ground conductor 55. The ground conductor 55 electrically contacts each of the conductive layers 34. Conversely, because of the use of the dielectric sidewall spacers 61, the conductors 54.1 through 54.4 contact only the single conductive layer 34. In some examples, the ground conductors 55 may not be in electrical contact with the respective conductive layers 34.

In the above example, the contact opening 33 is counted from the left to the right. If desired, the contact openings can be counted from left to right or from right to left or in other orders depending on design requirements. The key point is that always half of the contact openings are opened by the masks. That is, when there are even contact openings, each mask will open half of the contact opening, and when there are an odd number of contact openings, for example 15, each mask will open a slightly more or less than half of the contact opening, For example 7 or 8. One / two / four / eight removal of removable also be expressed as ^(N-1) Step 2 for each of layers ^0-2.

The masking and etching procedures of Figure 33 are shown in different forms in Figure 35. In Fig. 35, and subsequent figures 36 to 39, 0 indicates darkness, that is, has a photoresist material, and 1 indicates opening, that is, no photoresist material, so that there are 16 contact openings for each mask. 8 are open.

If the example of the etching process in FIGS. 33 and 35 removes one/two/four/eight layers for the mask 1-4, the contact layer seating (ie, etched to) positioned by the etching sequence can be identified as a seat. Layer, specified as 0-15. The contact layer seating (i.e., etched to) caused by the respective positions A to P is as shown in the figure as the seating layer 0, 1, 2, 3, and the like.

Other etching sequences can be used. For example, Figure 36 illustrates a change in the etching sequence in which the number of layers etched by the mask 1 and the mask 4 is exchanged such that the mask 1 is etched by 8 layers, the mask 2 is etched by 2 layers, and the mask 3 is etched 4 Layer, mask 4 is etched 1 layer. The contact layer seating (i.e., etched to) caused by the respective positions A to P is as shown in the figure as the seating layer 0, 8, 2, 10 and the like.

The order of the masks can be changed without changing the etching sequence, or in addition to changing the etching sequence, that is, comparing the number of layers etched by the respective masks as shown in Figs. 35 and 36. This is illustrated in Figure 37, in which mask 2 is etched 2 layers and mask 3 is etched 4 layers, as in the example of Fig. 35. However, in the example of Fig. 35, the mask order for the mask 2 (00110011, etc.) becomes the mask order for the mask 3 in the example of Fig. 37, and the mask 3 is masked in the example of Fig. 35. The mask order (00001111000, etc.) becomes the mask order for the mask 2 in Fig. 37. The contact layer seating (i.e., etched to) caused by the respective positions A to P is as shown in the figure as the seating layers 0, 1, 4, 5 and the like.

Refer to Figure 38 for the position change. In this example, the number of layers etched for masks 1 to 4 is the same as that of Fig. 35. Even if position A is exchanged with position J, the seat layer for each position A to P remains the same, including for position A. Layer 0 is layer 9 for the J position. However, for the two examples of Figs. 35 and 36, the etching for each of the positions A to P is the same. The contact layer seating (i.e., etched to) caused by the respective positions J, B, C, etc. is shown as the seating layer 9, 1, 2, 3, and the like.

Fig. 39 is a view showing the result of using the first example of Fig. 35 and changing the etching order of Fig. 36, changing the mask order of Fig. 37, and changing the position of Fig. 38. However, this resulting structure still has 16 different seating layers for 16 different locations. The contact layer seating (i.e., etched to) caused by the respective positions J, B, C, etc. is illustrated as the seating layers 9, 8, 4, 12, and the like.

Any patents, patent applications, and printed publications, which are hereby incorporated by reference, are incorporated herein by reference.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

14, 14.1, 14.2, 14.3, 14.4. . . Interconnect contact area

17. . . Inline area

18.1, 18.2, 18.3, 18.4, 160-1, 160-2, 160-3, 160-4. . . Contact layer

19. . .矽 substrate

twenty four. . . upper layer

25, 26. . . Dielectric layer

27, 96. . . Stop layer

28. . . Upper dielectric layer

29. . . Bottom dielectric layer

33, 33.1, 33.2, 33.3, 33.4. . . Contact opening

34, 34.1, 34.2, 34.3, 34.4. . . Conductive layer

35. . . Ground contact opening

36, 36.1, 36.2, 36.3, 36.4, 164, 165-1, 165-2, 165-3, 166. . . Insulation

52, 144, 154. . . Interlayer dielectric

54, 54.1, 54.2, 54.3, 54.4, 180. . . Electrical conductor

55. . . Ground conductor

57. . . The first part of the electrical conductor 54

59. . . The second part of the electrical conductor 54

61. . . Dielectric sidewall spacer

88, 92. . . Photoresist material

89. . . First mask

90. . . Second mask

93. . . Electrically conductive material

95. . . Charge trapping layer

97. . . Interlayer dielectric

100, 300. . . Three-dimensional stacked integrated circuit device

110. . . Memory array area

112. . . Memory cell access layer

120. . . Surrounding area

130. . . Semiconductor substrate

131a, 131b. . . Horizontal field effect transistor access device

132a, 132b. . . Source area

134a, 134b. . . Bungee area

135a, 135b. . . Trench isolation structure

140, 140a, 140b, 94. . . Word line (WL)

142a, 142b. . . Contact plug

146a, 146b. . . Contact window

150, 150a, 150b. . . Bit line (BL)

152a, 152b. . . Contact pad

161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b, 161-4. . . Landing area

165. . . Insulation Materials

170a, 170b. . . Conductive core layer

171a. . . First electrode column

171b. . . Second electrode column

172a, 172b. . . Polycrystalline germanium overlay

174a, 174b. . . Antifuse material layer

185. . . Internal connection

190. . . Inline structure

190-1, 190-2, 190-3, 190-4. . . Serial

192. . . Width of opening 810

194. . . Length of opening 810

200. . . Width of landing area 161-1a

201. . . Length of landing area 161-1a

202. . . Width of landing area 161-1b

203. . . Length of landing area 161-1b

204. . . Width of landing area 161-2a

205. . . Length of landing area 161-2a

206. . . Width of landing area 161-2b

207. . . Length of landing area 161-2b

214. . . Width of landing area 161-3a

215. . . Length of landing area 161-3a

216. . . Width of landing area 161-3b

217. . . Length of landing area 161-3b

224. . . Width of landing area 161-4

225. . . Length of landing area 161-4

250, 255, 260, 265, 270, 275, 810, 1000, 1010, 1200, 1210, 1310, 1320, 1510. . . Opening

251a, 251b, 256a, 256b, 261a, 261b, 271a, 271b, 276a, 276b. . . Vertical side wall

252. . . Length of opening 250

253a, 253b, 258a, 258b, 263a, 263b, 268a, 268b, 273a, 273b, 278a, 278b. . . Lateral side wall

254. . . Width of opening 250

257. . . Length of opening 255

259. . . Width of opening 255

262. . . Length of opening 260

264a, 264b. . . Width of opening 260

266a, 261a. . . Outer longitudinal side wall

266b, 261b. . . Medial longitudinal side wall

267. . . Length of opening 265

269a, 269b. . . Width of opening 265

272. . . Length of opening 270

274a, 274b, 274c. . . Width of opening 270

277. . . Length of opening 275

279a, 279b, 279c. . . Width of opening 275

360. . . Three-dimensional memory array

361. . . Column decoder

363. . . Row decoder

365, 367. . . Busbar

366. . . Sense amplifier and data input structure

368. . . Biased arrangement supply voltage

369. . . Biased state machine

371. . . Data input line

372. . . Data output line

374. . . Other circuit

544-1, 544-2, 544-3, 544-4. . . Memory component

546. . . Planar decoder

547. . . Ground

548. . . Programmable component

549. . . Rectifier

800. . . First mask

900. . . Second mask

910. . . Length of the second mask

1002. . . Length of opening 1000

1004. . . Width of opening 1000, 1010

1012. . . Length of opening 1010

1100, 1300. . . Reduced length mask

1110. . . The length of the mask 1100

1202. . . Length of opening 1200

1204. . . Width of openings 1200, 1210

1212. . . Length of opening 1210

1305. . . The length of the mask 1300

1312. . . Length of opening 1310

1314. . . Width of opening 1310

1322. . . Length of opening 1320

1324. . . Width of opening 1320

1400. . . Insulating filling material

Figures 1 through 16 and related descriptions are taken from U.S. Patent Application Serial No. 12/579,192, filed on Oct. 14, 2009, and entitled "3D Integrated Circuit Layer Interconnect having the same assignee as this application" The disclosure is incorporated herein by reference.

1 is a cross-sectional view of a device including a three-dimensional structure having an interconnect structure 190 having a small bottom area region, wherein the electrical conductors 180 extend to different contact layers 160-1 of the device to 160-4.

Fig. 2A is a plan view showing the contact layer 160-1, showing the landing area.

Figure 2B is a plan view of the contact layer 160-2 showing the opening adjacent to the landing area.

Figure 2C shows a plan view of the contact layer 160-3 showing the opening adjacent to the landing area.

Figure 2D shows a plan view of contact layer 160-4 showing the opening adjacent to the landing zone.

3A and 3B illustrate respective vertical views of a portion of a three-dimensional stacked integrated circuit device including a 3-dimensional interconnect structure having a small bottom area.

Figure 4 is a top plan view showing the layout of one embodiment of the device including an interconnect structure in the periphery of the sides of the memory array.

Figure 5 is a top plan view showing the layout of an embodiment of the device including an interconnect structure in the periphery of the four sides of the memory array.

Figure 6 is a schematic illustration of a portion of a memory device incorporating the interconnect structure described herein.

Figure 7 is a simplified block diagram of an integrated circuit device including a three dimensional memory array having the interconnect structure described herein.

8A through 8C through 15 illustrate steps for fabricating a manufacturing process for the interconnect structure described herein.

Figure 16 is a plan view showing the opening in the mask having a varying width along the longitudinal direction in a step-like manner to accommodate varying widths of the landing area on the layer.

17 to 34A are diagrams showing the structure and method of manufacturing an example of another three-dimensional stacked integrated circuit device.

17 and 17A are simplified side and top views of an interconnect region of another example of a three-dimensional stacked integrated circuit device.

The 18th and 18th drawings illustrate the interconnect region after the contact opening is formed through the upper layer to expose the conductive layer above the first contact layer.

19 and 19A illustrate the first mask on the structure of FIG. 18, the first mask exposing the partition opening.

Figures 20 and 20A illustrate the results of etching through a single contact layer at the exposed contact opening.

21 and 21A illustrate the removal of the first mask and the result of the second mask being formed on the structure of FIG. 20 such that the first and second contact openings from the left are covered by the second mask. Covered, while the third and fourth contact openings are exposed.

22 and 22A illustrate etching results of the two contact layers passing through the third and fourth contact openings.

23 and 23A illustrate the structure after the second mask is removed in FIG. 22.

24 and 24A illustrate a structure in which a sidewall spacer is formed on the sidewall of the opening in FIG. 23, whereby the contact layer is electrically insulated from the inside of the contact opening.

25 and 25A are cross-sectional views showing the structure of Fig. 24 plus the ground contact opening shown in Fig. 25. The contact opening is covered by the photoresist material and the ground contact opening is exposed.

Figures 26 and 26A illustrate the structure of Figure 25 after etching through the three contact layers to expose the conductive layer of the ground contact opening.

Figures 27 and 27A illustrate the structure after removal of the photoresist material in Figure 26.

FIGS. 28 and 28A illustrate a structure in which a polycrystalline germanium layer is filled with a contact opening and a ground contact opening and covered with an upper layer, and the polysilicon layer in the contact opening and the ground contact opening respectively form a conductor and a ground conductor.

29 and 29A illustrate the structure after etching away the polysilicon layer covering the upper layer in FIG.

Figures 30 and 30A illustrate the results of chemical mechanical polishing of the charge trapping layer from the upper surface down to the upper surface.

31 and 31A illustrate the structure of the deposition stop layer of FIG. 30 after depositing the interlayer dielectric oxide on the stop layer.

32 and 32A illustrate a structure in which the extension portion of the contact opening extends through the interlayer dielectric oxide and the stop layer to the conductor and the ground conductor, and then the via hole is filled with the conductor to generate the conductor. And a grounded conductor having a first portion extending through the contact layer and a second portion extending through the upper layer.

Figure 33 is a graphical representation of a set of sixteen contact openings, representing different sets of contact openings, etched to four different depths to produce the structure of Figure 17.

Figures 34 and 34A are cross-sectional and plan views of a three-dimensional stacked integrated circuit device.

Figure 35 illustrates a different form of masking and etching procedure in Figure 33.

Figures 36 through 38 are similar to Figure 35, but with changes in etching sequence, mask order changes, and positional order changes, respectively.

Figure 39 is similar to Figure 35 but incorporates the changes of Figures 36-38.

14.1, 14.2, 14.3, 14.4. . . Interconnect contact area

17. . . Inline area

18.1, 18.2, 18.3, 18.4. . . Contact layer

19. . .矽 substrate

25. . . Dielectric layer

27. . . Stop layer

28. . . Upper dielectric layer

29. . . Bottom dielectric layer

34.1, 34.2, 34.3, 34.4. . . Conductive layer

36.1, 36.2, 36.3, 36.4. . . Insulation

52. . . Interlayer dielectric

54.1, 54.2, 54.3, 54.4. . . Electrical conductor

55. . . Ground conductor

57. . . The first part of the electrical conductor 54

59. . . The second part of the electrical conductor 54

61. . . Dielectric sidewall spacer

Claims (23)

A method for using a three-dimensional stacked integrated circuit device having a stack of at least four contact layers in an interconnect region to generate a plurality of interconnect contact regions, the interconnect contact regions and the contact layers The plurality of landing areas are aligned and expose the landing areas of the contact layers, each of the contact layers comprising a conductive layer and an insulating layer, the method comprising: removing any upper layer disposed on the interconnecting area At least a portion to expose a first contact layer and to generate a plurality of contact openings for each of the contact layers; a set of N etch masks for generating a plurality of interconnects at the stack of the contact layers a line contact region layer, N is an integer at least equal to 2; using the N etch masks to etch the contact openings up to and including 2 N-th contact layers, the N mask use steps The method includes: using a first mask to etch one contact layer for the effective half of the contact openings; using a second mask to etch two of the contact layers for the effective half of the contact openings; And the The removing, the selecting, and the using step are performed such that the contact openings extend to the 2 N-th contact layers; and forming a plurality of electrical conductors through the contact openings to contact the contacts These landing areas of the layer. The method of claim 1, wherein the removing step is performed using an additional mask. The method of claim 1, wherein the first mask using step comprises etching the contact layer with every other one of the contact openings using the first mask; and the second mask using step comprises The two contact layers are etched using the second mask in the third and fourth contact openings of the at least one of the first to fourth contact openings. The method of claim 1, wherein the N masking steps further comprise: using a third mask to etch four of the contact layers for the effective half of the contact openings; A fourth mask is used to etch eight of the contact layers for the effective half of the contact openings. The method of claim 4, wherein the third mask use step comprises using the third mask to the fifth to the eighth of the at least one of the first to eighth contact openings The contact opening etches the four contact layers; and the fourth mask using step includes using the fourth mask to the ninth to the sixteenth contacts of the at least one of the first to sixteenth of the contact openings The openings etch eight of the contact layers. The method of claim 4, wherein the first mask use step is performed to etch the second, fourth, sixth, eighth, tenth, twelfth, tenth 4. One of the sixteenth opening of the contact layer; the second mask is used to perform etching for the third, fourth, seventh, eighth, eleventh, twelfth, and fifteenth And the two contact openings of the sixteenth opening; the third mask using step is performed to etch four of the contact layers located in the fifth to eighth, thirteenth to sixteenth openings; And the fourth mask using step is performed to etch the eight contact layers located in the ninth to sixteenth openings. The method of claim 4, wherein the first mask use step is performed to etch the second, fourth, sixth, eighth, tenth, twelfth, tenth 4. The eight contact openings of the sixteenth opening; the second mask using steps are performed for etching at the fifth, sixth, seventh, eighth, thirteenth, fourteenth, 15. The two contact layers of the sixteenth opening; the third mask using steps are performed for etching the third, fourth, seventh, eighth, eleventh, twelfth, Four of the contact layers of the fifteenth and sixteenth openings; and the fourth mask using step is performed to etch one of the contact layers located in the ninth to sixteenth openings. The method of claim 1, further comprising: generating a ground contact opening through the contact layers; and forming a ground conductor through the ground contact opening to form a plurality of the contact layers The conductive layers are in electrical contact. The method of claim 8, wherein the ground contact opening has a ground contact opening sidewall, and further comprising: a portion of the insulating layer removed from the sidewall of the ground contact opening before the grounding conductor forming step Therefore, the grounding conductor enhances electrical contact between the grounding conductor and the plurality of conductive layers of the contact layers. The method of claim 1, wherein the using step is performed in a numbered order of the contact layers different from the etching. The method of claim 1, wherein the contact openings have a plurality of sidewalls, and further comprising forming a dielectric layer on the sidewalls. A method for a three-dimensional stacked integrated circuit device of the type comprising an interconnect region, the method for providing a plurality of electrical connections to a stack of a plurality of contact layers located in the interconnect region a plurality of landing areas, the interconnecting area comprising an upper layer, the stack having the contact layers under the upper layer, each of the contact layers comprising a conductive layer and an insulating layer, the method comprising: removing the inner layer disposed therein Connecting at least a portion of any of the upper layers on the area to expose a first contact layer and to create a plurality of contact openings for each of the contact layers; selecting a set of N etch masks for the contact layers The stack generates a plurality of interconnecting contact region layers, N being an integer at least equal to 2; using the N etch masks to etch the contact openings up to and including 2 N-th contact layers The N mask use steps include: using a first mask to etch one of the contact layers for the effective half of the contact openings; using a second mask to effectively halve the contacts Open etching Two of the contact layers; and the removing, the selecting, and the using step are performed such that the contact openings define a plurality of sidewalls and extend to the two N-th contact layers; forming a dielectric layer And forming a plurality of electrical conductors through the contact openings to the landing regions of the contact layers, the dielectric layers electrically insulating the electrical conductors to the sidewalls. The method of claim 12, further comprising: generating a ground contact opening through the contact layers; and forming a ground conductor through the ground contact opening to form a plurality of the contact layers The conductive layers are in electrical contact. The method of claim 13, wherein the ground contact opening has a ground contact opening sidewall, and further comprising: the insulating layer removed from the sidewall of the ground contact opening before the grounding conductor forming step a portion of the plurality of conductive layers adjacent to the ground contact opening being exposed, thereby enhancing the electrical contact of the ground conductor with the plurality of conductive layers. The method of claim 12, further comprising forming a plurality of contact opening extensions on an upper layer disposed on the interconnect region, and wherein the electrical conductor forming steps extend through the contacts A first portion of one of the plurality of electrical conductors of the layer and a second portion of one of the electrical conductors extending through the upper layer are performed. The method of claim 15, wherein the electrical conductor forming steps are performed with the first portion and the second portion being different electrically conductive materials. a three-dimensional stacked integrated circuit device includes: at least one of the first, second, third, and fourth contact layers stacked in an interconnect region; each of the contact layers includes a conductive layer and an insulating layer; And the second, third, and fourth electrical conductors pass through the portion of the stack of the contact layers, wherein the fourth electrical conductor penetrates at least one of the contact layers; the first, second, third, and The fourth conductive system is in electrical contact with the first, second, third, and fourth conductive layers, respectively; and a dielectric sidewall spacer surrounds the second, third, and fourth electrical conductors, such that the second, The third and fourth electrical conductors only electrically contact the respective second, third, and fourth conductive layers. The stacked integrated circuit device of claim 17, wherein the first, second, third, and fourth electrical conductors have a constant pitch. The stacked integrated circuit device of claim 18, wherein the positions of the first, second, third, and fourth electrical conductors are determined by a common mask. The stacked integrated circuit device of claim 17, wherein the positions of the first, second, third, and fourth electrical conductors are determined by a common mask. The stacked integrated circuit device of claim 17, further comprising a grounding conductor passing through the portion of the stack of the contact layers and electrically contacting the first, second, third and fourth portions Conductive layer. Stacked integrated circuit package as described in claim 21 The position of the first, second, third, and fourth electrical conductors and the grounding conductor is determined by a common mask. a three-dimensional stacked integrated circuit device includes: at least one of the first, second, third, and fourth contact layers stacked in an interconnect region; each of the contact layers includes a conductive layer and an insulating layer; And the second, third, and fourth electrical conductors pass through the portion of the stack of the contact layers; the first, second, third, and fourth conductive systems are respectively associated with the first, second, third, and The fourth conductive layer is electrically contacted; a dielectric sidewall spacer surrounds the second, third, and fourth electrical conductors, such that the second, third, and fourth electrical conductors only electrically contact the respective second, a third and fourth conductive layer; a grounding conductor passes through the portion of the stack of the contact layers and electrically contacts the first, second, third, and fourth conductive layers; the first, second, The third and fourth electrical conductors have a constant spacing; and the positions of the first, second, third, and fourth electrical conductors and the ground electrical conductor are determined by a common mask.