TWI416613B - Method of alignment mark protection and semiconductor device formed thereby - Google Patents

Abstract

A method of protecting alignment marks from damage in a planarization process includes providing a substrate, forming alignment mark trenches in the substrate, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, patterning the second dielectric layer to expose the first dielectric layer associated with the alignment mark trenches, resulting in a patterned second dielectric layer, wherein openings are defined by the alignment mark trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings.

Description

Method for protecting alignment mark and semiconductor element formed by the same

The present invention relates generally to a method of fabricating a semiconductor, and more particularly to a method of preventing damage to an alignment mark in a planarization process and a semiconductor device formed by the method.

One of the focuses of manufacturing an integrated circuit (IC) is to align a plurality of layers in the fabrication of a semiconductor component. That is, each layer is precisely aligned so that the circuitry formed therein conforms to the design and functions properly. However, as the size of semiconductor components shrinks, the accuracy of aligning each layer is a critically important key in the process.

Layer-to-layer alignment is often used in conjunction with a tool called a stepper. By means of a stepper, a circuit pattern can be projected onto a film layer on a semiconductor wafer from a mask or reticle loaded on the stepper. Typically, the wafers that have been patterned are placed or aligned relative to the reticle. Alignment can be accomplished using an alignment mark that has been defined on the wafer in a prior process, and subsequent steps, such as a projection pattern, onto the semiconductor wafer can be performed.

FIG. 1 depicts a top view of the alignment mark region 11 in the substrate 10. The active region 13, the alignment mark region 11, and a plurality of alignment mark trenches 12 may be overlaid on the substrate 10. The alignment mark trenches 12 may be arranged in an optional cross pattern and formed in the alignment mark regions 11. Additionally, a flattop 14 of alignment marks can be defined between adjacent alignment mark trenches 12.

When more layers are formed on the wafer, in order to planarize the topography of the wafer in the middle process, a global planarization technique such as chemical and mechanical polish may be used. CMP), chemical mechanical polishing involves chemical etching and/or mechanical polishing/grinding of the surface. However, chemical mechanical polishing or other planarization processes may damage the alignment marks on the wafer and cause a loading effect, which will be discussed in Figures 2a through 2f.

Referring to FIG. 2a, a substrate 200 is provided. The substrate 200 may be p-type or n-type. The substrate 200 can be divided into an active area 210 and a predefined alignment mark area 211. The active area 210 can be used to form electronic component features; the predefined alignment mark area 211 has an alignment mark trench 207. The alignment mark trench 207 can be formed using plasma etching. The alignment mark trench 207 has a desired depth that is related to a function of the alignment radiation wavelength, such as λ/4.

Then, a thin oxide layer 201 is grown on the substrate 200. Next, a tantalum nitride (Si ₃ N ₄ ) layer 202 is formed on the oxide layer 201.

Referring to FIG. 2b, a patterned tantalum nitride layer 208 is formed in the active region 210 by photolithographic patterning and etching to define a shallow trench isolation (STI) region 220.

Referring to FIG. 2c, an oxide layer 230 is deposited on the tantalum nitride layers 202 and 208 to fill the STI regions 220 to form the STI features 221.

Referring to FIG. 2d, a portion of the oxide layer 230 is removed by an etching process, leaving the oxide layer 231 on the alignment trench 207, and then a planarization process is performed. The planarization may include a residue removal process, such as a CMP process, which wets the wafer by wetting the polishing pad with a slurry formed by mixing a basic solvent, abrasive particles, and suspension fluid. The surface finishes the CMP process. The CMP process can proceed to reach a termination layer, such as tantalum nitride layer 202.

Referring to FIG. 2e, the residual oxide 231 and tantalum nitride layer 202 are removed. Next, a polysilicon layer 240 is deposited.

Referring to FIG. 2f, with STI oxide 221 as the termination layer, when another planarization process such as CMP is performed, since oxide 221 is much harder than polysilicon 240, load effects may occur thereby damaging the alignment marks.

Embodiments of the present invention may provide a method of preventing alignment marks from being damaged during a planarization process. The method includes providing a substrate including a first region and a second region, forming a plurality of alignment mark trenches in the substrate of the second region, and forming a first dielectric layer on the substrate Forming a second dielectric layer on the first dielectric layer, removing a second dielectric layer over the alignment mark trench, and forming a patterned region in the first region of the substrate to form a patterned second dielectric layer, wherein the alignment mark trench and the patterned second dielectric layer define a plurality of openings, and the patterned regions expose portions of the substrate, and the substrate is etched through the exposed portions, Forming a third dielectric layer on the patterned second dielectric layer, using the patterned second dielectric layer as a stop layer, planarizing the third dielectric layer to form in the first region A plurality of isolation features and a residual third dielectric layer is formed in the openings of the second region.

Embodiments of the present invention can provide a method of preventing damage to alignment marks during a planarization process. The method includes providing a substrate, forming a plurality of alignment mark trenches in the substrate, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, and patterning the second dielectric layer a layer to expose a first dielectric layer associated with the alignment mark trench to form a patterned second dielectric layer, wherein the alignment mark trench and the patterned second dielectric layer define a plurality of openings, Forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the opening, and patterning the second dielectric layer as a termination layer to planarize the third dielectric layer A residual third dielectric layer is formed in the opening.

Embodiments of the present invention can provide a semiconductor component. This semiconductor element has a structure. This structure is used to protect the alignment marks from damage during the planarization process. The semiconductor component includes a substrate, a plurality of isolation features, and a plurality of alignment marks. The substrate includes a first region and a second region, the first region and the second region being separated from each other. The isolation feature is on the first region and the plurality of alignment marks are on the second region, wherein the alignment mark and the isolation feature are flush with each other over the substrate.

Additional features and advantages of the invention will be set forth in the <RTIgt; Additional features and advantages of the invention will be realized or obtained in the <RTIgt;

It is to be understood that the foregoing general description and the claims

The embodiments of the present invention are described in detail below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings

3a through 3g are cross-sectional views showing a method of protecting alignment marks in accordance with an embodiment of the present invention. Referring to FIG. 3a, a substrate 300 is provided. The substrate 300 may be p-type or n-type. The substrate 300 can include a first region 310 and one or more second regions 311 having a device feature thereon, and a second region 311 having alignment mark trenches 307. The first region 310 and the second region 311 may be separated from each other. In addition, the alignment mark trench 307 can be formed by a patterning and etching process or other suitable process. In a 75-nanometer (nm) flash memory process embodiment, each trench 307 has a depth of about 1200 angstroms (angstrom, ).

Then, a first dielectric layer 301 is formed on the substrate 300 by, for example, a thermal oxidation process. In an embodiment, the first dielectric layer 301 may include hafnium oxide, such as hafnium oxide (SiO ₂ ) or hafnium oxynitride (SiON). Further, in the embodiment of the 75-nano process, the first dielectric layer 301 may have a thickness of about 50 to 150 angstroms.

Next, a second dielectric layer 302 is formed on the first dielectric layer 301 by a deposition process. In an embodiment, the second dielectric layer 302 may include tantalum nitride (Si ₃ N ₄ ) and have a thickness of about 1400 to 1800 angstroms.

Referring to FIG. 3b, a patterned second dielectric layer 312 can be formed by a photolithographic patterning and etching process. The patterned second dielectric layer 312 can include a patterned region 308 that is located in the first region 310 that exposes a portion 320 of the substrate 300. Moreover, in the etching process, the second dielectric layer 312 over the alignment mark trench 307 can be removed to expose the first dielectric layer 301 in the alignment mark trench 307. Thus, the patterned second dielectric layer 312 and the alignment mark trench 307 on the second region 311 can define an opening 309.

Next, the substrate 300 is etched through the exposed portion 320 to form a shallow trench isolation (STI) feature.

Referring to FIG. 3c, a third dielectric layer 330 is formed on the patterned second dielectric layer 312 to form the STI features 321 in the first region 310. In one embodiment of the invention, the third dielectric layer 330 may comprise hafnium oxide or hafnium oxynitride and has a thickness of between about 3,000 and 4,000 angstroms.

Referring to FIG. 3d, the patterned second dielectric layer 312 is used as a termination layer, and a portion of the third dielectric layer 330 is removed through a first planarization process, such as a chemical mechanical polishing (CMP) process, to retain the opening 309. The third dielectric layer 332.

Referring to FIG. 3e, the patterned second dielectric layer 312 of FIG. 3d can be removed. The remaining third dielectric layer 332 can thus serve as an alignment mark.

Next, referring to FIG. 3f, a conductor layer 340, such as a polysilicon layer, is formed on the first dielectric layer 301, the STI features 321 and the remaining third dielectric layer 332 by, for example, a deposition process. In one embodiment, the conductor layer 340 has a thickness of between about 3,000 and 4,000 angstroms.

Referring to FIG. 3g, at least one of the STI feature 321 or the remaining third dielectric layer 332 is used as a termination layer, and the patterned conductor layer 342 is formed through a second planarization process, such as a CMP process. After the second planarization process, the remaining third dielectric layer 332, STI features 321 and patterned conductor layer 342 are flush with each other on the substrate 300. In addition, the remaining third dielectric layer 332 can include a first portion 3321 and a second portion 3322, wherein the first portion 3321 is in the substrate 300 and the second portion 3322 is above the substrate 300.

It will be apparent to those skilled in the art that modifications may be made to the embodiments without departing from the scope of the invention. It is understood that the invention is not limited to the specific embodiments disclosed herein, and the invention is intended to cover the modifications and the scope of the invention as defined by the appended claims.

Furthermore, in describing the exemplary embodiments of the present invention, the embodiments are described in a particular order of steps to illustrate the method or process of the invention. However, the method or process is not required to follow the specific sequence of steps set forth herein, and the method or process should not be limited to the specific order of steps described above. It will be appreciated by those of ordinary skill in the art that other sequences of steps are also reasonable. Therefore, the specific order of steps set forth in the examples should not be construed as limiting the scope of the claims. In addition, the scope of the patent application of the method or process of the present invention should not be limited to the effect of the above-described sequence of steps, and those skilled in the art can understand that without departing from the spirit and scope of the invention. The order is changeable.

10, 200, 300. . . Substrate

11, 211. . . Alignment mark area

13, 210. . . Active area

12, 207, 307. . . Alignment mark trench

14. . . Alignment mark flat top

201, 230, 231. . . Oxide layer

202, 208. . . Tantalum nitride layer

220. . . Shallow trench isolation area

221. . . STI oxide

240. . . Polycrystalline layer

301. . . First dielectric layer

302, 312. . . Second dielectric layer

308. . . Patterned area

309. . . Opening

310. . . First area

311. . . Second area

320. . . Exposed part

321. . . STI features

330, 332, 3321, 3322. . . Third dielectric layer

340, 342. . . Conductor layer

Figure 1 depicts a top view of an alignment mark area in a substrate.

2a through 2f are cross-sectional views showing a conventional semiconductor fabrication method in which a planarization process damages alignment marks.

3a through 3g are cross-sectional views showing a method of protecting alignment marks in accordance with an embodiment of the present invention.

300. . . Substrate

301. . . First dielectric layer

310. . . First area

311. . . Second area

321. . . STI features

332. . . Third dielectric layer

342. . . Conductor layer

Claims (17)

A method for preventing damage of an alignment mark in a planarization process, the method comprising: providing a substrate including a first region and a second region; forming a plurality of trenches, the trenches being from the second region a surface extending into the substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; removing the first dielectric layer and the second dielectric layer a plurality of portions to expose portions of the first region of the substrate and to remove the second dielectric layer over the trenches in the second region to form a patterned second The dielectric layer, the trenches in the second region and the patterned second dielectric layer define a plurality of openings; the substrate is etched through the exposed portions; and the patterned second dielectric layer is formed Forming a third dielectric layer thereon; and planarizing the third dielectric layer with the patterned second dielectric layer as a termination layer to form a plurality of isolation features in the first region, and a residual third dielectric layer is formed in the openings of the two regions, wherein the residual third dielectric Comprising a first portion and a second portion, the first portion in the substrate, the second portion over the substrate. The method for preventing damage of the alignment mark in the planarization process as described in claim 1, after planarizing the third dielectric layer, further comprising: removing the patterned second dielectric layer; Forming a conductor layer on the isolation features and the remaining third dielectric layer; and planarizing the conductor layer with one of the isolation features and the remaining third dielectric layer as a termination layer. A method of preventing damage to an alignment mark in a planarization process as described in claim 2, wherein the isolation features and the second portion of the residual third dielectric layer are flush with each other. The method for preventing damage of an alignment mark in a planarization process as described in claim 1, wherein the first dielectric layer and the third dielectric layer respectively comprise one of cerium oxide and cerium oxynitride. A method of preventing damage to an alignment mark in a planarization process as described in claim 1, wherein the second dielectric layer comprises tantalum nitride. A method for preventing damage to an alignment mark in a planarization process, the method comprising: providing a substrate, the substrate including a surface; forming a plurality of trenches extending from the surface into the substrate; forming on the substrate a first dielectric layer; a second dielectric layer formed on the first dielectric layer; the second dielectric layer above the trenches being removed to form a patterned second dielectric layer, The trenches and the patterned second dielectric layer define a plurality of openings; forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings; Forming the second dielectric layer as a termination layer, planarizing the third dielectric layer, and forming a residual third dielectric layer in the openings, wherein the remaining third dielectric layer comprises a first a portion and a second portion, the first portion being in the substrate and the second portion being above the substrate. A method for preventing damage of an alignment mark in a planarization process as described in claim 6: removing the patterned second dielectric layer; and the first dielectric layer and the residual third dielectric layer A conductor layer is formed on the electrical layer; and the remaining third dielectric layer is used as a termination layer to planarize the conductor layer. The method for preventing damage of an alignment mark in a planarization process as described in claim 6, wherein patterning the second dielectric layer further comprises: removing a second dielectric over the trenches a layer; and forming a patterned region on an active region of the substrate, wherein the patterned region exposes portions of the substrate. The method for preventing damage of an alignment mark in a planarization process, as described in claim 8, further comprising: etching the substrate through the exposed portions; and on the patterned second dielectric layer After forming the third dielectric layer and planarizing the third dielectric layer, a plurality of isolation features are formed. The method for preventing damage of the alignment mark in the planarization process as described in claim 9 after the planarization process, after planarizing the third dielectric layer, further comprising: removing the patterned second dielectric layer; Forming a conductor layer on the isolation features and the remaining third dielectric layer; and planarizing the conductor layer with one of the isolation features and the residual third dielectric layer as a termination layer. A method of preventing damage to an alignment mark in a planarization process as described in claim 9 wherein the isolation features and the second portion of the remaining third dielectric layer are flush with each other. The method for preventing damage of an alignment mark in a planarization process as described in claim 6, wherein the first dielectric layer and the third dielectric layer respectively comprise one of yttrium oxide and yttrium oxynitride. A method of preventing damage to an alignment mark in a planarization process as described in claim 6 wherein the second dielectric layer comprises tantalum nitride. A semiconductor device having a structure for protecting an alignment mark from damage during a planarization process, the semiconductor device comprising: a substrate including a surface, a first region and a second region, the first The region and the second region are separated from each other; a plurality of isolation features are disposed on the first region; and a plurality of alignment marks are disposed on the second region, wherein each of the alignment marks includes a first portion and a second portion a portion of the first portion is on the substrate, the second portion is over the substrate; and a patterned conductor layer, the alignment marks on the substrate, and the isolation features They are flush with each other. The semiconductor component of claim 14, wherein the second portion of each alignment mark and the isolation features are flush with each other. The semiconductor device of claim 14, wherein the alignment marks comprise one of cerium oxide and cerium oxynitride. The semiconductor device of claim 14, wherein the isolation features comprise one of cerium oxide and cerium oxynitride.