TWI398838B - Shift register unit, scan driving circuit, display apparatus and control method of shift register unit - Google Patents

Description

Shift register unit, scan drive circuit, display device and shift register Unit control method

The invention relates to a shift temporary storage unit, a scan driving circuit, a display device and a control method of a shift temporary storage unit.

The display device has been developed from an early cathode ray tube (CRT) display device to today's liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices, and electronic paper. (E-Paper) display device, and is widely used in communications, information and consumer electronics.

In the case of a liquid crystal display device, it includes a scan driving circuit. The scan driving circuit has a shift register unit for transmitting a driving signal to sequentially drive the plurality of scan lines electrically connected to the shift register unit. Referring to FIG. 1 , the conventional shift register unit 1 includes a plurality of shift registers 11 to 13. The shift register 11 is electrically connected to the scan line S ₁₁ , and the shift register 12 is electrically connected to the shift register 11 and the scan line S ₁₂ , and the shift register 13 is shifted. The bit register 12 and the scan line S _{13 are} electrically connected.

In the prior art, the output of the first stage shift register is used as the start signal of the next stage shift register. Thereto, the output of the shift register 11 transmits in addition to the scan lines S _11, and more as a starting signal of shift register 12.

However, the shift registers 11 to 13 are electrically connected to the load (for example) Such as scan lines and thin film transistors, etc., so that the output waveform of the shift register of the later stage will produce a more serious RC delay effect. When driving a large-sized, high-resolution display device, the number of shift registers required will increase. As a result, the shift register of the later stage may be in a malfunction.

In addition, in a large-sized, high-resolution display device, the signal transmitted by each scan line will need to drive a larger number of thin film transistors, so the output power of the current shift register will be insufficient.

Therefore, how to provide a shift temporary storage unit, a scan driving circuit, a display device, and a shift register unit control method capable of avoiding a malfunction of the shift register and increasing its output power is one of the current important topics. .

In view of the above problems, an object of the present invention is to provide a shift register unit, a scan drive circuit, a display device, and a shift register unit control method capable of avoiding a malfunction of a shift register and increasing its output power.

To achieve the above object, the present invention provides a shift temporary storage unit that is used in conjunction with a first scan line. The shift register unit includes a first pre-boost element and a first boost element. The first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a boosting signal having a first level. The first pre-boosting component outputs a boosting signal having a second level according to a first clock signal and a first level of the boosting signal. First boosting element and first pre-boosting element and first scan line electrical The connection generates a boost signal having a third level according to a second clock signal and a second level boost signal. The first boosting component causes the first scan line to transmit a first scan signal according to the second clock signal and the third level boost signal.

To achieve the above object, the present invention provides a method for controlling a shift register unit, which is applied in conjunction with a first scan line. The shift register unit has a first pre-boosting component and a first boosting component, and the first boosting component is electrically connected to the first pre-boosting component and the first scan line. The control method of the shift register unit includes the following steps: outputting, by the first pre-boosting component, a second displacement control signal according to a first displacement control signal, and generating a boost signal having a first level; The pre-boosting component causes the first pre-boosting component to output a boosting signal having a second level according to a first clock signal and a first level of the boosting signal; The second clock signal and the second level boost signal generate a boost signal having a third level; and the first boosting element is based on the second clock signal and the third level boost signal, The first scan line transmits a first scan signal.

To achieve the above object, the present invention provides a method for controlling a shift register unit, which is applied in conjunction with a first scan line. The shift register unit has a first pre-boost element and a first boost element. The first pre-boosting element has a first transistor, a second transistor, a third transistor, and a fourth transistor. Wherein one of the first transistor has a drain or a source electrically connected to a gate thereof, the second crystal is electrically connected to the first transistor, the third crystal and the first transistor and the second transistor Electrical connection, fourth The crystal is electrically connected to the first transistor, the second transistor, and the first boosting element, and a drain or a source thereof is electrically connected to a gate thereof. The first boosting element has a fifth transistor electrically connected to the fourth transistor. The control method of the shift register unit includes the steps of: inputting a first voltage control signal of a high voltage level to turn on the first transistor and the third transistor at a first time, and outputting the first pre-boost component a second displacement control signal, and generating a boost signal having a first level to one of the gates of the fifth transistor; and at a second time, inputting a first clock signal of a high voltage level, The first pre-boosting component outputs a boost signal having a second level to a gate of the fifth transistor; and at a third time, inputting a second clock signal of a high voltage level, by the first The pre-boost element outputs a boost signal having a third level to the gate of the fifth transistor.

To achieve the above object, the present invention provides a scan driving circuit that is used in conjunction with a first scan line, the scan drive circuit including a shift register unit. The shift register unit is electrically connected to the first scan line and has a first pre-boosting component and a first boosting component. The first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a boosting signal having a first level. The first pre-boosting component outputs a boosting signal having a second level according to the first clock signal and the first level of the boosting signal. The first boosting component is electrically connected to the first pre-boosting component and the first scan line, and generates a boost signal having a third level according to a second clock signal and a boost signal of the second level. The first boosting component causes the first scan line to output a first scan signal according to the second clock signal and the third level boost signal.

To achieve the above object, the present invention provides a display device including a display panel, a data driving circuit, and a scan driving circuit. The data driving circuit is electrically connected to the display panel by a plurality of data lines. The scan driving circuit is electrically connected to the display panel by at least one first scan line, and has a shift register unit. The shift register unit has a first pre-boost element and a first boost element. The first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a boosting signal having a first level. The first pre-boosting component outputs a boosting signal having a second level according to the first clock signal and the first level of the boosting signal. The first boosting component is electrically connected to the first pre-boosting component and the first scan line, and generates a boost signal having a third level according to a second clock signal and a boost signal of the second level. The first boosting component causes the first scan line to transmit a first scan signal according to the second clock signal and the third level boost signal.

According to the present invention, the shift temporary storage unit, the scan driving circuit, the display device and the shift temporary storage unit control method are the first displacement control signals output by the pre-boosting component as the next-level pre-control The start signal of the boost component. Compared with the prior art, the first displacement control signal of the embodiment is directly transmitted to the next-stage pre-boosting component. Therefore, the first displacement control signal does not generate a time delay effect, and the pre-boost components of each stage are output. The second displacement control signal can normally activate the corresponding boosting component. In addition, the voltage level of a gate terminal of the transistor of the shift register unit electrically connected to the scan line is raised from the first level to the third level by the control method of the shift register unit of the present invention. Bit to increase the boost component output power, which in turn drives a larger load.

Hereinafter, a method of controlling a shift register unit, a scan driving circuit, a display device, and a shift register unit according to a plurality of embodiments of the present invention will be described with reference to the related drawings.

Referring to FIG. 2, the display device 2 of the preferred embodiment of the present invention includes a display panel 3, a data driving circuit 4, and a scan driving circuit 5. The scan driving circuit 5 is electrically connected to the display panel 3 by the plurality of scanning lines S ₂₁ to S _2m , and the data driving circuit 4 is electrically connected to the display panel 3 by the plurality of data lines D ₂₁ to D _2n .

Referring to FIG. 3, the scan driving circuit 5 of the present embodiment includes a shift register unit 51, which is used in combination with at least one of the scan lines S ₂₁ to S _2m . The shift register unit 51 has a first pre-boosting element 511 and a first boosting element 512. The shift register unit 51 of the embodiment further includes a second pre-boosting component 513, a second boosting component 514, a third pre-boosting component 515, a third boosting component 516, and a fourth pre- A boosting element 517 and a fourth boosting element 518. The first boosting component 512 is electrically connected to the first pre-boosting component 511 and the scan line S ₂₁ , the second pre-boosting component 513 is electrically connected to the first pre-boosting component 511 , and the second boosting component 514 is electrically connected to the first boosting component 511 . the first pre-boosting element 511, a second pre-boosting element 513, element 512 and first booster ₂₂ is electrically connected to the scan line S. The third pre-boosting component 515 is electrically connected to the second pre-boosting component 513, and the third boosting component 516 and the second pre-boosting component 513, the third pre-boosting component 515, the second boosting component 514, and the scan. Line S _{23 is} electrically connected. The fourth pre-boosting component 517 is electrically connected to the third pre-boosting component 515, and the fourth boosting component 518 and the third pre-boosting component 515, the fourth pre-boosting component 517, the third boosting component 516, and the scan. Line S _{24 is} electrically connected. It is well known to those skilled in the art that the number of pre-boost elements and boost elements can be increased depending on their needs.

In this embodiment, the shift register unit 51 can be applied in conjunction with four clocks. The first pre-boosting component 511 and the fourth boosting component 518 are applied together with the first clock signal CK ₂₁ , and the first boosting component 512 and the second pre-boosting component 513 and the second clock signal CK _{22 .} The second boosting component 514 and the third pre-boosting component 515 are used in conjunction with the third clock signal CK ₂₃ , and the third boosting component 516 and the fourth pre-boosting component 517 and the fourth clock signal CK _{24 .} With the application.

In addition, the second pre-boosting component 513, the third pre-boosting component 515, and the fourth pre-boosting component 517 can have the same circuit as the first pre-boosting component 511, and the second boosting component 514, the third booster The voltage element 516 and the fourth boost element 518 can have the same circuitry as the first boost element 512. To simplify the description, the internal circuit architecture will be described below by taking the first pre-boosting component 511 and the first boosting component 512 as an example.

First embodiment

Referring to FIG. 4, it is a shift temporary storage unit 51 according to the first embodiment of the present invention. The first pre-boosting element 511 includes a transistor T ₁₀₁ , a transistor T ₁₀₂ , a transistor T _{103 ,} and A transistor T ₁₀₄ . Wherein, one of the gates or the source of the transistor T ₁₀₁ is electrically connected to a gate thereof, and the transistor T ₁₀₃ is electrically connected to the transistor T ₁₀₁ , the transistor T ₁₀₂ and the transistor T ₁₀₄ , and the transistor T ₁₀₄ One of the drains or one source is electrically connected to its gate. The first pre-boosting element 511 of this embodiment further includes a transistor T ₁₀₅ electrically connected to the transistor T ₁₀₃ .

The first boosting component 512 includes a transistor T _106. In the embodiment, the first boosting component 512 further includes a transistor T ₁₀₇ , a transistor T ₁₀₈ , a transistor T ₁₀₉ , and a transistor T _{110 .} And a transistor T ₁₁₁ . The transistor T ₁₀₆ is electrically connected to the transistor T ₁₀₄ , the transistor T ₁₀₈ , the transistor T ₁₀₉ , the transistor T _{110 ,} and the transistor T ₁₁₁ , and the transistor T ₁₀₇ is electrically connected to the transistor T ₁₀₈ .

Referring to Figure, t _11, a first displacement control signal output 5 A ₁₁ at a first time a high voltage level, the second scan line S ₂₂ transmits a low voltage level of the second scan signal B ₁₂ A second clock signal CK ₂₂ outputs a low voltage level. At this time, the transistor T ₁₀₂ , the transistor T _{105 ,} and the transistor T ₁₁₀ are in an off state, and the transistor T ₁₀₁ , the transistor T _{103 ,} and the transistor T ₁₀₄ are in an on state. P _a node of the node and the node voltage V _Pa P _b of the node voltage V _Pb are as _{follows: V Pa = V DD -V th} , V Pb = V DD -2 × V th.

The voltage difference between the high voltage level and the low voltage level of the first displacement control signal A ₁₁ is V _DD , and the threshold voltage of the transistor T ₁₀₁ and the transistor T ₁₀₄ is V _th , respectively. The node voltage V _Pa of the node P _{a is} the voltage of the gate terminal of the transistor T ₁₀₃ , and the node voltage V _Pb of the node P _{b is} the voltage of the gate terminal of the transistor T ₁₀₆ . In this embodiment, the first displacement control signal A ₁₁ can be a start signal. Thereto, transistor T having a gate terminal ₁₀₆ of the first level L ₁ of the node voltage V _Pb, In this case, the first level of the voltage level L ₁ are as _{follows: L 1 = V Pb = V} Pb = V _DD -2 × V _th .

At the same time, the shift register unit 51 outputs a scan signal B ₁₁ , which is the second clock signal CK ₂₂ , and therefore, the scan signal B ₁₁ is at a low voltage level.

In addition, a second displacement control signal A _{12 of} a low voltage level is output via the transistor T ₁₀₃ and transmitted to the second pre-boosting element 513. In this embodiment, the first clock signal CK _{21 is} the second displacement control signal A ₁₂ .

During a second time t ₁₂ , the first displacement control signal A ₁₁ outputs a low voltage level, and the second scan line S ₂₂ transmits a low voltage level second scan signal B ₁₂ , the first clock signal CK ₂₁ The high voltage level is output, and the second clock signal CK ₂₂ outputs a low voltage level. At this time, the transistor T ₁₀₂ , the transistor T _{105 ,} and the transistor T ₁₁₀ are in an off state, and the transistor T ₁₀₁ , the transistor T _{103 ,} and the transistor T ₁₀₄ are in an on state. The node voltage V _Pa of the node P _a is V _DD -V _th , and the capacitor C ₁₁ is electrically connected to the transistor T ₁₀₃ and the transistor T ₁₀₅ , and the voltage level of the node voltage is raised by ΔV _pa , at this time, the node The node voltage V _{Pa of} P _a and the node voltage V _{Pb of the} node P _b are as follows: V _Pa = V _DD - V _th , V _Pb = V _DD - 2 × V _th + ΔV _Pa .

Where ΔV _pa is the voltage difference between the high voltage level and the low voltage level of the first clock signal CK ₂₁ . Thereto, transistor T having a gate terminal ₁₀₆ of a second level L ₂ of the node voltage V _Pb, In this case, second level L ₂ of the node voltage V _Pb as follows: V _Pb = V _DD -2 × V _th +ΔV _Pa .

At the same time, the shift register unit 51 outputs a scan signal B ₁₁ , which is the second clock signal CK ₂₂ , and therefore, the scan signal B ₁₁ is at a low voltage level.

In addition, a second displacement control signal A _{12 of} a high voltage level is output via the transistor T ₁₀₃ and transmitted to the second pre-boosting element 513.

During a third time t ₁₃ , the first displacement control signal A ₁₁ outputs a low voltage level, and the second scan line S ₂₂ transmits a low voltage level second scan signal B ₁₂ , the first clock signal CK ₂₁ The low voltage level is output, and the second clock signal CK ₂₂ outputs a high voltage level. At this time, the transistor T ₁₀₂ , the transistor T _{105 ,} and the transistor T ₁₁₀ are in an off state, and the transistor T ₁₀₁ , the transistor T _{103 ,} and the transistor T ₁₀₄ are in an on state. In this case, the node P _a node and the node voltage V _Pa P _b of the node voltage V _Pb are as _{follows: V Pa = V DD -V th} + △ V Pa, V Pb = V DD -2 × V th + △ V _Pa .

Moreover, one end of the capacitor C ₁₂ is electrically connected to the transistor T ₁₀₆ and the transistor T ₁₁₀ , and the voltage level of the node voltage is increased by ΔV _Pb . At this time, the node voltage V _{Pb of the} node P _b is as follows: V _Pb =V _DD -2 × V _th +ΔV _Pa +ΔV _Pb .

Where ΔV _Pb is the voltage difference between the high voltage level and the low voltage level of the second clock signal CK ₂₂ . Thereto, transistor T having a gate terminal ₁₀₆ of the third level L ₃ of the node voltage V _Pb, In this case, the node L ₃ third level of voltage V _Pb as follows: V _Pb = V _DD -2 × V _th +ΔV _pa +ΔV _pb .

At the same time, the shift register unit 51 outputs a scan signal B ₁₁ , which is the second clock signal CK ₂₂ , and therefore, the scan signal B ₁₁ is at a high voltage level.

In addition, a second displacement control signal A _{12 of} a low voltage level is output via the transistor T ₁₀₃ and transmitted to the second pre-boosting element 513.

During a fourth time t ₁₄ , the first displacement control signal A ₁₁ outputs a low voltage level, and the second scan line S ₂₂ transmits a second scan signal B _{12 of a} high voltage level, and the first clock signal CK ₂₁ outputs a low output. At the voltage level, the second clock signal CK ₂₂ outputs a low voltage level. At this time, the transistor T ₁₀₂ , the transistor T ₁₀₅ , the transistor T _{109 ,} and the transistor T ₁₁₀ are in an on state. At this time, the node P _a is discharged via the transistor T ₁₀₂ such that its node voltage is the ground voltage V _SS . Node P _b via the transistor T ₁₀₉ T ₁₀₈ and discharge transistor, such that the node voltage is the ground voltage V _SS node voltage VP _b of the ground voltage V _SS.

Compared with the prior art, the first pre-boosting component 511 of the present embodiment outputs the second displacement control signal A ₁₂ according to the first displacement control signal A ₁₁ and transmits it to the second pre-boosting component 513.

As described above, the first displacement control signal outputted by the pre-boosting component of the embodiment is used as the start signal of the next-stage pre-boosting component. Compared with the prior art, the first displacement control signal of the embodiment is directly transmitted to the next-stage pre-boosting component. Therefore, the first displacement control signal does not generate a time delay effect, and the pre-boost components of each stage are output. The second displacement control signal can normally activate the corresponding boosting component.

In addition, the voltage level of the gate terminal of the transistor T ₁₀₆ is raised from the first level to the third level. Therefore, the shift register unit 51 of the embodiment is driven by increasing the output power of the boosting element. Larger load.

Please refer to FIG. 6 , which is a shifting temporary embodiment of the first embodiment of the present invention. The control method of the storage unit includes steps W11 to W14.

In step W11, the first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a voltage signal having a first level.

In step W12, the first pre-boosting component outputs a voltage signal having a second level according to a voltage signal of the first clock signal and the first level.

In step W13, the first boosting component generates a voltage signal having a third level according to a voltage signal of the second clock signal and the second level.

In step W14, the first boosting component outputs a first scan signal according to the voltage signals of the second clock signal and the third level.

The detailed control method has been described in detail in the above embodiments, and thus will not be further described herein.

Referring to FIG. 7, it is a control method of the shift temporary storage unit according to the first embodiment of the present invention, which includes steps W21 to W23. The shift register unit is coupled to a first scan line and has a first pre-boost element and a first boost element. The first pre-boosting element has a first transistor, a second transistor, a third transistor, and a fourth transistor. One of the first transistor has a drain or a source electrically connected to a gate thereof, the second crystal is electrically connected to the first transistor, and the third crystal and the first transistor and the second transistor are electrically connected connection. The fourth crystal is electrically connected to the first transistor, the second transistor and the first boosting element, and a drain or a source thereof is electrically connected to the gate. The first boosting element has a The fourth transistor is electrically connected to the fifth transistor. The control method control method of the shift register unit includes steps W21 to W23.

Step W21, in a first time, inputting a first voltage control signal of a high voltage level to turn on the first transistor and the third transistor, and causing the first pre-boosting component to output a second displacement control signal, and A voltage signal having a first level is generated to one of the gates of the fifth transistor.

Step W22, in a second time, inputting a first clock signal of a high voltage level, and outputting, by the first pre-boosting component, a voltage signal having a second level to a gate of the fifth transistor.

Step W23, in a third time, inputting a second clock signal of a high voltage level, and outputting, by the first pre-boosting component, a voltage signal having a third level to the fifth transistor.

The detailed control method has been described in detail in the above embodiments, and thus will not be further described herein.

Second embodiment

Referring to FIG. 8, the shift register unit 51a of the second embodiment of the present invention includes a first pre-boosting element 511a and a first boosting element 512a. The first pre-boosting element 511a includes a transistor T ₂₀₁ , a transistor T _{202 ,} and a transistor T ₂₀₃ . The first boosting element 512a includes a transistor T ₂₀₆ , a transistor T _{209 ,} and a transistor T ₂₁₀ .

In addition, the first pre-boosting element 511a and the first boosting element 512a of the shift register unit 51a have the same technical features as the first pre-boosting element 511 and the first boosting element 512 in the first embodiment. Function, so it will not be repeated here. The transistor T ₂₀₁ , the transistor T _{202 ,} and the transistor T _{203 of the} first pre-boosting element 511a have the same technical features and functions as the transistor T ₁₀₁ , the transistor T _{102 ,} and the transistor T ₁₀₃ in the first embodiment. Therefore, it will not be repeated here. The transistor T ₂₀₆ , the transistor T _{209 ,} and the transistor T _{210 of the} first boosting element 512a have the same technical features and functions as the transistor T ₁₀₆ , the transistor T _{109 ,} and the transistor T _11o in the first embodiment. Therefore, it will not be repeated here.

Shift register unit 51a of the present embodiment comprises a capacitor C _23, which system and the transistor T ₂₀₆ is electrically connected. In addition, it is well known to those skilled in the art that the operation of the shift register unit 51a of the present embodiment can be deduced by the description of the first embodiment, and details are not described herein again.

Third embodiment

In this embodiment, the shift register unit is not limited to be applied to the four clock signals. Referring to FIG. 9, the shift register unit 61 of the present embodiment can be combined with three clocks CK ₃₁ ~ CK ₃₃ works with the application. The shift register unit 61 has a first pre-boosting element 611 and a first boosting element 612. The shift register unit 61 of the embodiment further includes a second pre-boosting component 613, a second boosting component 614, a third pre-boosting component 615, and a third boosting component 616.

The first pre-boosting component 611, the first boosting component 612, the second pre-boosting component 613, the second boosting component 614, the third pre-boosting component 615, and a third boosting device of the shift register unit 61 The component 616 and the first pre-boosting component 511, the first boosting component 512, the second pre-boosting component 513, the second boosting component 514, the third pre-boosting component 515, and a third liter in the above embodiment The pressure element 516 has the same technical features and functions, so it is not Let me repeat them.

Referring to FIG. 10, the first pre-boosting element 611 includes a transistor T ₃₀₁ , a transistor T ₃₀₂ , a transistor T ₃₀₃ , a transistor T _{304 ,} and a transistor T ₃₀₅ . The first boosting element 612 includes a transistor T ₃₀₆ , a transistor T ₃₀₇ , a transistor T ₃₀₈ , a transistor T ₃₀₉ , a transistor T _{310 ,} and a transistor T ₃₁₁ .

In addition, the first pre-boosting component 611 and the first boosting component 612 of the shift register unit 61 have the same technical features as the first pre-boosting component 511 and the first boosting component 512 in the first embodiment. Function, so it will not be repeated here. The transistor T ₃₀₁ , the transistor T ₃₀₂ , the transistor T ₃₀₃ , the transistor T _{304 ,} and the transistor T _{305 of the} first pre-boosting element 611 are different from the transistor T ₁₀₁ , the transistor T ₁₀₂ , and the electric in the first embodiment. The crystal T ₁₀₃ , the transistor T _{104 ,} and the transistor T ₁₀₅ have the same technical features and functions, and thus will not be further described herein. The transistor T _{306 of the} first boosting element 612, the transistor T ₃₀₇ , the transistor T ₃₀₈ , the transistor T ₃₀₉ , the transistor T _{310 ,} and the transistor T _{311 are the} same as the transistor T ₁₀₆ and the transistor in the first embodiment. T ₁₀₇ , transistor T ₁₀₈ , transistor T ₁₀₉ , transistor T _{110 ,} and transistor T ₁₁₁ have the same technical features and functions, and thus will not be further described herein.

The shift register unit 61 of the present embodiment further includes a transistor T ₃₁₂ and a transistor T _313. The transistor T ₃₁₂ is electrically connected to the transistor T ₃₀₆ and is controlled to be turned on according to the third clock signal CK ₃₃ . Or deadline. The transistor T ₃₁₃ is electrically connected to the transistor T ₃₀₆ and is controlled to be turned on or off according to the first clock signal CK ₃₁ . In addition, it is well known to those skilled in the art that the operation of the shift register unit 61 of the present embodiment can be derived through the description of the above embodiments, and details are not described herein again.

Fourth embodiment

Referring to FIG. 11, the shift register unit 61a of the present embodiment can be applied in combination with three clocks CK ₃₁ CK CK ₃₃ . The shift register unit 61a has a first pre-boosting element 611a and a first boosting element 612a.

The first pre-boosting element 611a includes a transistor T ₄₀₁ , a transistor T ₄₀₂ , a transistor T ₄₀₃ , a transistor T _{404 ,} and a transistor T ₄₀₅ . The first boosting element 612a includes a transistor T ₄₀₆ , a transistor T ₄₀₇ , a transistor T ₄₀₈ , a transistor T ₄₀₉ , a transistor T _{410 ,} and a transistor T ₄₁₁ .

In addition, the first pre-boosting element 611a and the first boosting element 612a of the shift register unit 61a have the same technical features and functions as the first pre-boosting element 611 and the first boosting element 612 in the above embodiment. Therefore, it will not be repeated here. The transistor T _{401 of the} first pre-boosting element 611a, the transistor T ₄₀₂ , the transistor T ₄₀₃ , the transistor T ₄₀₄ and the transistor T _{405 are the} same as the transistor T ₁₀₁ , the transistor T ₁₀₂ , and the electric in the first embodiment. The crystal T ₁₀₃ , the transistor T _{104 ,} and the transistor T ₁₀₅ have the same technical features and functions, and thus will not be further described herein. The transistor T _{406 of the} first boosting element 612a, the transistor T ₄₀₇ , the transistor T ₄₀₈ , the transistor T ₄₀₉ , the transistor T _{410 ,} and the transistor T _{411 are the} same as the transistor T ₁₀₆ and the transistor in the first embodiment. T ₁₀₇ , transistor T ₁₀₈ , transistor T ₁₀₉ , transistor T _{110 ,} and transistor T ₁₁₁ have the same technical features and functions, and thus will not be further described herein.

In addition, it is well known to those skilled in the art that the operation of the shift register unit 61 of the present embodiment can be derived from the description of the above embodiments. No longer.

In addition, in order to improve the conventional problems, the present invention provides another shift register unit 71. Referring to FIG. 12, the shift register unit 71 of the present embodiment is used in conjunction with the clock signals CK ₄₁ CK CK ₄₂ . The shift register unit 71 includes a transistor T ₅₀₁ , a transistor T ₅₀₂ , and a The transistor T ₅₀₃ , a transistor T ₅₀₄ , a transistor T ₅₀₅ , a transistor T ₅₀₆ , a transistor T _{507 ,} and a transistor T ₅₀₈ .

One of the gates or a source of the transistor T ₅₀₁ is electrically connected to a gate thereof, the transistor T ₅₀₃ and the transistor T ₅₀₁ , the transistor T ₅₀₂ , the transistor T ₅₀₄ , the transistor T _{5o5 ,} and a capacitor C _{53 .} Electrical connection. The scan signal B ₁₂ controls the transistor T ₅₀₂ and the transistor T _{504 to be} turned on or off. One of the gates or a source of the transistor T ₅₀₅ is electrically connected to a gate thereof, and the transistor T ₅₀₇ and the transistor T ₅₀₅ , the transistor T ₅₀₆ , the transistor T ₅₀₇ , the transistor T _{508 ,} and a capacitor C ₅₃ Electrical connection. The scan signal B ₁₃ controls the transistor T ₅₀₆ and the transistor T _{508 to be} turned on or off. A capacitor C ₅₁ and a capacitor C ₅₂ are parasitic capacitances of the transistor T ₅₀₃ and the transistor T ₅₀₇ , respectively.

In summary, the shift temporary storage unit, the scan driving circuit, the display device, and the shift register unit control method according to the present invention are the first displacement control signals output by the pre-boosting component as the next-stage pre-elevation The starting signal of the pressure element. Compared with the prior art, the first displacement control signal of the embodiment is directly transmitted to the next-stage pre-boosting component. Therefore, the first displacement control signal does not generate a time delay effect, and the pre-boost components of each stage are output. The second displacement control signal can normally activate the corresponding boosting component. In addition, the transistor of the shift register unit electrically connected to the scan line has a gate The extreme voltage level is raised from the first level to the third level by the control method of the shift register unit of the present invention to increase the output power of the boosting element, thereby driving a larger load.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1, 51, 51a, 61, 61a, 71‧‧ ‧ shift temporary storage unit

11, 12, 13‧‧‧ shift register

2‧‧‧Display device

3‧‧‧ display panel

4‧‧‧Data Drive Circuit

5‧‧‧Scan drive circuit

511, 511a, 611, 611a‧‧‧ first pre-boost components

512, 512a, 612, 612a‧‧‧ first boosting components

513, 613‧‧‧second pre-boosting components

514, 614‧‧‧ second boosting element

515, 615‧‧‧ third pre-boosting components

516, 616‧‧‧ third boosting element

517‧‧‧fourth pre-boosting component

518‧‧‧4th boosting element

A ₁₁ , A ₁₂ ‧‧‧ Displacement control signals

B ₁₁ , B ₁₂ , B ₁₃ ‧ ‧ scan signals

CK ₂₁ ~ CK ₂₄ , CK ₃₁ ~ CK ₃₃ ‧‧‧ clock signal

D ₂₁ ~D _2n ‧‧‧ data line

S ₁₁ ~S ₁₃ , S ₂₁ ~S _2m ‧‧‧ scan line

T ₁₀₁ ~T ₅₀₈ ‧‧‧O crystal

VP _b ‧‧‧ node voltage

V _SS ‧‧‧ Grounding voltage

W11~W14, W21~W23‧‧‧ steps

1 is a schematic diagram of a conventional shift register unit; FIG. 2 is a schematic diagram of a display device according to a preferred embodiment of the present invention; FIG. 3 is a schematic diagram of a shift register unit according to a preferred embodiment of the present invention; FIG. 5 is a timing diagram of a shift temporary storage unit according to a first embodiment of the present invention; FIG. 6 is a timing shifting diagram of a shift temporary storage unit according to a first embodiment of the present invention; FIG. 7 is a flowchart of another control step of the shift temporary storage unit according to the first embodiment of the present invention; FIG. 8 is a schematic diagram of the shift temporary storage unit according to the second embodiment of the present invention; FIG. 9 to FIG. FIG. 11 is a schematic diagram of a shift temporary storage unit according to a fourth embodiment of the present invention; and FIG. 12 is a shift temporary storage unit according to a preferred embodiment of the present invention; Schematic diagram.

51‧‧‧Shift register unit

511‧‧‧First pre-boosting element

512‧‧‧First boosting element

513‧‧‧Second pre-boosting element

514‧‧‧Second boosting element

515‧‧‧ Third pre-boosting element

516‧‧‧ Third boosting element

517‧‧‧fourth pre-boosting component

518‧‧‧4th boosting element

S ₂₁ , S ₂₂ , S ₂₃ , S ₂₄ ‧‧‧ scan lines

CK ₂₁ , CK ₂₂ , CK ₂₃ , CK ₂₄ ‧ ‧ clock signal

Claims (24)

A shift temporary storage unit is configured to cooperate with a first scan line, the shift temporary storage unit includes: a first pre-boost component, and outputs a second displacement control signal according to a first displacement control signal, and generates a voltage signal of the first level, the first pre-boosting component outputs a voltage signal having a second level according to a first clock signal and the voltage signal of the first level; and a first boosting component And electrically connecting to the first pre-boosting component and the first scan line, generating a voltage signal having a third level according to a voltage signal of the second clock signal and the second level, the first liter The voltage component transmits the first scan signal to the first scan line according to the voltage signals of the second clock signal and the third level. The shift register unit of claim 1, wherein the first displacement control signal is a start signal. The shift temporary storage unit of claim 1, further comprising: a second pre-boosting component electrically connected to the first pre-boosting component, and outputting a third according to the second displacement control signal Displacement control signal, and generating a voltage signal having the first level, the second pre-boosting component outputting a voltage signal having the second level according to the second clock signal and the voltage signal of the first level; And a second boosting component electrically coupled to the first pre-boosting component, the second pre-boosting component, the first boosting component, and a second scan line, according to a third clock signal and the Second level voltage signal A voltage signal having the third level is generated, and the second boosting component causes the second scan line to transmit a second scan signal according to the voltage signals of the third clock signal and the third level. The shifting temporary storage unit of claim 3, wherein the first pre-boosting element comprises: a first transistor, wherein a drain or a source is electrically connected to a gate thereof; The second crystal is electrically connected to the first transistor, wherein the second scan signal controls the second crystal to be turned on or off; and a third crystal is electrically connected to the first transistor and the second transistor And a fourth crystal, electrically connected to the first transistor, the second transistor and the first boosting component, and one of the drains or the source is electrically connected to a gate thereof . The shift register unit of claim 4, wherein the first boosting element comprises: a fifth crystal, electrically connected to the fourth crystal, according to the second clock signal and the The third level voltage signal outputs the first scan signal via the fifth crystal. The shift register unit of claim 1, wherein the second level is between the first level and the third level. A scan driving circuit is used in conjunction with a first scan line. The scan driving circuit includes: a shift register unit electrically connected to the first scan line, and having: a first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a voltage signal having a first level, the first pre-boosting component is based on the first clock signal and The voltage signal of the first level outputs a voltage signal having a second level; and a first boosting element is electrically connected to the first pre-boosting element and the first scanning line, according to a second time The voltage signal and the voltage signal of the second level generate a voltage signal having a third level, and the first boosting component causes the first signal according to the voltage signal of the second clock signal and the third level The scan line transmits a first scan signal. The scan driving circuit of claim 7, wherein the first displacement control signal is a start signal. The scan driving circuit of claim 7, wherein the shift register unit further comprises: a second pre-boosting component electrically connected to the first pre-boosting component, according to the second displacement control The signal outputs a third displacement control signal, and generates a voltage signal having the first level. The second pre-boosting component has the second standard according to the second clock signal and the voltage signal output of the first level. a voltage signal of the bit; and a second boosting component electrically connected to the first pre-boosting component, the second pre-boosting component, the first boosting component, and a second scan line, according to a third The clock signal and the voltage signal of the second level generate a voltage signal having the third level, and the second boosting element And transmitting, according to the third clock signal and the voltage signal of the third level, the second scan line to transmit a second scan signal. The scan driving circuit of claim 9, wherein the first pre-boosting element comprises: a first transistor, wherein a drain or a source is electrically connected to a gate thereof; a first crystal electrically connected to the first transistor, wherein the second scan signal controls the second crystal to be turned on or off; and a third crystal is electrically connected to the first transistor and the second transistor And a fourth crystal, electrically connected to the first transistor, the second transistor, and the first boosting element, and a drain or a source thereof is electrically connected to a gate thereof. The scan driving circuit of claim 10, wherein the first boosting element comprises: a fifth crystal, electrically connected to the fourth crystal, according to the second clock signal and the third The voltage signal of the level outputs the first scan signal via the fifth crystal. The scan driving circuit of claim 7, wherein the second level is between the first level and the third level. A display device comprising: a display panel; a data driving circuit electrically connected to the display panel by a plurality of data lines; a scan driving circuit is electrically connected to the display panel by at least one first scan line, and has: a shift temporary storage unit having: a first pre-boosting component, and outputting a signal according to a first displacement control signal The second displacement control signal generates a voltage signal having a first level, and the first pre-boosting component outputs a voltage signal having a second level according to the first clock signal and the voltage signal of the first level And a first boosting component electrically connected to the first pre-boosting component and the first scan line, and generating a third level according to a voltage signal of the second clock signal and the second level The first boosting component transmits the first scan signal to the first scan line according to the voltage signals of the second clock signal and the third level. The display device of claim 13, wherein the first displacement control signal is a start signal. The display device of claim 13, wherein the shift register unit further comprises: a second pre-boosting component electrically connected to the first pre-boosting component, according to the second displacement control signal And outputting a third displacement control signal, and generating a voltage signal having the first level, the second pre-boosting component having the second level according to the second clock signal and the voltage signal output of the first level a voltage signal; and a second boosting component, the first pre-boosting component, the second pre-elevating component The voltage component, the first boosting component and the second scan line are electrically connected to generate a voltage signal having the third level according to a third clock signal and the voltage signal of the second level, the second liter The voltage component transmits the second scan signal according to the voltage signal of the third clock signal and the third level. The display device of claim 15, wherein the first pre-boosting element comprises: a first transistor, wherein a drain or a source is electrically connected to a gate thereof; The second transistor is electrically connected to the first transistor, and the second transistor is electrically connected to the first transistor and the second transistor; And a fourth crystal, electrically connected to the first transistor, the second transistor and the first boosting element, and a drain or a source thereof is electrically connected to a gate thereof. The display device of claim 16, wherein the first boosting element comprises: a fifth crystal, electrically connected to the fourth crystal, according to the second clock signal and the third standard The voltage signal of the bit outputs the first scan signal via the fifth crystal. The display device of claim 13, wherein the second level is between the first level and the third level. A control method for shifting temporary storage unit, matched with a first scan line The first temporary boosting component is electrically connected to the first pre-boosting component and the first scan line, and the first boosting component is electrically connected to the first pre-boosting component. The method includes the following steps: the first pre-boosting component outputs a second displacement control signal according to a first displacement control signal, and generates a voltage signal having a first level; and the first pre-boosting component is based on the first pre-boosting component a first clock signal and a voltage signal of the first level, wherein the first pre-boosting component outputs a voltage signal having a second level; and the first boosting component is based on a second clock signal and The voltage signal of the second level generates a voltage signal having a third level; and the first boosting element causes the first scan according to the voltage signals of the second clock signal and the third level The line transmits a first scan signal. The control method of claim 19, further comprising: outputting, by a second pre-boosting component, a third displacement control signal according to the second displacement control signal, and generating a voltage signal having the first level The second pre-boosting component outputs a voltage signal having the second level according to the voltage signal of the second clock signal and the first level, and the second pre-boosting component outputs a voltage signal having the second level; The boosting component generates a voltage signal having the third level according to a third clock signal and a voltage signal of the second level; And causing, by the second boosting component, the second scan line to transmit a second scan signal according to the voltage signals of the third clock signal and the third level. The control method of claim 19, wherein the second level is between the first level and the third level. A control method for shifting a temporary storage unit, which is matched with a first scan line, the shift register unit has a first pre-boosting component and a first boosting component, and the first pre-boosting component has a a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein one of the first transistor has a drain or a source electrically connected to a gate thereof, the second transistor Electrically connecting with the first transistor, the third crystal is electrically connected to the first transistor and the second transistor, the fourth crystal and the first transistor, the second transistor, and the The first boosting element is electrically connected, and a drain or a source thereof is electrically connected to a gate thereof. The first boosting element has a fifth transistor electrically connected to the fourth transistor. The control method includes the following steps: at a first time, the first displacement control signal inputting a high voltage level turns on the first transistor and the third transistor, and the first pre-boost component outputs a Second shifting the control signal and generating a voltage signal having a first level to the fifth One transistor gate; at a second time, a high level input voltage is one of a first clock signal having a second power level of the output element of the first pre-boost Pressing a signal to the gate of the fifth transistor; and, at a third time, inputting a second clock signal of a high voltage level, the first pre-boost component output having a third level The voltage signal is to the gate of the fifth transistor. The control method of claim 22, further comprising: providing the gate-discharge path of the fifth transistor at a fourth time. The control method of claim 22, wherein the second level is between the first level and the third level.