TWI395276B - Chip can be expanded to control the number of signal burner - Google Patents

Description

Chip pre-burning machine that can expand the number of control signals

The invention relates to a firmware structure of a pre-fired logic chip, in particular to a wafer pre-burning machine table suitable for expanding the number of control signals.

Generally, the memory chip of the conventional memory wafer has a much smaller number of pins than the conventional logic chip. Therefore, in the pre-burning operation of the memory chip, the conventional standard memory chip is pre-fired (Burn- In) The number of memory chip pins that the machine can output to the programmable control signal at one time does not need to be too much.

As shown in FIG. 1 , it is a schematic diagram of a conventional interface card and a pre-burning board. The interface card 9 on the standard memory chip pre-burning machine table includes a plurality of output pins 91 and a plurality of output pins. 91 is further electrically connected to the pre-burning plate 90 to pre-sinter the data in the interface card 9 to the memory chip 92 of the pre-burning plate 90 in parallel.

On the contrary, the general logic chip is different from the above memory chip, and the logic chip has hundreds of pins. Therefore, the conventional standard logic chip burn-in machine needs hundreds of programmable control signals. Bit for logic chip burn-in.

Therefore, if the pre-burning machine used for the memory chip is to be modified into a logic chip pre-burning machine, the original memory chip pre-burning machine should have dozens of output pins, and increase its The number is changed to hundreds of output pins of the logic chip, and the internal hardware must also be modified accordingly. The preparation work before the burn-in is lengthened, thus increasing the time, labor, and hardware costs.

The invention relates to a wafer burn in machine capable of expanding the number of control signals, comprising a first bus bar, a second bus bar, at least two first registers, a second register, and a An output interface, an input interface, and a controller.

Each of the first registers of the at least two first registers includes N input pins, a clock pin, and N output pins, wherein N is a positive integer greater than or equal to 1, and N input pins The bit and the clock pin are respectively electrically connected to the first bus bar, and the N output pins are electrically connected to the second bus bar, respectively.

The second register includes M input pins, a clock pin, and M output pins, wherein M refers to a positive integer greater than N, and M input pins are electrically connected to the second bus, And correspondingly connected to one of the output pins of the at least two first data registers to be electrically connected, and the clock pin is also electrically connected to the second bus.

The output interface includes M data output pins, which respectively correspond to M output pins electrically connected to the second register.

The input interface is electrically connected to the first bus bar, and the input interface includes N input pins, at least two first clock pins, and a second clock pin, wherein at least two first clock positions The number is the same as the number of at least two first registers, and at least two first clock positions correspond to at least two first The clock pin of the register is electrically connected, and the second clock pin is electrically connected to the clock pin of the second register.

The controller is capable of separately controlling at least two first clock pin positions of the enable input interface, and then controlling the second clock pin position of the enable input interface at the next time.

In this way, the effect of expanding the input interface can be achieved, and the purpose of pre-burning the logic chip under the memory pre-burning machine architecture without modifying the existing hardware device is advantageous, which has the advantages of cost saving, fastness and convenience.

In addition, the controller may include an FPGA chip module, or an equivalent controller such as a PC computer. The controller may separately control at least two first clock pin positions of the enable input interface in sequence or not, and the data signals of the N input pins of the input interface are transmitted in batches through the first bus bar and temporarily stored to the sequence. The first clock pin of the enable corresponds to the N input pins of the first register, and is synchronously corresponding to the input pin temporarily stored in the second register.

The controller controls the second clock pin of the enable input interface at the next time so that the M output pins of the second register output the data signals to the M data output pins of the output interface.

Wherein, the positive integer M is an integer multiple of a positive integer N, but may also be a non-integer multiple, as long as M is a positive integer greater than N, and at least two first temporary registers may respectively refer to a latch (Latch) . The second register can refer to a latch.

Please refer to FIG. 2, which is a schematic view of a first preferred embodiment of the present invention. As shown in the figure, the embodiment is a wafer pre-burning machine station capable of expanding the number of control signals, comprising a first bus bar 10, a second bus bar 20, and four first registers 21, 22, 23, 24. A second register 31, an output interface 40, an input interface 1, and a controller 5.

In the figure, each of the first registers of the four first registers 21, 22, 23, 24 includes N input pins d1, d2, d3, ..., dn, a clock pin CLK, And N output pins q1, q2, q3, ..., qn. Also in this example, the first registers 21, 22, 23, 24 refer to a latch, respectively.

Where N is a positive integer greater than or equal to 1 (ie, N≧1), and N input pins d1, d2, d3, ..., dn, and clock pin CLK1 are electrically connected to the first busbar 10, respectively. The N output pins q1, q2, q3, ..., qn are electrically connected to the second bus bar 20, respectively.

In this embodiment, the first register 21 has 25 input pins d1, d2, d3, ..., d25, and the first register 21 has 25 output pins q1, q2, q3, ..., q25, And one clock pin CLK1. See Figure 2, and the rest of the first registers 22, 23, 24 and so on.

The second register 31 includes M input pins D1, D2, D3, ..., Dm, a clock pin CLK5, and M output pins Q1, Q2, Q3, ..., Qm, in this example, The second register 31 refers to a latch.

The above M refers to a positive integer greater than N (ie, M>N≧1), or the number M is an integer multiple of the number N, but may also be a non-integer multiple, as long as M is a positive integer greater than N.

As shown in FIG. 2, M input pins D1, D2, D3, ..., Dm are electrically connected to the second busbar 20, respectively, and correspond to four first data registers 21, 22, 23, 24, respectively. One of the output pins q1, q2, q3, ..., qn is electrically connected. In this embodiment, the second register 31 includes 100 input pins D1, D2, D3, ..., D100, and 100 output pins Q1, Q2, Q3, ..., Q100.

The output interface 40 is disposed on a pre-burning board 4 and includes M data output pins DR1, DR2, DR3, ..., DRm. In this embodiment, the output interface 40 has 100 data output pins. DR1, DR2, DR3, ..., DR100 respectively correspond to 100 output pins Q1, Q2, Q3, ..., Q100 electrically connected to the second register 31.

The input interface 1 is electrically connected to the first bus bar 10. The input interface 1 includes N input pins p1, p2, . . . , pn, four first clock pin positions CLK1, CLK2, CLK3, CLK4, and one. The second clock pin CLK5, in this embodiment, the input interface 1 includes 25 input pins p1, p2, ..., p25.

The number of the four first clock pins CLK1, CLK2, CLK3, and CLK4 is the same as the number of the four first registers 21, 22, 23, 24, and the four first clock pins CLK1, CLK2 , CLK3, CLK4 corresponding to the four first register 21, 22, 23, 24 clock pin CLK1, CLK2, CLK3, CLK4 are electrically connected, and the second clock pin CLK5 corresponds to the second The clock pin CLK5 of the register 31 is electrically connected.

The controller 5 includes an FPGA chip module or a PC computer. The controller 5 can selectively control the first four times of the enable input interface 1 before a first time T1. Pulse pin CLK1, CLK2, CLK3, CLK4.

The controller 5 controls the first clock pin positions CLK1, CLK2, CLK3, CLK4 of the enable input interface 1 and the 25 input pins p1, p2, ..., p25 of the input interface 1 in sequence or not. The data signal is transmitted in batches through the first bus 10 and temporarily stored to the 25 input pins of the first register 21, 22, 23, 24 corresponding to the sequentially enabled first clock pin CLK1~CLK4. D1, d2, d3, ..., d25, and the synchronous corresponding temporary storage in the input pin of the second register 31, the controller 5 is the second clock pin of the control enable input interface 1 at the next time T2 CLK5, so that the 100 output pins Q1, Q2, Q3, ..., Q100 of the second register 31 output the data signals to the 100 data output pins DR1, DR2, DR3, ... of the output interface 40, DR100.

In summary, in this example, the burn-in data I1, I2, I3, I4 (not shown) in the input interface 1 is output through the controller 5 through the input pins p1, p2, ..., p25 of the input interface 1 to The first bus bar 10.

When the first clock pin CLK1 is enabled, the input pins p1, p2, ..., p25 of the input interface 1 synchronously output the burn-in data I1 for temporary storage in the first register 21, when the first clock pin When CLK2 is enabled, the input pins p1, p2, ..., p25 of the input interface 1 synchronously output the burn-in data I2 for temporary storage in the first register 22, and when the first clock pin CLK3 is enabled, the input interface The input pin p1, p2, ..., p25 of the synchronous output pre-burning data I3 is temporarily stored in the first register 23, and when the first clock pin CLK4 is enabled, the input pin p1, p2 of the input interface 1 is input. , ..., p25 synchronously outputs the burn-in data I4 to be temporarily stored in the first register 24, and temporarily stores the burn-in data I1~I4 in the second register 31. The second clock pulse pin CLK5 is further enabled to provide the output interface 40 for pre-sintering the wafer by using the burn-in data I1~I4 in the second register 31.

Therefore, the input pins p1, p2, . . . , p25 of the input interface 1 can be expanded to the output of the second register 31 through the first registers 21, 22, 23, 24 and the second register 31. Pins Q1, Q2, Q3, ..., Q100, under the structure of the limited position of the memory pre-burning machine, can expand the foot without modifying any hardware equipment, and the memory pre-burning machine architecture The purpose of pre-burning a large number of logic chips is to save cost, speed and convenience.

Please refer to FIG. 3, which is a schematic view of a second preferred embodiment of the present invention. The architecture of the present embodiment is substantially the same as that of the previous embodiment, except that the input interface 51 in the controller 50 has only two first clock pins CLK1, CLK2, and two first data registers 21, twenty two. In this example, the first data registers 61, 62 respectively have 25 input pins d1, d2, d3, ..., d25, 25 output pins q1, q2, q3, ..., q25; The register 32 only needs 25 input pins D1, D2, D3, ..., D50, and 25 output pins Q1, Q2, Q3, ..., Q50, and the output interface 41 of the burn-in board 42 only needs 50 Data output pins DR1, DR2, DR3, ..., DR50. The number of the first data registers 61, 62 can be increased or decreased according to the number of bits of the output interface 41 required by the pre-burning plate 42, but not less than two, so that the input of the input interface 51 can be flexibly expanded. Pins p1, p2, ..., p25.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

Input interface ‧‧1,51

First bus ‧ ‧ ‧

Second bus ‧ ‧ ‧

First register ‧‧21,22,23,24

Second register ‧‧31,32

Burnt plate ‧‧‧4,42

Output interface ‧‧‧40,41

Controller ‧‧5,50

First register ‧‧6.11,62

Interface card ‧‧9

Burnt plate ‧‧90

Output pin ‧‧‧91

Memory chip ‧‧92

Input pin ‧‧‧p1,p2,...,pn

Input pin ‧‧‧d1,d2,d3,...,dn

Input pin ‧‧D1, D2, D3,..., Dm

Output pin ‧‧‧q1,q2,q3,...,qn

Output pin ‧‧‧Q1, Q2, Q3,...,Qm

First clock pin ‧‧‧CLK1~CLK4

Time ‧‧T1, T2

Output pin ‧‧‧DR1,DR2,DR3,...,DRm

Second clock pin ‧‧‧CLK5

Pre-burning information ‧‧‧I1, I2, I3, I4

FIG. 1 is a schematic diagram of a conventional interface card and a pre-burning plate.

Figure 2 is a schematic illustration of a first preferred embodiment of the present invention.

Figure 3 is a schematic illustration of a second preferred embodiment of the present invention.

Input interface ‧‧1

First bus ‧ ‧ ‧

Second bus ‧ ‧ ‧

First register ‧‧21,22,23,24

Second register ‧‧31

Burnt plate ‧‧4

Output interface ‧‧40

Controller ‧‧5

Input pin ‧‧‧p1,p2,...,pn

Input pin ‧‧‧d1,d2,d3,...,dn

Input pin ‧‧D1, D2, D3,..., Dm

Output pin ‧‧‧q1,q2,q3,...,qn

Output pin ‧‧‧Q1, Q2, Q3,...,Qm

Output pin ‧‧‧DR1,DR2,DR3,...,DRm

First clock pin ‧‧‧CLK1~CLK4

Second clock pin ‧‧‧CLK5

Claims (7)

A wafer pre-burning machine capable of expanding the number of control signals, comprising: a first bus bar; a second bus bar; at least two first registers, each of the first registers includes N input pins, a clock pin, and N output pins, wherein N is a positive integer greater than or equal to 1, the N input pins, and the clock pin are electrically connected to the first bus, respectively, the N The output pin is electrically connected to the second bus; the second register includes M input pins, a clock pin, and M output pins, wherein the M is greater than N. An integer, the M input pins are electrically connected to the second bus, and respectively connected to one of the output pins of the at least two first data registers to be electrically connected; an output interface includes M data output pin positions respectively corresponding to the M output pin positions electrically connected to the second register; an input interface electrically connected to the first bus bar, the input interface comprising N Input pin, at least two first clock pin, and a second clock pin, wherein the at least two The number of the clock pins is the same as the number of the at least two first registers, and the at least two first clock pins are respectively electrically connected to the clock pins of the at least two first registers. The second clock pin corresponds to the clock pin of the second register to be electrically connected; A controller is configured to first control the at least two first clock pin positions of the input interface, and then control the second clock pin position of the input interface at a next time. The wafer pre-burning machine capable of expanding the number of control signals as described in claim 1 of the patent application, wherein the controller comprises an FPGA chip module. The wafer pre-burning machine capable of expanding the number of control signals according to the first aspect of the patent application, wherein the controller sequentially controls the at least two first clock positions that enable the input interface, the input interface The data signals of the N input pins are transmitted in batches through the first bus and temporarily stored to the N input pins of the first register corresponding to the sequentially enabled first clock pin. And synchronously corresponding to the input pin temporarily stored in the second register. The wafer pre-burning machine capable of expanding the number of control signals as described in claim 1 , wherein the controller controls the second clock pin of the input interface at the next time to enable the The M output pins of the second register output the data signals to the M data output pins of the output interface. A wafer pre-burning machine capable of expanding the number of control signals as described in claim 1 wherein the positive integer M is an integer multiple of the positive integer N. The wafer pre-burning machine capable of expanding the number of control signals according to the first aspect of the patent application, wherein the at least two first registers respectively refer to a latch. A wafer pre-burning machine capable of expanding the number of control signals as described in claim 1 of the patent application, wherein the second register refers to a latch.