TWI392070B - Package substrate having semiconductor component embedded therein and fabrication method thereof - Google Patents

Description

Semiconductor component and package substrate embedded with semiconductor component and method of manufacturing same

The invention relates to a semiconductor structure and a manufacturing method, in particular to a semiconductor component and a package substrate embedded with a semiconductor component and a manufacturing method thereof.

With the evolution of semiconductor packaging technology, in addition to the conventional wire bonding semiconductor packaging technology, semiconductor devices have been developed in different package types, such as directly embedded in a package substrate. And electrically integrated with a semiconductor wafer having an integrated circuit, the semiconductor device can reduce the overall size and thickness, and enhance the electrical function, and the package structure gradually becomes a mainstream of the package.

Please refer to the method for manufacturing a semiconductor wafer-embedded package substrate disclosed in US Pat. No. 6,586,276, which is incorporated herein by reference. FIG. 1A shows a wafer 10 having a plurality of electrode pads 101; As shown in FIG. 1B, a passivation layer 11 is formed on the wafer 10; as shown in FIG. 1C, a first opening 110 is formed in the passivation layer 11 to expose the electrode pad 101; as shown in FIG. 1D The surface of the passivation layer 11 and the electrode pad 101 is covered with an adhesive layer 12; as shown in FIG. 1E, a protective layer 13 is formed on the surface of the adhesive layer 12; as shown in FIG. The wafer 10 is formed to form a plurality of semiconductor wafers 10a; as shown in FIG. 1G, a substrate body 14 having an opening 140 is provided, the semiconductor wafer 10a is placed in the opening 140 of the substrate body 14, and formed by the bonding material 15 a gap between the opening 140 of the substrate body 14 and the semiconductor wafer 10a The semiconductor wafer 10a is fixed in the opening 140; as shown in FIG. 1H, a conductive layer 16 is formed on the protective layer 13, the bonding material 15 and the substrate body 14 of the semiconductor wafer 10a; As shown in the figure, a resist layer 17 is formed on the conductive layer 16, and a resist opening 170 is formed at a position corresponding to the electrode pads 101; as shown in FIG. 1J, the conductive layer in the resist opening 170 16 is plated to form an Expanded Pad 18; as shown in FIG. 1K, the resist layer 17 and the conductive layer 16, the protective layer 13 and the adhesive layer 12 are removed to expose the expansion pad 18 and passivation. The layer 11, wherein the expansion pad 18 is larger than the electrode pad 101 to facilitate subsequent bonding of the dielectric layer and the alignment of the circuit layer; as shown in FIG. 1L, the expansion pad 18 and the passivation layer 11 are applied. And forming a build-up structure 19 on the substrate body 14. The build-up structure 19 includes at least one dielectric layer 191, a circuit layer 192 stacked on the dielectric layer, and formed in the dielectric layer and electrically Connecting the conductive blind holes 193 of the expansion pad 18, and having a plurality of electrical connections to the circuit layer 19 on the surface of the build-up structure 19 An electrical contact pad 194 is further formed on the build-up structure 19 to form an insulating protective layer 195. The insulating protective layer 195 is formed with a plurality of insulating protective layer openings 1950 to correspondingly expose the electrical contact pads 194.

As can be seen from the above, in the method of fabricating a package substrate in which a semiconductor wafer is embedded, it is necessary to form an adhesive layer 12 on the passivation layer 11 and the electrode pad 101, and then form a protective layer 13 on the adhesive layer 12. The wafer 10 is cut into a plurality of semiconductor wafers 10a; the semiconductor wafer 10a is then fixed in the opening 140 of the substrate body 14 with a bonding material 15, and then the expansion pad 18 is formed on the adhesive layer 12 and the protective layer 13. It The dielectric layer 191 of the build-up structure 19 is formed on the semiconductor wafer 10a, the bonding material 15 and the substrate body 14 on which the expansion pad 18 is formed; that is, the semiconductor wafer 10a must be first fixed to the substrate body 14 by the bonding material 15. In the opening 140, the process complexity is increased; then the expansion pad 18 is formed on the electrode pad 101 of the semiconductor wafer 10a, so that the subsequent build-up structure 19 can be performed to avoid the build-up structure by the expansion pad 18. When the dielectric layer 191 of 19 is formed into an opening, the electrode pad 101 of the semiconductor wafer 10a is damaged. Thus, the manufacturing process of manufacturing the expansion pad 18 will result in an increase in process steps, time and production cost, and the expansion pad 18 and the conductive layer are included. The electrical connection structure of the blind via 193 is also a complicated structure.

Therefore, in view of the above problems, how to avoid the problems of high processing cost and wasted time and complicated structure in the prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide a semiconductor device and a package substrate embedded with the semiconductor device and a method of fabricating the same, which can simplify the structure of the semiconductor device and save the process steps.

Another object of the present invention is to provide a semiconductor device and a package substrate embedded with a semiconductor device and a method for fabricating the same, which can electrically connect the conductive blind vias directly to the electrode pads of the semiconductor wafer.

To achieve the above and other objects, the present invention discloses a semiconductor device comprising: a semiconductor wafer having a corresponding active surface and a non-active surface, the active surface having a plurality of electrode pads; and a passivation layer disposed thereon a working surface and an electrode pad; and a metal pad is disposed on the passivation layer, and Corresponding to the electrode pads.

According to the above structure, the passivation layer is composed of a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad, wherein the first passivation layer It is made of tantalum nitride (Si ₃ N ₄ ) or cerium oxide (SiO ₂ ), and the second passivation layer is polyimide or benzocyclobutene (BCB). The metal pad is copper.

The present invention further provides a package substrate embedded with a semiconductor component, comprising: a substrate body having at least one opening; and a semiconductor wafer fixed in an opening of the substrate body, the semiconductor wafer having a corresponding active surface and a non- The active surface has a plurality of electrode pads and a passivation layer disposed on the active surface, the passivation layer has a passivation layer opening corresponding to the electrode pad; and a metal ring is disposed on the opening of the passivation layer; The first dielectric layer is disposed on the substrate body, the passivation layer and the metal ring, and the dielectric pad is formed with an opening through the dielectric layer to expose the electrode pad; and the first circuit layer is disposed on the substrate layer A first conductive via hole is disposed in the dielectric layer opening and the opening of the passivation layer to electrically connect the electrode pad, and the first conductive blind hole contacts the metal ring.

According to the above structure, the passivation layer is composed of a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad, wherein the first passivation The layer is tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ), and the second passivation layer is polyimide or benzocyclobutene (BCB).

The first dielectric layer and the first circuit layer are provided with a build-up structure, and the build-up structure includes at least one second dielectric layer stacked on the second dielectric layer. a second circuit layer, and a plurality of second conductive blind holes disposed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and electrically connected to the build-up structure The electrical contact pad of the second circuit layer is further provided with an insulating protective layer on the layered structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electrical contact pads.

The invention further provides a method for manufacturing a package substrate embedded with a semiconductor component, comprising: providing a wafer having a corresponding active surface and a non-active surface, wherein the active surface has a plurality of electrode pads formed on the active surface a passivation layer, and a metal pad corresponding to the electrode pad is disposed on the passivation layer; the wafer is cut to form a plurality of semiconductor wafers; a substrate body having an opening is provided, and the semiconductor wafer is received in the opening Forming a first dielectric layer on the substrate body and the semiconductor wafer, and filling the first dielectric layer into a gap between the opening of the substrate body and the semiconductor wafer to fix the semiconductor wafer in the opening Forming a dielectric layer opening corresponding to the metal pad in the first dielectric layer, and exposing a portion of the surface of the metal pad; removing the metal pad and the passivation layer in the opening of the dielectric layer, Forming a passivation layer opening and exposing the electrode pad, and forming the metal pad to form a metal ring; forming a first circuit layer on the first dielectric layer, the first circuit layer having a plurality of layers formed on the dielectric layer open Openings of the passivation layer and first conductive vias to electrically connected to the electrode pad, and the first conductive vias contacting the metal ring; and removing the resist layer and the conductive layer is covered.

According to the above method, the metal pad is formed by metal layer etching or physical sputtering; the passivation layer is formed by a first passivation layer having an opening to expose the electrode pad and formed on the first passivation layer and covering the electrode pad a second passivation layer, wherein the first passivation layer is tantalum nitride (Si ₃ N ₄ ) or cerium oxide (SiO ₂ ), and the second passivation layer is polyimide (Polyimide) or Benzocyclobutene (BCB); the laser system is a carbon dioxide laser.

Forming a passivation layer on the active surface of the wafer, comprising: forming a first passivation layer on the wafer, and forming an opening in the first passivation layer to expose the electrode pad; and the electrode pad, Forming a second passivation layer on a passivation layer and an opening thereof; and forming the metal pad on a position corresponding to the electrode pad on the second passivation layer.

The metal pad and the passivation layer in the opening of the dielectric layer are removed synchronously, or the metal pad is removed first, and then the passivation layer is removed.

The first circuit layer and the first conductive via hole are formed on the electrode pad, the passivation layer opening, the first dielectric layer and the opening surface of the dielectric layer are formed with a conductive layer; on the conductive layer Forming a resist layer, wherein the resist layer is formed with a plurality of resist layer openings to expose a surface of the conductive layer portion on the first dielectric layer, a dielectric layer opening and a conductive layer in the opening of the passivation layer; and The first circuit layer is formed by electroplating on the conductive layer in the layer opening, and the first conductive blind hole is formed in the opening of the resist layer, the opening of the dielectric layer and the opening of the passivation layer to electrically connect the electrode pad.

Forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure comprising at least one second dielectric layer, a second circuit layer stacked on the second dielectric layer, and a plurality a second conductive via hole formed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and electrically connected to the second circuit layer on the build-up structure Pad, again An insulating protective layer is formed on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electrical contact pads.

Therefore, the semiconductor device of the present invention and the package substrate embedded with the semiconductor device and the method for manufacturing the same are to cut a wafer having a metal pad provided on the passivation layer and opposed to the electrode pad into a plurality of semiconductor wafers, and the semiconductor wafer is disposed Forming a first dielectric layer on the semiconductor wafer and the substrate body in the opening of the substrate body to fix the semiconductor wafer in the opening of the substrate body, so as to prevent the conventional material from being fixed by the bonding material. Dielectric layer, and adding a process defect; then, forming a dielectric layer opening in the first dielectric layer by laser, and blocking by the metal pad to avoid penetrating the electrode pad, and then removing the dielectric layer a metal pad and a passivation layer in the opening of the electric layer to expose the electrode pad of the semiconductor wafer, and then forming a first circuit layer on the first dielectric layer and electrically connecting the electrode pad, thereby eliminating the need for conventional The expansion pad is first formed, and then the missing structure is formed to reduce the cost of the wafer process and the time course of product fabrication; therefore, the invention has the electrode pad for protecting the semiconductor wafer and can be directly charged. And conductively connected to the process step of saving effect.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

[First Embodiment]

Please refer to FIGS. 2A to 2D and FIGS. 3A to 3H , which illustrate a semiconductor device of the present invention and a package substrate in which a semiconductor element is embedded and a method of fabricating the same.

Please refer to Figures 2A to 2D for forming a passivation layer and metal on the wafer. The method of making the pad.

As shown in FIG. 2A, a wafer 20 having a corresponding active surface 20a and a non-active surface 20b is provided, and a plurality of electrode pads 201 are provided on the active surface 20a.

As shown in FIG. 2B, a first passivation layer 22a such as tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ) is formed on the active surface 20a of the wafer 20, and the first passivation layer is formed. 22a is formed with an opening 220a to expose a part of the surface of the electrode pad 201.

As shown in FIG. 2C, a second passivation layer 22b such as polyimide or benzocyclobutene (BCB) is formed on the electrode pad 201 and the first passivation layer 22a to make the first passivation. The layer 22a and the second passivation layer 22b constitute a passivation layer 22.

As shown in FIG. 2D, a metal pad 23 is formed on the passivation layer 22 by metal layer etching or physical sputtering; wherein the metal layer is formed by first forming a metal layer, and then forming a resist layer on the metal layer. Forming a resist layer opening corresponding to the electrode pad in the resist layer to expose a portion of the metal layer, removing the metal layer not covered by the resist layer, and finally removing the resist layer to expose the metal pad; The physical sputtering is placed on the passivation layer by a photomask, and the photomask has a perforation corresponding to the electrode pad, the metal pad is formed by physical sputtering in the perforation, and the photomask is finally removed to expose the photomask. Metal pad.

Referring to FIG. 3A, the wafer 20 is then diced to form a plurality of semiconductor wafers 20'. Accordingly, the present invention provides a semiconductor device comprising: a semiconductor wafer 20' having a corresponding active surface 20a and a non-active surface 20b, having a plurality of electrode pads 201 on the active surface 20a; blunt The layer 22 is disposed on the active surface 20a and the electrode pad 201; and the metal pad 23 is disposed on the passivation layer 22 and is disposed on the electrode pad 201.

The passivation layer 22 is composed of a first passivation layer 22a having an opening 220a to expose the electrode pad 201 and a second passivation layer 22b formed on the first passivation layer 22a and covering the electrode pad 201. A passivation layer 22a is tantalum nitride (Si ₃ N ₄ ), and the second passivation layer 22b is polyimide. The metal pad 23 is made of copper.

Please refer to FIGS. 3A to 3H , which are cross-sectional views showing a process flow for embedding a semiconductor wafer in a package substrate.

As shown in FIG. 3A, a wafer 20 such as FIG. 2D is provided, and the wafer 20 is diced to form a plurality of semiconductor wafers 20' having corresponding active faces 20a and non-active surfaces. 20b, the active surface 20a has a plurality of electrode pads 201 and a passivation layer 22 formed on the active surface 20a, and a metal pad 23 is disposed on the passivation layer 22 corresponding to the electrode pads 201.

As shown in FIG. 3B, a substrate body 30 having an opening 300 is provided, the semiconductor wafer 20' is received in the opening 300, and a first dielectric layer 31 is formed on the semiconductor wafer 20' and the substrate body 30, The first dielectric layer 31 is filled in the gap between the opening 300 and the semiconductor wafer 20' to fix the semiconductor wafer 20' in the opening 300.

As shown in FIG. 3C, a dielectric layer opening 310 is formed in the first dielectric layer 31 by, for example, a carbon dioxide laser, and a portion of the surface of the metal pad 23 is exposed, and the metal pad 23 is blocked to avoid lightning. The light penetrates through the electrode pad 201.

As shown in FIG. 3D, the metal pad 23 is sequentially removed (removed by micro-etching) and the passivation layer 22 is removed to form a passivation layer opening 220 and expose the electrode pad 201, and the The metal pad forms a metal ring 23'.

As shown in FIG. 3E, a conductive layer 32 is formed on the surface of the electrode pad 201, the passivation layer opening 220, the first dielectric layer 31, and the dielectric layer opening 310. The conductive layer 32 is mainly used as a plating metal material to be described later. a desired current conduction path, which may be composed of a metal, an alloy or a plurality of deposited metal layers, or a conductive polymer material may be used as the conductive layer 32; then, a resist layer 33 is formed on the conductive layer 32, the resistance The layer 33 is a photoresist layer such as a dry film or a liquid photoresist, which is formed on the surface of the conductive layer 32 by printing, spin coating or lamination, and then patterned by exposure, development, or the like. A plurality of resist opening openings 330 are formed in the resist layer 33 to expose a portion of the surface of the conductive layer 32 on the first dielectric layer 31, and the conductive layer 32 in the dielectric layer opening 310 and the passivation layer opening 220. .

As shown in FIG. 3F, the conductive layer 32 is used as a current conduction path to form a first wiring layer 34 on the conductive layer 32 in the barrier layer opening 330, and the barrier layer opening 330 and the dielectric layer are formed. A first conductive via hole 341 is formed in the opening 310 and the passivation layer opening 220 to electrically connect the electrode pad 201, and the first conductive blind hole 341 contacts the metal ring 23'.

As shown in FIG. 3G, the resist layer 33 and the conductive layer 32 covered thereon are removed to expose the first dielectric layer 31 and the first wiring layer 34.

Finally, as shown in FIG. 3H, finally, a build-up structure 35 is formed on the first dielectric layer 31 and the first circuit layer 34, and the build-up structure 35 includes a second dielectric layer 351, a second circuit layer 352 stacked on the second dielectric layer, and a plurality of dielectric layers 252 are electrically formed in the second dielectric layer and electrically connected to the first circuit layer 34 and the second a second conductive via 353 of the circuit layer 352, and an electrical contact pad 354 electrically connected to the second circuit layer 352, and then an insulating protective layer 36 is formed on the build-up structure 35, and The insulating protective layer 36 has a plurality of insulating protective layer openings 360 to correspondingly expose the electrical contact pads 354.

The present invention provides a package substrate in which a semiconductor device is embedded, comprising: a substrate body 30 having at least one opening 300; a semiconductor wafer 20' fixed in an opening 300 of the substrate body 30, the semiconductor wafer 20' There is a corresponding active surface 20a and a non-active surface 20b. The active surface 20a has a plurality of electrode pads 201 and a passivation layer 22 disposed on the active surface 20a. The passivation layer 22 has a passivation layer corresponding to the electrode pads 201. The opening 220; the metal ring 23' is disposed on the passivation layer opening 220; the first dielectric layer 31 is disposed on the substrate body 30, the passivation layer 22 and the metal ring 23', and the electrode pad is 201 is formed through the dielectric layer opening 310 to expose the electrode pad 201; and the first circuit layer 34 is disposed on the first dielectric layer 31, and is opened in the dielectric layer opening 310 and the passivation layer A first conductive blind via 341 is disposed in the hole 220 to electrically connect the electrode pad 201, and the first conductive blind via 341 contacts the metal ring 23'.

According to the above structure, the passivation layer 22 is composed of a first passivation layer 22a having an opening 220a to expose the electrode pad 201 and a second passivation layer 22b formed on the first passivation layer 22a and covering the electrode pad 201. Wherein the first passivation layer 22a is tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ), and the second passivation layer 22b is polyimide or benzocyclobutene (BCB).

The first dielectric layer 31 and the first circuit layer 34 are provided with a build-up structure 35. The build-up structure 35 includes at least one second dielectric layer 351 and a plurality of stacked on the second dielectric layer. a second circuit layer 352, and a plurality of second conductive vias 353 disposed in the second dielectric layer and electrically connected to the second circuit layer 352. The second conductive via 353 is electrically connected to the first circuit layer. 34, and the electrical layer 354 is electrically connected to the second circuit layer 352, and the insulating layer 36 is provided on the layering structure 35, and the insulating layer 36 has a plurality of insulating layers 36. The insulating layer is opened 360 to correspondingly expose the electrical contact pad 354.

Therefore, the semiconductor device of the present invention and the package substrate embedded with the semiconductor device and the method for manufacturing the same are to cut a wafer having a metal pad provided on the passivation layer and opposed to the electrode pad into a plurality of semiconductor wafers, and the semiconductor wafer is disposed Forming a first dielectric layer on the semiconductor wafer and the substrate body in the opening of the substrate body to fix the semiconductor wafer in the opening of the substrate body, so as to prevent the conventional material from being fixed by the bonding material. Dielectric layer, and adding a process defect; then, forming a dielectric layer opening in the first dielectric layer by laser, and blocking by the metal pad to avoid penetrating the electrode pad, and then removing the dielectric layer a metal pad and a passivation layer in the opening of the electrical layer to expose the electrode pad of the semiconductor wafer, and then forming a first circuit layer on the first dielectric layer, and in the opening of the dielectric layer and the opening of the passivation layer Forming a first conductive blind via to electrically connect the electrode pad, the germanium may be omitted to make an expansion pad to protect the electrode pad, and then forming a missing layer structure to reduce the crystal The cost of the round process and the time course of product manufacturing; therefore, the present invention has the effect of protecting the electrode pads of the semiconductor wafer, and being capable of direct electrical conduction and saving process steps.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 20‧‧‧ wafer

101, 201‧‧‧electrode pads

10a, 20’‧‧‧ semiconductor wafer

11, 22‧‧‧ Passivation layer

110‧‧‧First opening

12‧‧‧Adhesive layer

13‧‧‧Protective layer

14, 30‧‧‧ substrate body

140, 300‧‧‧ openings

15‧‧‧Combined materials

16, 32‧‧‧ conductive layer

17, 33‧‧‧ resistance layer

170, 330‧‧‧ barrier opening

18‧‧‧Expansion pad

19, 35‧‧ ‧ layered structure

191‧‧‧ dielectric layer

192‧‧‧circuit layer

193‧‧‧ Conductive blind holes

194, 354‧‧‧Electrical contact pads

195, 36‧‧‧Insulating protective layer

1950, 360‧‧‧Insulation protective layer opening

20a‧‧‧Action surface

20b‧‧‧Non-active surface

220‧‧‧ Passivation layer opening

220a‧‧‧ opening

22a‧‧‧First passivation layer

22b‧‧‧second passivation layer

23‧‧‧Metal pad

23’‧‧‧Metal ring

31‧‧‧First dielectric layer

310‧‧‧Dielectric layer opening

34‧‧‧First line layer

341‧‧‧First conductive blind hole

351‧‧‧Second dielectric layer

352‧‧‧second circuit layer

353‧‧‧Second conductive blind hole

1A to 1L are schematic cross-sectional views showing a conventional method of manufacturing a package substrate in which a semiconductor element is embedded; and FIGS. 2A to 2D are cross-sectional views showing a method of forming a passivation layer on a wafer active surface in the present invention; 3A to 3H are schematic cross-sectional views showing a method of manufacturing a package substrate in which a semiconductor element is embedded in the present invention.

20’‧‧‧Semiconductor wafer

201‧‧‧electrode pads

30‧‧‧Substrate body

31‧‧‧First dielectric layer

34‧‧‧First line layer

341‧‧‧First conductive blind hole

Claims (21)

A semiconductor device comprising: a semiconductor wafer having a corresponding active surface and a non-active surface; the active surface having a plurality of electrode pads; a passivation layer disposed on the active surface and the electrode pad, the passivation layer being a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad; and a metal pad disposed on the second passivation layer, and Corresponding to the electrode pad position. The semiconductor device of claim 1, wherein the first passivation layer is tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ). The semiconductor device of claim 1, wherein the second passivation layer is polyimide or benzocyclobutene (BCB). The semiconductor component of claim 1, wherein the metal pad is copper. A package substrate embedded with a semiconductor component, comprising: a substrate body having at least one opening; and a semiconductor wafer fixed in an opening of the substrate body, the semiconductor wafer having a corresponding active surface and a non-active surface The active surface has a plurality of electrode pads and a passivation layer disposed on the active surface, the passivation layer having a passivation layer opening corresponding to the electrode pad, the passivation layer being first passivated by having an opening to expose the electrode pad Layer and Forming on the first passivation layer and covering the second passivation layer of the electrode pad; the metal ring is disposed on the opening of the passivation layer; the first dielectric layer is disposed on the substrate body, the passivation layer, and a metal ring is formed on the electrode pad to form a through hole through the dielectric layer to expose the electrode pad; and the first circuit layer is disposed on the first dielectric layer and is opened in the dielectric layer A first conductive blind via is disposed in the opening of the passivation layer to electrically connect the electrode pad, and the first conductive blind via contacts the metal ring. A package substrate embedded with a semiconductor element according to claim 5, wherein the first passivation layer is tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ). A package substrate embedded with a semiconductor element according to claim 5, wherein the second passivation layer is polyimide or benzocyclobutene (BCB). The package substrate embedded with the semiconductor component of claim 5 is further provided with a build-up structure, and is disposed on the first dielectric layer and the first circuit layer. The package substrate embedding a semiconductor device according to claim 7 , wherein the build-up structure comprises at least one second dielectric layer, a second circuit layer stacked on the second dielectric layer, And a plurality of second conductive blind vias disposed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and the build-up structure has electrical contact electrically connected to the second circuit layer pad. The package substrate embedded with the semiconductor component of claim 9 is further provided with an insulating protective layer on the layered structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electricity. Sexual contact pads. A method for manufacturing a package substrate with embedded semiconductor components, comprising: providing a wafer having a corresponding active surface and a non-active surface, wherein the active surface has a plurality of electrode pads and a passivation layer formed on the active surface, The passivation layer is composed of a first passivation layer having an opening to expose the electrode pad and a second passivation layer formed on the first passivation layer and covering the electrode pad, and is provided on the second passivation layer a metal pad of the electrode pad; cutting the wafer to form a plurality of semiconductor wafers; providing a substrate body having an opening, and housing the semiconductor wafer in the opening; forming a first dielectric on the substrate body and the semiconductor wafer a layer, and filling the first dielectric layer into a gap between the opening of the substrate body and the semiconductor wafer to fix the semiconductor wafer in the opening; and forming a relative laser in the first dielectric layer The dielectric layer of the metal pad is opened and a portion of the surface of the metal pad is exposed; the metal pad and the passivation layer in the opening of the dielectric layer are removed to form a passivation layer opening and expose the electrode pad, and The Metal pad is formed of a metal ring; a first wiring layer formed on the first dielectric layer, the first circuit The layer has a plurality of first conductive blind vias formed in the opening of the dielectric layer and the opening of the passivation layer to electrically connect the electrode pad, and the first conductive blind via contacts the metal ring; and removing the resist layer And the conductive layer covered by it. The method of claim 11, wherein the metal pad is formed by metal layer etching or physical sputtering. The method of claim 11, wherein the first passivation layer is tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO ₂ ). The method of claim 11, wherein the second passivation layer is polyimide or benzocyclobutene (BCB). The method for manufacturing a package substrate with embedded semiconductor components according to claim 11 , wherein the method for forming a passivation layer and a metal pad on the active surface of the wafer comprises: forming a first passivation layer on the wafer And forming an opening in the first passivation layer to expose the electrode pad; forming a second passivation layer on the electrode pad, the first passivation layer and the opening thereof; and corresponding to the electrode pad on the second passivation layer The location of the metal pad is formed. A method of manufacturing a package substrate in which a semiconductor element is embedded in claim 11, wherein the laser system is a carbon dioxide laser. The method of claim 11, wherein the metal pad and the passivation layer in the opening of the dielectric layer first remove the metal pad and then remove the passivation layer. The method for manufacturing a package substrate with a semiconductor device embedded in claim 11, wherein the first circuit layer and the first conductive via hole are formed on the electrode pad, the passivation layer opening, and the first interface a conductive layer is formed on the surface of the opening of the electrical layer and the dielectric layer; a resist layer is formed on the conductive layer, and a plurality of resist openings are formed in the resist layer to expose a portion of the conductive layer on the first dielectric layer a surface, a dielectric layer opening and a conductive layer in the opening of the passivation layer; and plating the first wiring layer on the conductive layer in the opening of the resist layer, and opening the opening, dielectric opening and passivation layer The first conductive blind via is formed in the opening to electrically connect the electrode pad. The method for manufacturing a package substrate embedded with a semiconductor device according to claim 11 is characterized in that the first dielectric layer and the first circuit layer are formed to form a build-up structure. The method of claim 19, wherein the build-up structure comprises at least one second dielectric layer and a second circuit layer stacked on the second dielectric layer. And a plurality of second conductive blind holes formed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, and the build-up structure has electrical connection electrically connected to the second circuit layer Sexual contact pads. A package embedded with a semiconductor component as claimed in claim 20 The substrate manufacturing method further comprises forming an insulating protective layer on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings to correspondingly expose the electrical contact pads.