1288845 等雜質，製成n型或p型之方法。 具體之液晶顯示裝置用之陣列基板之製造方法係於玻璃 基板上形麵晶半導體層之後，將此非晶半導體層進行雷 射光束退火’製成多晶半導體層之後進行圖案化。此後， 於包含此多晶半導體層之玻璃基板上，將閘極絕緣膜成膜。 此時’料素辅助電容未大於某程度，將無法保持此像 素輔助電容，因此閘極絕緣膜之膜厚宜儘量薄。因此，製 成在夕曰曰半導體層上形成閘極絕緣膜，&此問才虽絕緣膜形 成閘極電極之層之構造。因此，形成此閘極電極之前，將 光阻圖案化，藉由摻雜注入n型摻雜物（PH3)，分別形成卜仏 薄膜電晶體（TFT)之n+區域、像素電容及作為電路部之電容 區域之電容部。 並且，於含有此等n+區域、像素電容及電路部之電容部 之各別之閘極絕緣膜上將閘極電極成膜後，將成為^仆薄 膜電晶體（TFT)用之閘極電極圖案化之後，將p型摻雜物 (Β#5)作為雜質注入，形成p_ch薄膜電晶體之p+區域。 接著，將n-ch薄膜電晶體側之閘極電極圖案化之後，將 此等n-ch薄膜電晶體及p-ch薄膜電晶體分別退火之後，使此 等n-ch薄膜電晶體之n+區域及p-ch薄膜電晶體之p+區域分 別活化，其次於包含此等n_ch及p-ch薄膜電晶體之閘極電極 之閘極絕緣膜上，將層間絕緣膜成膜。 並且，於此層間絕緣膜形成接觸孔洞，連通n-ch薄膜電 晶體之n+區域及p-ch薄膜電晶體之P+區域之後，於包含此等 接觸孔洞之層間絕緣膜上形成導電層。此後，將此導電層 95517.doc 1288845 圖案化，形成電性地連接於n-ch薄膜電晶體之n+區域及p-ch 薄膜電晶體之P+區域之源極電極及汲極電極之構成係為人 所知。此構成揭示於例如：特開2002-/359252號公報（第7-10 頁、圖8-圖9)。 ’ 於此液晶顯示裝置，作為閘極配線係採用鉬-鎢（M〇W)或 鉬-鈕（MoTa)等含鉬合金。而且，此液晶顯示裝置之閘極電 極亦閘極配線之抽取線、像素電容配線及電路電容配線分 別於一層一體地形成。 銷合金具有耐熱性，作為可耐於5〇〇°C以上、6〇〇。(3以下 程度之熱活化之熱退火之材料而用於閘極電極。然而，由 於膜厚300 nm之鉬合金之片電阻（sheet Resistance)高達 〇_5 Ω /cm2，因此若細線化，電阻將變高，故無法將閘極 電極微細化。 為了使此閘極電極低電阻，使用比鉬合金低電阻之材 料例如·具有泛用性之鋁（A1)或鋁-銅（AlCu)等鋁合金亦 可:然而一，關於此紹合金，由於在後續工序之熱活化之際 之μ度冋，因此配線容易短路，唯恐產生電致遷移 =eCtr〇migration)所造成之電阻劣化或斷線等所引起之可 靠度劣化的問題。亦即’於熱活化之際，#以高溫將銘或 銘合金退火，將產生突起物，配線間容易短路。因此，由 製程的觀點考量，難以將閘極電極低電阻化。 田並且’於採用銘-钕（侧)之情況，即使以聲c以下的 /皿度退火，雖不發生可靠庚 4問，但在加工精度及生產 性仍有問題。亦即，若 、知用此鋁-歛之情況細線化至2 μηι 955l7.doc 1288845 ’ 於在濕式蝕刻難以控制線寬之變動，因此薄膜電 曰曰體之閑極電極長度之變動變大。因此，成為此薄膜電晶 體之電晶體特性變動的原因，故採用可控制此變動之乾式 名虫刻進行加工。 【發明内容】 y而’以上述液晶顯示裝置之閘極電極為鋁-鈦，將此閘 極電極進行乾式姓刻時，氯化鋁（A1C12)等蝕刻產生物大量 附著於乾式蝕刻裝置之處理室内壁面，故不易提升生產 ^ 口此’在需要閘極電極細線化之製品，由加工的觀點 考ΐ，難以將鋁-鈥作為閘極電極使用。故，具有難以將閘 極電極細線化及低電阻化的問題。 本發明係有鑑於此點所實現者，其目的在於提供一種可 將第一導電層細線化及低電阻化之陣列基板、液晶顯示裝 置及陣列基板之製造方法。 有關本發明之態樣之陣列基板具備： 透光性基板； 複數多晶半導體層，其係設於此透光性基板之一主面者； 閘極絕緣膜，其係設於包含此等複數多晶半導體層之前 述透光性基板之一主面者； 第一導電層，其係與前述複數多晶半導體層之任何之一 對向而經由前述閘極絕緣膜設置者；及 弟一導電層’其具備：配線部，其係設於此第一導電層 之一主面，電性連接於此第一導電層者；及電容配線部， 其係與前述複數多晶半導體層之任何其他對向而經由前述 95517.doc -10- 1288845 閘極絕緣膜設置，在與此多晶半導體層之間形成電容者。 又，關於本發明之其他態樣之液晶顯糸裝置具備： 陣列、基板，其具有··透光性基板；複數多晶半導體層， 其係没於此透光性基板之一主面者；閘極絕緣膜，其係設 於包含此等複數多晶半導體層之前述透光性基板之一主面 者，第一導電層，其係與前述複數多晶半導體層之任一對 向而經由前述閘極絕緣膜設' 置者；及第二導電層，其具備·· 配線部，其係設於此第一導電層之一主面，電性連接於此 第一導電層者；及電容配線部，其係與前述複數多晶半導 體層之任何其他對向而經由前述閘極絕緣膜設置，在與此 夕晶半導體層之間形成電容者，· 對向基板，其係與此陣列基板對向設置者；及 液晶，其係介插於此對向基板及前述陣列基板之間者。 又，有關本發明之其他態樣之陣列基板之製造方法，其 係： 於透光性基板之一主面設置複數多晶半導體層； 於包含此等複數多晶半導體層之前述透光性基板之一主 面設置閘極絕緣膜； 於此閘極絕緣膜之一主面設置第一導電層； 將此第一導電層圖案化，形成與前述複數多晶半導體層 之任一對向之1對閘極電極； 將此等1對閘極電極之任何之一作為掩模，在與此閘極電 極對向之前述多晶半導體層進行摻雜，作為P型開關元件之 源極區域及汲極區域； 95517.doc 11 1288845 將此等1對閘極 極對向之前述多晶半導::其他:為掩模，在與此㈣^ 义 導體層，及刖述閘極電極未對向設置 诉朽=M半導體層之各個進行摻雜，形成n型開關元件之 源極區域與料區域及辅助電容之電容部； :包含前述1對閘極電極之前述閘極絕緣膜之—主面形 成弟—導電層； 將此第二導電層圖案化，形成前述1對閘極電極對向之-對配線部及與此等1對閘極電極未對㈣置之前述多晶半 導體層對向之前述辅助電容之輔助電容部。 【實施方式】 、 >考固1至圖10，說明有關本發明之第一實施型態 之液晶顯示裝置之構成。 於圖1至圖10,作為平面顯示裝置之液晶顯示裝置】為薄 膜電晶體方式液晶顯示裝置’具備大致矩形平板狀之陣列 土板2 itb陣列基板2具有玻璃基板3，其係作為大致透明矩 形平板狀之絕緣基板之透光性基板。於此玻璃基板3之一主 面之表面上，層疊以氮化石夕膜或氧切膜等構成之未圖示 之底塗層而成膜。 於此底塗層上，作為液晶顯示用之n型開關元件之複數口 通道（n-ch)型薄膜電晶體（TFT)4係形成矩陣狀。並且，於此 底塗層上’作為液晶顯示用之P型開關元件之複數p通道 (p-ch)型薄膜電晶體（TFT)5及作為辅助電容之複數像素輔 助電容6之各個係複數形成矩陣狀。 在此，此等薄膜電晶體4、5各個作為！像素構成要素而配 95517.doc -12- 1288845 设。並且，此等薄膜電晶體4、5各個具傷形成於底塗層上 之作為多晶半導體層之多晶矽層11。此多晶矽層η係藉由 利用作為非曰曰半導體之非晶石夕之雷射退火所形成之多晶石夕 所構成。而且’此多日日日♦層u具有通道區域12，其係設於 此多晶梦層u之中央部之作為活性層者。於此通道區扣 之兩側η區域或p區域之源極區域13及沒極區域之各 個係對向設置。 於分別包含此等通道區域12、源極區域13及沒極區域Μ 之底塗層上，層疊具有絕緣性之氧化矽膜之閘極絕緣膜^ 而成膜。並且，在與通道區域12對向之閘極絕緣膜15上， 層璺以作為第一導電層之第一金屬層72所構成之閘極電極 16而成膜。第一金屬層72係藉由含有鉬（Μ〇)之合金，亦即 鉬-鎢（MoW)所構成。在此，此等閘極電極丨6係經由閘極絕 緣膜15而與各薄膜電晶體4、5之通道區域12對向，具有大 致與此通道區域12之寬度尺寸相等之寬度尺寸。 於此等閘極電極16上，層疊並形成作為第二導電層之第 二金屬層73所構成之作為閘極配線之配線部丨7。此等配線 部17係分別對於各閘極電極16而電性連接，具有與各閘極 電極16之寬度尺寸相等之寬度尺寸之閘極電極間配線。在 此，此等配線部17係藉由電阻值比閘極電極1 6小之材質所 構成。 另一方面，於連續於薄膜電晶體4、5之底塗層上，層疊 並形成以多晶矽構成之像素輔助電容6。此像素輔助電容6 係鄰接於p通道型薄膜電晶體5而設置，設置於經由此薄膜 95517.doc -13- 1288845 電晶體5之η通道型薄膜電晶體4之相反侧。 此像素輔助電容6配置在玻璃基板3上之與薄膜電晶體 4、5相同之平面上。又，此像素輔助電容6具備以多晶石夕構 成之電容部22。此電容部22係藉由利用作為非晶半導體之 非晶矽之雷射退火所形成之多晶矽而構成。又，此電容部 2 2係採用與各薄膜電晶體4、5之多晶碎層11相同之工序所 形成，並層疊於底塗層上。 於包含之電容部22之底塗層上，層疊閘極絕緣膜15而成 膜。而且，在與電容部22對向之閘極絕緣膜15上，層疊並 形成採用與各薄膜電晶體4、5之配線部17同一層之第二金 屬層73所構成之電容配線部23。此電容配線部23係偏向ρ 通道型薄膜電晶體5側之電容部22之寬度方向之一側而設 置。換言之，此電容配線部23設置在比電容部22之寬度方 向之中央部靠近ρ通道型薄膜電晶體5側之位置。 此等電容配線部23分別經由此等電容配線部23與電容部 22之間之閘極絕緣膜15，於此等電容部22之間形成電容。 在此’此等電容配線部23係採用與各薄膜電晶體4、5之配 線部17同一工序及同一材質所形成。因此，此等電容配線 部23具有比各薄膜電晶體4、5之配線部17之電阻值小的電 阻值。 在分別包含此電容配線部23及各薄膜電晶體4、5之配線 部17之閘極絕緣膜15上，層疊具有絕緣性之氧化石夕膜之層 間絕緣膜3 1而成膜。而且，於此等層間絕緣膜3 1及閘極絕 緣膜15，複數接觸孔洞32、33、34、35、36係開口而設置， 95517.doc -14- 1288845 其係作為分別貫通此等層間絕緣膜31及閘極絕緣膜15之導 通部。 在此，接觸孔洞32、33分別設於η通道型薄臈電晶體4之 閘極電極16兩側、此薄膜電晶體4之源極區域13及汲極區域 14上。而且，接觸孔洞32係連通於η通道型薄膜電晶體4之 源極區域13而開口，接觸孔洞3 3係連通於η通道型薄膜電晶 體4之汲極區域14而開口。 接觸孔洞34、35分別設於ρ通道型薄膜電晶體5之閘極電 極16兩側、此薄膜電晶體5之源極區域13及汲極區域14上。 而且，接觸孔洞34係連通於ρ通道型薄膜電晶體5之源極區 域13而開口，接觸孔洞35係連通於ρ通道型薄膜電晶體5之 汲極區域14而開口。又，接觸孔洞36係連通於像素輔助電 容6之電容部22而開口。 在連通於η通道型薄膜電晶體4之源極區域13之接觸孔洞 32 ’層豐設置作為導電層之信號線之源極電極4丨。此源極 電極41係經由接觸孔洞32 ’電性連接於η通道型薄膜電晶體 4之源極區域13而導通。又，在連通於η通道型薄膜電晶體4 之汲極區域14之接觸孔洞33，層疊設置作為導電層之信號 線之汲極電極42。此汲極電極42係經由接觸孔洞3 3，電性 連接於η通道型薄膜電晶體4之汲極區域14而導通。 在連通於ρ通道型薄膜電晶體5之源極區域13之接觸孔洞 34，層疊設置作為導電層之信號線之源極電極43。此源極 電極43係經由接觸孔洞34,電性連接於ρ通道型薄膜電晶體 5之源極區域13而導通。又，在連通於ρ通道型薄膜電晶體5 95517.doc -15- 1288845 之汲極區域14之接觸孔洞35，層疊設置作為導電層之信號 線之汲極電極44。此汲極電極44係經由接觸孔洞3 3，電性 連接於p通道型薄膜電晶體5之汲極區域14而導通。並且， 在連通於像素辅助電容6之電容部22之接觸孔洞3 6，層疊並 設置作為導電層之閘極抽取配線之抽取電極45。 另一方面，於包含各薄膜電晶體4、5之源極電極41、43 及汲極電極42、44，及像素輔助電容6之抽取電極45之層間 絕緣膜3 1上’以分別覆蓋此等薄膜電晶體4、5及像素辅助 電容6之方式層疊保護膜51而成膜。而且，於此保護膜51， 作為貫通此保護膜5 1之導通部之接觸孔洞52係開口而設 置。此接觸孔洞52連通於像素辅助電容6之抽取電極45而開 D 〇 於包含此接觸孔洞52之保護膜51上，層疊像素電極53而 成膜。此像素電極53經由接觸孔洞52，電性連接於抽取電 極45。亦即’此像素電極53經由抽取電極45，電性連接於 像素輔助電容6之電容部22。又，此像素電極53係由任一之 薄膜電晶體4、5所控制。並且，於包含此像素電極53之保 護膜51上，層疊定向膜54而成膜。 另一方面，與陣列基板2對向而配設矩形平板狀之對向基 板61。此對向基板61具備作為大致透明矩形平板狀之絕緣 基板之透光性基板之玻璃基板62。於此玻璃基板62之與陣 列基板2對向側之一主面，設置對向電極63。又。此對向電 極63上，層疊定向膜64而成膜。而且，液晶65夾持於此對 向基板61之定向膜64與陣列基板2之定向膜54之間。 95517.doc -16- 1288845 其次，說明上述第一實施型態之陣列基板之製造方法。 首先，以CVD(Chemical Vapor Deposition:化學氣相沈 積法），在玻璃基板3上，將膜厚50 nm之作為非晶半導體之 非晶矽之非晶矽膜成膜。此後，於此玻璃基板3上之非晶矽 膜照射準分子雷射光束（雷射退火），使結晶化，將此非晶矽 膜製成作為多晶半導體層之多晶碎膜71。此時，此多晶砍 膜'71之膜厚宜在40 nm以上、80 nm以下的範圍。 其次，藉由摻雜將二硼烷（B2H5)注入此多晶矽膜71，以 光微影工序製成島狀。此時，注入此多晶石夕膜71之删濃度 設定在1016/cm3以上、l〇17/cm3以下。再者，藉由於此多晶 石夕膜71注入硼，可控制各薄膜電晶體4、5之臨限值電壓。 並且，以PE(PlasmaEnhanced:電漿輔助）-CVD法，於包 含各島狀多晶石夕膜71之玻璃基板3上，將膜厚1〇〇 nm今閘極 絕緣膜15成膜。 其次，如圖2所示，於此閘極絕緣膜15上，將成為各薄膜 電晶體4、5之閘極電極16之膜厚300 nm之鉬-鎢合金（M〇 W) 成膜，形成第一導電層之第一金屬層72。此時，此第一金 屬層72之片電阻為〇·5 Ω /cm2。再者，除了鉬-鎢（m〇W)以 外，亦可成膜並形成鉬-鈕（MoTa)，以作為第一金屬層72。 此後，以光微影工序，將第一金屬層7 2除去p通道型薄膜 電晶體5之閘極電極16兩側之源極區域π及汲極區域14部 分之部分之未圖示之光阻圖案化，以含有氟及氧之混合氣 體’將此薄膜電晶體5之多晶石夕層π兩側進行電漿姓刻。此 時，此p通道型之閘極電極16之配線寬在1() _以上、2〇 , 95517.doc -17- 1288845 以下。 而且，進行此電漿蚀刻之I，以有機驗液將閘極絕緣膜 15上之光阻剥離。 在此狀恶，如圖3所示，將電漿蝕刻後殘留之第一金屬層 72作為掩模，於p通道型薄膜電晶體5之成為源極區域13及 汲極區域14之部分，藉由摻雜將p型摻雜物之二硼烷（B2h5) 注入。在此，此二硼烷之摻雜係為了降低多晶矽層n之電 阻值，取彳于與金屬之歐姆接觸。再者，此二硼烷對於多晶 矽層11之注入係加速電壓為5〇 keV，摻雜量為i〇15cm_2。 其次，以光微影工序，於第一金屬層72之11通道型薄膜電 晶體4之成為閘極電極16之部分及？通道型薄膜電晶體5之 部分，將未圖不之光阻圖案化，將此等n通道型薄膜電晶體 4之成為源極區域13及汲極區域14之部分，及成為輔助電容 6之邛刀，分別以含有氟及氧之混合氣體進行電漿蝕刻。此 時，此η通道型薄膜電晶體4之閘極電極16之配線寬在1〇 μηι以上、2.0 μχη以下。 而且，進行此電漿蝕刻之後，以有機鹼液將閘極絕緣膜 15上之光阻剝離。 此後，如圖4所示，以光微影工序，於第一金屬層72之η 通道型薄膜電晶體4之成為閘極電極16之部分及ρ通道型薄 膜電晶體5之部分，分別將光阻7〇圖案化，將η通道型薄膜 電晶體4之源極區域13及汲極區域14，及成為狀輔助電容6 之電谷部22之多晶矽層11，藉由摻雜將η型摻雜物之磷化氫 (ΡΗ3)注入。再者，此磷化氫對於多晶矽層丨丨之注入係加速 95517.doc -18- 1288845 電壓為70 keV，摻雜量為l〇15cm_2。 在此’使η通道型薄膜電晶體4為LDD(Lightly Doped Dram :低摻雜汲極）構造時，亦可進一步再度將此n通道型 薄膜電晶體4之成為閘極電極16之部分之第一金屬層72|虫 刻’縮小寬度尺寸之後，將η型摻雜物低摻雜，形成η•區域。 此時，此η通道型薄膜電晶體4之成為閘極電極16之第一 金屬層72作為同一掩模，分別可達成高摻雜及低摻雜，因 此可縮短LDD區域長度，同時可提升此η通道型薄膜電晶體 4之電晶體特性（離子特性）。 此後，將η通道型薄膜電晶體4及ρ通道型薄膜電晶體5分 別之源極區域13及汲極區域14，及像素輔助電容6之電容部 22,分別以4〇〇。(：以上、500°C以下之溫度進行熱退火處理， 將此等源極區域13、汲極區域14及電容部22活化。此時，ρ 通道型薄膜電晶體5之p+區域之源極區域13及汲極區域！ 4 分別之片電阻為3k Ω /cm2，η通道型薄膜電晶體4之n+區域 之源極區域13及汲極區域14分別之片電阻為2k Ω /cm2。 其次，如圖5所示，於各薄膜電晶體4、5之包含閘極電極 16之閘極絕緣膜15上，以低電阻材料，將連結此等薄膜電 晶體4、5之閘極電極16間之配線部π及像素辅助電容6之電 容配線部23之第二導電層之第二金屬層73成膜，此第二金 屬層73直接形成於閘極絕緣膜15上。 此時，作為第二金屬層73，其係由下層為鈦（Ti)/鋁-銅 (AlCu)/鈦（Ti)之各膜厚為5〇 nm/3〇〇 nm/75 nm之3層構造之 疊層膜。並且，此第二金屬層73之片電阻為〇·12 Q/cm2。再 95517.doc -19- 1288845 者’作為此第二金屬層73，亦可為鈦（Ti)/氮化鈦（TiN)/鋁_ 銅（AlCu)/鈦（Ti)/氮化鈦（TiN)之5層構造，或將鋁_銅變更為 純鋁之構造（例如：Ti/A1/Ti)，或鋁-鈥（A1Nd)“g(M〇)等。 此後，如圖6所示，以光微影工序，將第二金屬層73圖案 化’使成為連繫第一金屬層72之閘極電極丨6間之配線部i 7 及電容配線部23。此時，此第二金屬層73含有鋁（A1)或鋁_ 銅（AlCu)時’進行利用氯化金屬類氣體之乾式蝕刻。又， 此第二金屬層73含有鋁^^(A1Nd)時，進行濕式蝕刻。 其次，如圖7所示，以PE_CVD&，於包含此等配線部17 及電容配線部23之閘極絕緣膜15上，將膜厚600 nm之矽氧 化物成膜，形成層間絕緣膜3丨。 接著，如圖8所示，以光微影工序，形成分別連通於各薄 膜電晶體4、5之源極區域13及汲極區域14，及像素辅助電 容6之電容部22之接觸孔洞32、33、34、％、％。 此後，於分別包含此等接觸孔洞32、33、34、35、％之 層間絕緣膜31上，以濺鍍法，將例如··膜厚5〇11111之鉬（M〇) 及膜厚500 nm之鋁（A1)之疊層體成膜，以作為信號線配線 之導電層74。 接著，如圖9所示，以光微影工序將導電層74蝕刻，形成 源極電極41、43、汲極電極42、44及抽取電極45。此時， 以鋁（A1)或鋁-銅（A1Cu)等金屬形成此導電層”時，以氯氣 蝕刻，進行圖案化。 並且，如圖10所示，於包含此等源極電極41、43、汲極 電極42、44及抽取電極45之層間絕緣膜31上之全面，以 95517.doc -20- 1288845 ΡΕ-CVD法，將膜厚500㈣之氮化矽膜成膜，形成保護膜$卜 接著，以光微影工序將此保護膜51蝕刻，於此保護膜51， 形成導通於像素辅助電容6之抽取電極45之接觸孔洞52，此 時，作為此蝕刻係採用四氟化碳（CD氣體及氧氣之電漿蝕 刻。 此後，於包含此接觸孔洞52之保護膜51上，以濺鍍將透 明導電膜成膜並形成像素電極53之後，進行光微影工序及 I虫刻工序，將此像素電極5 3圖案化成像素形狀。此時，此 像素電極53之韻刻係採用蓓酸（H〇〇C-C〇〇H)。 在此，如以往，將n通道型薄膜電晶體及p通道型薄膜電 晶體之薄膜電晶體2層化，並連繫低電阻金屬之配線部時， 作為形成第二金屬層之工序，除了成膜工序、光微影工序 及蝕刻工序以外，作為形成電容部之工序，追加光微影工 序、n+摻雜工序及電阻剝離工序，因此工序數增加，生產 性劣化。 特別是若欲以多晶矽所構成之電容部、閘極絕緣膜及閘 極電極形成像素輔助電容，於形成此閘極電極之前，必須 於作為電容部之多晶矽層，藉由摻雜注入作為n型摻雜物之 構化氣（PH3)。 因此，如上述第-實施型態，像素辅助電容6作為以多晶 石夕構成之電容部22、閘極絕緣膜15、低電阻配線之第二金 屬層73所構成之電容配線23,使形成此像素輔助電㈣之電 容部22所需之n +摻雜’同時與n通道型薄臈電晶體4之源極 區域13及汲極區域μ之形成在同一工序進行。 95517.doc -21 - 1288845 結果，可刪減以往必要之電容形成工序，亦即光微影工 序、n+摻雜工序及光阻剝離工序。故，可將工序數抑制在 最小限度而將閘極電極16細線化及低電阻化，因此作為液 晶顯示裝置1 ’可高精細化、高開口率化及低耗電化，同時 可形成内建記憶體電路或至今TAB安裝之驅動電路之液晶 顯示裝置1。 又，η通道型薄膜電晶體4及p通道型薄膜電晶體5分別製 成閘極電極16及配線部17之2層構造。結果，於必須在熱活 性前形成之閘極電極16，使用耐熱性材料，於像素輔助電 谷6之電谷配線部2 3之牵繞長度較長之部分，使用低電阻材 料’並於熱活化後形成第二金屬層7 3。因此，可將此等薄 膜電晶體4、5分別之閘極電極16之配線電阻微細化及低電 阻化。 故’藉由將此等薄膜電晶體4、5之閘極電極16製成2層 化，並且變更像素輔助電容6之構造，可持續將陣列基板2 之工序數之增加抑制在最小限度，可將此等薄膜電晶體4、 5之閘極電極16低電阻化。 其次’參考圖11至圖19，說明本發明之第二實施型態之 液晶顯示裝置之構成。 此圖11至圖19所示之液晶顯示裝置1，基本上與圖1至圖 10所示之液晶顯示裝置1相同，在於包含閘極電極16之閘極 絕緣膜15上形成第一層間絕緣膜81之後，於此第一層間絕 緣膜81，形成作為連通於各閘極電極16之導通部之接觸孔 洞82、83之後’於包含此等接觸孔洞82、83之第一層間絕 95517.doc -22- 1288845 緣膜81上，將第二金屬層73成膜。 換言之，此液晶顯示裝置1係將層間絕緣膜31分成第一層 間絕緣膜81及第二層間絕緣膜84之2層而進行成膜，於此第 一層間絕緣膜81及第二層間絕緣膜84之間形成第二金屬層 73。亦即，此液晶顯示裝置1係於形成第一金屬層72之後， 經由第一層間絕緣膜81而形成第二金屬層73。 此第一層間絕緣膜81係層疊於包含各閘極電極16之閘極 絕緣膜15上而成膜，而且於此等各閘極電極16上之第一層 間絕緣膜81上，設置接觸孔洞82、83，其係朝向對於面向 垂直之方向貫通第一層間絕緣膜8丨者。此等接觸孔洞82、 83具有與各閘極電極16之寬度尺寸相等之寬度尺寸。而 且，於此等接觸孔洞82、83形成配線部17，此等配線部17 分別對於各閘極電極16電性地連接。 於包含此等配線部17及電容配線部23之第一層間絕緣膜 81上，層疊第二層間絕緣膜84而成膜。而且，於此等第二 層間絕緣膜84、第一層間絕緣膜81及閘極絕緣膜15，複數 接觸孔洞32、33、34、35、36.係開口，其係朝向正交於面 向之垂直方向之上下方向，分別貫通此等第二層間絕緣膜 84、第一層間絕緣膜81及閘極絕緣膜15者。 其次，說明上述第二實施型態之陣列基板之製造方法。 再者，於閘極絕緣膜15上形成閘極電極16為止之工序， 與上述第一實施型態之圖2至圖4所示工序相同。 而且，如圖12所示，以PE_CVD法，於包含各閘極電極w 之閘極絕緣膜15上，將膜厚50 nmi氧化矽物成膜，形成第 95517.doc -23- Ϊ288845 層間絕緣膜81。此時，此第一層間絕緣膜8丨之膜厚係在 像素輔助電谷6之電谷比製品規格之值大而決定。 其次，如圖13所示，以光微影工序，於第一層間絕緣膜 81开> 成為了與各閘極電極16接合之接觸孔洞μ、83。 此後，如圖14所示，於包含此等接觸孔洞82、83之第一 層間絕緣膜81上，以低電阻材料膜，將連結各閘極電極16 間之配線部17及成為像素輔助電容6之電容配線部23之第 一金屬層73成膜之後，如圖15所示，進行光微影工序之後， 進行蝕刻。在此，此等光微影工序及蝕刻工序係與上述第 一實施型態相同。 並且，如圖16所示，於包含各配線部17及電容配線部23 之第一層間絕緣膜81上，將膜厚6〇〇 nm之氧化矽物成膜， 形成第二層間絕緣膜84。 此後，如圖17所示，以光微影工序，形成貫通此第二層 間絕緣膜84、第一層間絕緣膜81及閘極絕緣膜15之複數接 觸孔洞 32、33、34、35、36。 並且’如圖1 8所示’於分別包含此等接觸孔洞3 3 3、 34、35、36之第二層間絕緣膜84上，將成為信號線配線之 導電層74成膜之後，以光微影工序將此導電層74蝕刻，形 成源極電極41、43、汲極電極42、44及抽取電極45。 其次，如圖19所示，於包含此等源極電極41、43、汲極 電極42、44及抽取電極45之層間絕緣膜31上之全面，以 PE-CVD法將氮化矽成膜，並形成保護膜51。 此後，以光微影工序，將此保護膜5丨蝕刻，形成接觸孔 95517.doc -24- 1288845 洞52之後，於包含此接觸孔洞52之保護膜51上，形成像素 電極5 3。 如上述’根據上述第二實施型態，使層間絕緣膜31成為 第一層間絕緣膜81及第二層間絕緣膜84之2層構造，因此相 較於上述第一實施型態，增加形成接觸孔洞82、83之工序。 但钱刻第二金屬層73之際，第一金屬層72之閘極電極16係 由第一層間絕緣膜81所保護，因此無須使用高選擇率餘 刻，因此第二金屬層73之蝕刻加工變得容易。 於姓刻笫一金屬層7 2之閘極電極16時，閘極絕緣膜1 $過 度蝕刻30 nm，因此，以閘極電極16及閘極絕緣膜15形成高 性能之薄膜電晶體4、5時，若此閘極絕緣膜1 5薄，成為像 素辅助電容6之部分之閘極絕緣膜15之膜厚.變薄。亦雷射退 火形成多晶矽膜71時，唯恐此多晶矽膜71表面形成突起。 因此’像素輔助電容6之電容部22之部分之閘極絕緣膜！ 5 之膜厚薄時，唯恐在多晶矽膜71所形成之電容部22與第二 金屬層73所形成之電容配線部23之間無法充分絕緣，此等 電容部22與電容配線部23之間會漏電。結果，唯恐於液晶 顯示裝置1產生點缺陷，良率下降。 故/於上述第二實施型態，閘極絕緣膜丨5之膜厚較薄（例 如· 90 nm以下）之液晶顯示裝置1之情況，尤其可提升生產 性。 、 再者，於上述各實施型態，亦可使像素輔助電容6之電容 部22與電容配線部23之間之電容為驅動液晶顯示裝置1之 電路部電容。 95517.doc -25- 1288845 作為第一金屬層72，亦可採用含有鉬（M〇)之合金，亦即 鉬-鎢（MoW)及鉬-钽（MoTa)之任一構成。 作為第二金屬層73，亦可採用含有鋁（A1)之合金，亦即 铭（A1)及紹-銅（AlCu)之至少任何一方，及鉬（Mo)、鈦（τ〇 ’ 及氮化鈦（TiN)之至少任一之疊層膜所構成。 · 【產業上之利用可能性】 根據本發明，可將工序數抑制在最小限度，將閘極配線 細線化及低電阻化，因此可形成具有一種薄膜電晶體之液 晶顯示裝置，該薄膜電晶體係可達成高開口率化、低耗電 _ 化’同時内建記憶體電路及以往TAB安裝之驅動電路。 【圖式簡單說明】 圖1係表示有關本發明之第一實施型態之液晶顯示裝置 之說明剖面圖。 圖2係表示在同上液晶顯示裝置之透光性基板上形成第 一導電層之狀態之說明剖面圖。 圖3係表示將成為同上液晶顯示裝置之卩通道型薄臈電晶 體之源極區域及汲極區域之部分摻雜之狀態之說明剖面 _ 圖。 圖4表示將成為同上液晶顯示裝置之n通道型薄膜電晶體 之源極區域及汲極區域之部分，及成為輔助電容之電容部 之部分摻雜之狀態之說明剖面圖。 · 圖5係表示在同上液晶顯示裝置之包含閘極電極之閘極 _ 絶緣膜上形成第二導電層之狀態之說明剖面圖。 圖6係表示將同上液晶顯示裝置之第二導電層圖案化之 95517.doc -26- 1288845 狀態之說明剖面圖。 圖7係表示在同上液晶顯示裝置之包含配線部及電容配 線部之閘極絕緣膜上形成層間絕緣膜之狀態之說明剖面 圖。 圖8係表示在同上液晶顯示裝置之層間絕緣膜形成接觸 孔洞之狀態之說明剖面圖。 圖9係表示將在同上液晶顯示裝置之包含接觸孔洞之層 間絕緣膜上形成之導電層圖案化之狀態之說明剖面圖。 圖10係表示在同上液晶顯示裝置之包含源極電極、汲極 電極及抽取電極之層間絕緣膜上形成保護膜之狀態之說明 剖面圖。 圖11係表示有關本發明之第二實施型態之液晶顯示裳置 之說明剖面圖。 圖12係表示在同上液晶顯示裝置之包含閘極電極之閘極 絕緣膜上形成第一層間絕緣膜之狀態之說明剖面圖。 圖13係表示在同上液晶顯示裝置之第一層間絕緣膜形成 接觸孔洞之狀態之說明剖面圖。 圖14係表示在同上液晶顯示裝置之包含接觸孔洞之第一 層間絕緣膜上形成第二金屬層之狀態之說明剖面圖。 圖15係表示將同上液晶顯示裝置之第二金屬層圖案化之 狀態之說明剖面圖。 圖16係表示在同上液晶顯示裝置之包含配線部及電容配 線部之閘極絕緣膜上形成第二層間絕緣膜之狀態之說明剖 面圖。 95517.doc -27- 1288845 圖17係表示在同上液晶顯示裝置之第二層間絕緣膜形成 接觸孔洞之狀態之說明剖面圖。 圖18係表示將在同上液晶顯示裝置之包含接觸孔洞之第 二層間絕緣膜上形成之導電層圖案化之狀態之說明剖面 圖。 圖19係表示在同上液晶顯示裝置之包含源極電極、汲極 電極及抽取電極之第二層間絕緣膜上形成保護膜之狀態之 說明剖面圖。 【主要元件符號說明】 1 液晶顯示裝置 2 陣列基板 3、62 玻璃基板 4 η通道型薄膜電晶體 5 Ρ通道型薄膜電晶體 6 像素輔助電容 11 多晶秒層 12 通道區域 13 /原極區域 14 汲極區域 15 閘極絕緣膜 16 閘極電極 17 配線部 22 電容部 23 電容配線部 95517doc -28- 1288845 31 層間絕緣膜 32-36 、 52 、 82 、 83 接觸孔洞 41、43 源極電極 42、44 汲極電極 45 抽取電極 51 保護膜 53 像素電極 54、64 定向膜 61 對向基板 63 對向電極 65 液晶 71 多晶矽膜 72 第一金屬層 73 第二金屬層 74 導電層 81 第一層間絕緣膜 84 第二層間絕緣膜1288845 and other impurities, made into n-type or p-type method. Specifically, a method of manufacturing an array substrate for a liquid crystal display device is to form a polycrystalline semiconductor layer after performing a surface beam semiconductor layer on a glass substrate, and then patterning the amorphous semiconductor layer into a polycrystalline semiconductor layer. Thereafter, a gate insulating film is formed on the glass substrate including the polycrystalline semiconductor layer. At this time, the material auxiliary capacitor is not larger than a certain level, and the pixel auxiliary capacitor cannot be held. Therefore, the film thickness of the gate insulating film should be as thin as possible. Therefore, a gate insulating film is formed on the matte semiconductor layer, and this is the structure in which the insulating film forms a layer of the gate electrode. Therefore, before the gate electrode is formed, the photoresist is patterned, and the n-type dopant (PH3) is doped by doping to form an n+ region of the thin film transistor (TFT), a pixel capacitance, and a circuit portion. The capacitance part of the capacitor area. Further, after the gate electrode is formed on each of the gate insulating films including the n+ region, the pixel capacitor, and the capacitor portion of the circuit portion, the gate electrode pattern for the thin film transistor (TFT) is formed. After the formation, a p-type dopant (Β#5) was implanted as an impurity to form a p+ region of the p_ch thin film transistor. Next, after patterning the gate electrode on the n-ch thin film transistor side, after annealing the n-ch thin film transistor and the p-ch thin film transistor, respectively, the n+ region of the n-ch thin film transistor is made. The p+ regions of the p-ch thin film transistor are respectively activated, and secondly, the interlayer insulating film is formed on the gate insulating film including the gate electrodes of the n_ch and p-ch thin film transistors. Further, after the interlayer insulating film forms a contact hole, connects the n+ region of the n-ch thin film transistor and the P+ region of the p-ch thin film transistor, a conductive layer is formed on the interlayer insulating film including the contact holes. Thereafter, this conductive layer 95517. Doc 1288845 is patterned to form a source electrode and a drain electrode electrically connected to the n+ region of the n-ch thin film transistor and the P+ region of the p-ch thin film transistor. This configuration is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2002-/359252 (pages 7-10, Figs. 8 to 9). In the liquid crystal display device, a molybdenum-containing alloy such as molybdenum-tungsten (M〇W) or molybdenum-knuckle (MoTa) is used as the gate wiring system. Further, the gate electrode of the liquid crystal display device and the extraction line of the gate wiring, the pixel capacitor wiring, and the circuit capacitor wiring are integrally formed in one layer. The pin alloy has heat resistance and is resistant to 5 〇〇 ° C or more and 6 〇〇. (3) The thermal activation material of the thermal activation is used for the gate electrode. However, since the sheet resistance of the molybdenum alloy with a film thickness of 300 nm is as high as 〇_5 Ω/cm2, if the wire is thinned, the resistance is Since the gate electrode is made high, it is impossible to make the gate electrode fine. In order to make the gate electrode low in resistance, a material having a lower resistance than a molybdenum alloy, for example, aluminum having a versatile aluminum (A1) or aluminum-copper (AlCu) is used. The alloy may be: However, as for the alloy, the friction is likely to be short-circuited due to the thermal activation in the subsequent process, so that the resistance is deteriorated or disconnected due to electromigration = eCtr〇migration. The problem caused by the deterioration of reliability. That is, at the time of heat activation, # annealing the Ming or Ming alloy at a high temperature, and a projection is generated, and the wiring is easily short-circuited. Therefore, it is difficult to reduce the resistance of the gate electrode from the viewpoint of the process. In the case of using the 钕-钕 (side), even if it is annealed below the sound c, the reliability does not occur, but there are still problems in processing accuracy and productivity. That is, if you know the use of this aluminum-convergence, thinning it to 2 μηι 955l7. Doc 1288845' is difficult to control the variation of the line width in wet etching, so the variation of the length of the idle electrode of the thin film electrode becomes large. Therefore, since the crystal characteristics of the thin film transistor are changed, the dry type insect in which the change can be controlled is processed. SUMMARY OF THE INVENTION When the gate electrode of the liquid crystal display device is aluminum-titanium, when the gate electrode is dry-type, an etching product such as aluminum chloride (A1C12) is attached to the dry etching apparatus in a large amount. The inner wall surface is not easy to improve the production. In the case of a product requiring a thin electrode of a gate electrode, it is difficult to use aluminum-bismuth as a gate electrode from the viewpoint of processing. Therefore, there is a problem that it is difficult to thin the gate electrode and reduce the resistance. The present invention has been made in view of the above, and an object thereof is to provide an array substrate, a liquid crystal display device, and a method of manufacturing an array substrate which can thin the first conductive layer and reduce the resistance. The array substrate according to the aspect of the invention includes: a light-transmitting substrate; a plurality of polycrystalline semiconductor layers provided on one of the main faces of the light-transmitting substrate; and a gate insulating film which is provided in the plural a main surface of the light-transmitting substrate of the polycrystalline semiconductor layer; a first conductive layer disposed opposite to any one of the plurality of polycrystalline semiconductor layers via the gate insulating film; and a conductive a layer having: a wiring portion provided on one main surface of the first conductive layer and electrically connected to the first conductive layer; and a capacitor wiring portion which is any other of the plurality of polycrystalline semiconductor layers Opposite through the aforementioned 95517. Doc -10- 1288845 The gate insulating film is placed to form a capacitor between this polycrystalline semiconductor layer. Further, a liquid crystal display device according to another aspect of the present invention includes: an array, a substrate, and a translucent substrate; and a plurality of polycrystalline semiconductor layers which are not one of the main faces of the translucent substrate; a gate insulating film which is provided on one of the main faces of the light-transmitting substrate including the plurality of polycrystalline semiconductor layers, and the first conductive layer is opposed to any of the plurality of polycrystalline semiconductor layers The gate insulating film is provided; and the second conductive layer is provided with a wiring portion which is provided on one main surface of the first conductive layer and electrically connected to the first conductive layer; and a capacitor a wiring portion which is provided through the gate insulating film in any other direction opposite to the plurality of polycrystalline semiconductor layers, forms a capacitor between the planar semiconductor layer, and a counter substrate, and the array substrate The opposite device and the liquid crystal are interposed between the opposite substrate and the array substrate. Further, a method of manufacturing an array substrate according to another aspect of the present invention is characterized in that: a plurality of polycrystalline semiconductor layers are provided on one main surface of the light-transmitting substrate; and the light-transmitting substrate is formed on the plurality of polycrystalline semiconductor layers. a main insulating surface is provided with a gate insulating film; a first conductive layer is disposed on one main surface of the gate insulating film; and the first conductive layer is patterned to form any one of the plurality of polycrystalline semiconductor layers For the gate electrode; using any one of the pair of gate electrodes as a mask, doping the polycrystalline semiconductor layer opposite to the gate electrode as a source region of the P-type switching device and 汲Polar region; 95517. Doc 11 1288845 These 1 pair of gate poles are opposite to the aforementioned polycrystalline semiconductor:: Other: as a mask, in the (4) sense conductor layer, and the description of the gate electrode is not opposite to the opposite = M semiconductor Each of the layers is doped to form a source region of the n-type switching device and a capacitor region of the material region and the auxiliary capacitor; the main surface of the gate insulating film including the pair of gate electrodes is formed as a conductive layer; Patterning the second conductive layer to form the pair of gate electrodes opposite to the pair of gate portions and the pair of gate electrodes are not paired with (4) the auxiliary semiconductor capacitors facing the polycrystalline semiconductor layer Capacitor section. [Embodiment], > Test 1 to Fig. 10, a configuration of a liquid crystal display device according to a first embodiment of the present invention will be described. 1 to 10, a liquid crystal display device as a flat display device is a thin film transistor liquid crystal display device having an array of earth plates having a substantially rectangular flat shape. The itb array substrate 2 has a glass substrate 3 as a substantially transparent rectangle. A light-transmissive substrate of a flat insulating substrate. On the surface of one of the main surfaces of the glass substrate 3, an undercoat layer (not shown) made of a nitride film or an oxygen cut film is laminated to form a film. On the undercoat layer, a plurality of n-ch type thin film transistors (TFTs) 4, which are n-type switching elements for liquid crystal display, are formed in a matrix. Further, on the undercoat layer, a plurality of p-channel type thin film transistors (TFTs) 5 as P-type switching elements for liquid crystal display and a plurality of pixel auxiliary capacitors 6 as auxiliary capacitors are formed in plural numbers. Matrix shape. Here, these thin film transistors 4, 5 are each used! Pixel components and 95517. Doc -12- 1288845 set. Further, these thin film transistors 4, 5 each have a polycrystalline germanium layer 11 as a polycrystalline semiconductor layer formed on the undercoat layer. This polycrystalline germanium layer η is formed by using a polycrystalline stone formed by a laser annealing of a non-neuterium semiconductor. Further, the multi-day day ♦ layer u has a channel region 12 which is provided as an active layer in the central portion of the polycrystalline dream layer u. The η region on both sides of the channel region or the source region 13 and the immersion region of the p region are opposed to each other. A gate insulating film having an insulating ruthenium oxide film is laminated on the undercoat layer including the channel region 12, the source region 13 and the electrodeless region 分别, respectively. Further, on the gate insulating film 15 opposed to the channel region 12, the gate electrode 16 is formed by the gate electrode 16 composed of the first metal layer 72 as the first conductive layer. The first metal layer 72 is composed of an alloy containing molybdenum (ruthenium), that is, molybdenum-tungsten (MoW). Here, the gate electrodes 6 are opposed to the channel regions 12 of the respective thin film transistors 4, 5 via the gate insulating film 15, and have a width dimension substantially equal to the width dimension of the channel region 12. On the gate electrodes 16, a wiring portion 作为7 as a gate wiring composed of a second metal layer 73 as a second conductive layer is laminated. These wiring portions 17 are electrically connected to the gate electrodes 16, respectively, and have gate-to-electrode wirings having a width dimension equal to the width dimension of each of the gate electrodes 16. Here, these wiring portions 17 are composed of a material having a smaller resistance value than the gate electrode 16. On the other hand, on the undercoat layer continuous to the thin film transistors 4, 5, a pixel auxiliary capacitor 6 composed of polycrystalline germanium is laminated and formed. The pixel auxiliary capacitor 6 is disposed adjacent to the p-channel type thin film transistor 5, and is disposed through the film 95517. Doc -13- 1288845 The opposite side of the n-channel type thin film transistor 4 of the transistor 5. This pixel auxiliary capacitor 6 is disposed on the same plane as the thin film transistors 4, 5 on the glass substrate 3. Further, the pixel auxiliary capacitor 6 is provided with a capacitor portion 22 formed of polycrystalline stone. The capacitor portion 22 is formed by using a polysilicon formed by laser annealing of an amorphous germanium as an amorphous semiconductor. Further, the capacitor portion 2 is formed by the same process as the polycrystalline layer 11 of each of the thin film transistors 4 and 5, and laminated on the undercoat layer. On the undercoat layer of the capacitor portion 22 included, the gate insulating film 15 is laminated to form a film. Further, on the gate insulating film 15 opposed to the capacitor portion 22, a capacitor wiring portion 23 composed of a second metal layer 73 of the same layer as the wiring portion 17 of each of the thin film transistors 4, 5 is laminated. The capacitor wiring portion 23 is provided on one side in the width direction of the capacitor portion 22 on the side of the p-channel type thin film transistor 5. In other words, the capacitor wiring portion 23 is provided closer to the side of the p-channel type thin film transistor 5 than the central portion in the width direction of the capacitor portion 22. The capacitor wiring portions 23 respectively form a capacitance between the capacitor portions 22 via the gate insulating film 15 between the capacitor wiring portions 23 and the capacitor portions 22. Here, the capacitor wiring portions 23 are formed in the same process and the same material as the wiring portions 17 of the thin film transistors 4 and 5. Therefore, the capacitor wiring portion 23 has a resistance value smaller than the resistance value of the wiring portion 17 of each of the thin film transistors 4, 5. On the gate insulating film 15 including the capacitor wiring portion 23 and the wiring portions 17 of the thin film transistors 4 and 5, an interlayer insulating film 31 having an insulating oxidized oxide film is laminated. Further, in the interlayer insulating film 31 and the gate insulating film 15, the plurality of contact holes 32, 33, 34, 35, 36 are opened, 95517. Doc - 14 - 1288845 is a conduction portion that penetrates the interlayer insulating film 31 and the gate insulating film 15, respectively. Here, the contact holes 32, 33 are respectively provided on both sides of the gate electrode 16 of the n-channel type thin germanium transistor 4, the source region 13 of the thin film transistor 4, and the drain region 14. Further, the contact hole 32 is opened to communicate with the source region 13 of the n-channel type thin film transistor 4, and the contact hole 3 is opened to communicate with the drain region 14 of the n-channel type thin film transistor 4. Contact holes 34, 35 are respectively provided on both sides of the gate electrode 16 of the p-channel type thin film transistor 5, the source region 13 and the drain region 14 of the thin film transistor 5. Further, the contact hole 34 is opened to communicate with the source region 13 of the p-channel type thin film transistor 5, and the contact hole 35 is opened to communicate with the drain region 14 of the p-channel type thin film transistor 5. Further, the contact hole 36 is opened to communicate with the capacitance portion 22 of the pixel auxiliary capacitor 6. A contact hole 32' connected to the source region 13 of the n-channel type thin film transistor 4 is provided with a source electrode 4' as a signal line of the conductive layer. The source electrode 41 is electrically connected to the source region 13 of the n-channel type thin film transistor 4 via the contact hole 32'. Further, a drain electrode 42 as a signal line of the conductive layer is laminated on the contact hole 33 which is connected to the drain region 14 of the n-channel type thin film transistor 4. The drain electrode 42 is electrically connected to the drain region 14 of the n-channel type thin film transistor 4 via the contact hole 33, and is electrically connected. A source electrode 43 as a signal line of the conductive layer is laminated on the contact hole 34 which is connected to the source region 13 of the p-channel type thin film transistor 5. The source electrode 43 is electrically connected to the source region 13 of the p-channel type thin film transistor 5 via the contact hole 34. Also, in communication with the p-channel type thin film transistor 5 95517. The contact hole 35 of the drain region 14 of doc -15- 1288845 is laminated with a drain electrode 44 as a signal line of the conductive layer. The drain electrode 44 is electrically connected to the drain region 14 of the p-channel type thin film transistor 5 via the contact hole 33. Further, an extraction electrode 45 as a gate extraction wiring of the conductive layer is laminated and provided in a contact hole 36 connected to the capacitance portion 22 of the pixel storage capacitor 6. On the other hand, on the interlayer insulating film 3 1 including the source electrodes 41 and 43 and the drain electrodes 42 and 44 of the respective thin film transistors 4 and 5, and the extraction electrode 45 of the pixel auxiliary capacitor 6, respectively, The protective film 51 is formed by laminating the thin film transistors 4 and 5 and the pixel auxiliary capacitor 6. Further, the protective film 51 is provided as a contact hole 52 that penetrates the conduction portion of the protective film 51. The contact hole 52 is connected to the extraction electrode 45 of the pixel storage capacitor 6 to be opened on the protective film 51 including the contact hole 52, and the pixel electrode 53 is stacked to form a film. The pixel electrode 53 is electrically connected to the extraction electrode 45 via the contact hole 52. That is, the pixel electrode 53 is electrically connected to the capacitance portion 22 of the pixel auxiliary capacitor 6 via the extraction electrode 45. Further, the pixel electrode 53 is controlled by any of the thin film transistors 4, 5. Further, on the protective film 51 including the pixel electrode 53, the alignment film 54 is laminated to form a film. On the other hand, a rectangular flat plate-shaped opposing substrate 61 is disposed opposite to the array substrate 2. The counter substrate 61 is provided with a glass substrate 62 which is a translucent substrate of an insulating substrate having a substantially transparent rectangular plate shape. On the main surface of the glass substrate 62 on the opposite side to the array substrate 2, a counter electrode 63 is provided. also. On the counter electrode 63, the alignment film 64 is laminated to form a film. Further, the liquid crystal 65 is sandwiched between the alignment film 64 of the opposite substrate 61 and the alignment film 54 of the array substrate 2. 95517. Doc -16 - 1288845 Next, a method of manufacturing the array substrate of the first embodiment described above will be described. First, an amorphous germanium film of amorphous amorphous film having a thickness of 50 nm is formed on a glass substrate 3 by CVD (Chemical Vapor Deposition). Thereafter, the amorphous ruthenium film on the glass substrate 3 is irradiated with a pseudo-molecular laser beam (laser annealing) to be crystallized, and this amorphous ruthenium film is formed into a polycrystalline semiconductor film 71 as a polycrystalline semiconductor layer. At this time, the film thickness of the polycrystalline chopping film '71 is preferably in the range of 40 nm or more and 80 nm or less. Next, diborane (B2H5) is implanted into the polycrystalline germanium film 71 by doping to form an island shape by a photolithography process. At this time, the concentration of the polycrystalline stone film 71 to be injected is set to be 1016 / cm 3 or more and 10 17 / cm 3 or less. Further, by implanting boron into the polycrystalline silicon film 71, the threshold voltage of each of the thin film transistors 4, 5 can be controlled. Further, a film thickness of 1 〇〇 nm of the gate insulating film 15 is formed on the glass substrate 3 including the island-shaped polycrystalline film 71 by a PE (Plasma Enhanced: CVD) method. Next, as shown in FIG. 2, a molybdenum-tungsten alloy (M〇W) having a thickness of 300 nm which is a gate electrode 16 of each of the thin film transistors 4 and 5 is formed on the gate insulating film 15 to form a film. The first metal layer 72 of the first conductive layer. At this time, the sheet resistance of this first metal layer 72 is 〇·5 Ω / cm 2 . Further, in addition to molybdenum-tungsten (m〇W), a molybdenum-button (MoTa) may be formed as the first metal layer 72. Thereafter, in the photolithography process, the first metal layer 7 2 is removed from the source region π on both sides of the gate electrode 16 of the p-channel type thin film transistor 5 and a portion of the drain region 14 is not shown. Patterning, the mixed gas containing fluorine and oxygen 'the plasma crystal 5 of the polycrystalline stone layer π on both sides of the plasma surname. At this time, the wiring width of the p-channel type gate electrode 16 is 1 () _ or more, 2 〇, 95517. Doc -17- 1288845 below. Further, by performing this plasma etching I, the photoresist on the gate insulating film 15 is peeled off by an organic liquid. In this case, as shown in FIG. 3, the first metal layer 72 remaining after the plasma etching is used as a mask, and the portion of the p-channel type thin film transistor 5 which becomes the source region 13 and the drain region 14 is borrowed. The p-type dopant diborane (B2h5) is implanted by doping. Here, the doping of the diborane is based on the ohmic contact with the metal in order to lower the resistance value of the polysilicon layer n. Further, the injection of the diborane to the polycrystalline germanium layer 11 has an accelerating voltage of 5 〇 keV and a doping amount of i 〇 15 cm 2 . Next, in the photolithography process, the 11-channel type thin film transistor 4 of the first metal layer 72 becomes part of the gate electrode 16 and ? Part of the channel-type thin film transistor 5 is patterned by a photoresist which is not shown, and the n-channel thin film transistor 4 is part of the source region 13 and the drain region 14, and becomes the auxiliary capacitor 6. The knives are plasma etched with a mixed gas containing fluorine and oxygen, respectively. At this time, the wiring width of the gate electrode 16 of the n-channel type thin film transistor 4 is wider than 1 〇 μηι, 2. 0 μχη or less. Further, after this plasma etching, the photoresist on the gate insulating film 15 is peeled off with an organic alkali solution. Thereafter, as shown in FIG. 4, in the photolithography process, the light is applied to the portion of the n-channel type thin film transistor 4 of the first metal layer 72 which becomes the portion of the gate electrode 16 and the portion of the p-channel type thin film transistor 5, respectively. The pattern is patterned, and the source region 13 and the drain region 14 of the n-channel thin film transistor 4 and the polysilicon layer 11 of the electric valley portion 22 of the auxiliary capacitor 6 are doped by n-type doping. The phosphine (ΡΗ3) is injected. Furthermore, this phosphine accelerates the injection of polycrystalline germanium layer 95517. Doc -18- 1288845 The voltage is 70 keV and the doping amount is l〇15cm_2. Here, when the n-channel type thin film transistor 4 is an LDD (Lightly Doped Dram) structure, the n-channel type thin film transistor 4 can be further made into a portion of the gate electrode 16 After a metal layer 72|inserts' reduced width dimension, the n-type dopant is doped low to form an η• region. At this time, the first metal layer 72 of the n-channel type thin film transistor 4 serving as the gate electrode 16 serves as the same mask, respectively, achieving high doping and low doping, thereby shortening the length of the LDD region and improving the length The transistor characteristics (ion characteristics) of the n-channel type thin film transistor 4. Thereafter, the source region 13 and the drain region 14 of the n-channel type thin film transistor 4 and the p-channel type thin film transistor 5, and the capacitance portion 22 of the pixel auxiliary capacitor 6 are respectively 4 Å. (: The above is performed at a temperature of 500 ° C or lower, and the source region 13 , the drain region 14 , and the capacitor portion 22 are activated. At this time, the source region of the p + region of the p channel type thin film transistor 5 13 and the drain region! 4 The respective sheet resistance is 3k Ω /cm2, and the sheet resistance of the source region 13 and the drain region 14 of the n+ region of the n-channel type thin film transistor 4 is 2k Ω /cm 2 respectively. As shown in FIG. 5, the wiring between the gate electrodes 16 of the thin film transistors 4 and 5 is connected to the gate insulating film 15 including the gate electrode 16 of each of the thin film transistors 4 and 5 with a low-resistance material. The portion π and the second metal layer 73 of the second conductive layer of the capacitor wiring portion 23 of the pixel auxiliary capacitor 6 are formed, and the second metal layer 73 is directly formed on the gate insulating film 15. At this time, as the second metal layer 73. The lower layer is a laminated film of a three-layer structure in which each film thickness of titanium (Ti)/aluminum-copper (AlCu)/titanium (Ti) is 5 〇nm/3〇〇nm/75 nm. The sheet resistance of the second metal layer 73 is 〇·12 Q/cm 2 . Then 95517. Doc -19- 1288845 'As this second metal layer 73, may also be titanium (Ti) / titanium nitride (TiN) / aluminum _ copper (AlCu) / titanium (Ti) / titanium nitride (TiN) 5 Layer structure, or a structure in which aluminum-copper is changed to pure aluminum (for example, Ti/A1/Ti), or aluminum-germanium (A1Nd) "g(M〇), etc. Thereafter, as shown in Fig. 6, In the shadowing process, the second metal layer 73 is patterned to form the wiring portion i 7 and the capacitor wiring portion 23 between the gate electrodes 6 of the first metal layer 72. At this time, the second metal layer 73 contains aluminum. (A1) or aluminum _ copper (AlCu) 'dry etching using a chlorinated metal-based gas. Further, when the second metal layer 73 contains aluminum (A1Nd), wet etching is performed. Next, as shown in FIG. As shown in the figure, on the gate insulating film 15 including the wiring portion 17 and the capacitor wiring portion 23, a film of a thickness of 600 nm is formed into a film by PE_CVD & As shown in FIG. 8, in the photolithography process, the contact holes 32, 33, 34 which are respectively connected to the source region 13 and the drain region 14 of each of the thin film transistors 4 and 5, and the capacitance portion 22 of the pixel auxiliary capacitor 6 are formed. %, %. Thereafter, on the interlayer insulating film 31 including the contact holes 32, 33, 34, 35, and %, respectively, a molybdenum (M〇) having a film thickness of 5〇11111 and a film thickness of 500 nm are deposited by sputtering. The laminate of aluminum (A1) is formed into a film as a conductive layer 74 for signal line wiring. Next, as shown in FIG. 9, the conductive layer 74 is etched by a photolithography process to form source electrodes 41, 43, and 汲. The electrode electrodes 42 and 44 and the extraction electrode 45. In this case, when the conductive layer is formed of a metal such as aluminum (A1) or aluminum-copper (A1Cu), it is patterned by chlorine etching. Further, as shown in Fig. 10, on the interlayer insulating film 31 including the source electrodes 41, 43, the drain electrodes 42, 44 and the extraction electrode 45, it is 95517. Doc -20- 1288845 ΡΕ-CVD method, forming a film of a tantalum nitride film having a thickness of 500 (4) to form a protective film. Then, the protective film 51 is etched by a photolithography process, and the protective film 51 is formed to be electrically connected thereto. The contact hole 52 of the extraction electrode 45 of the pixel auxiliary capacitor 6 is used, and at this time, as the etching system, plasma etching of carbon tetrafluoride (CD gas and oxygen gas is used. Thereafter, on the protective film 51 including the contact hole 52, After the transparent conductive film is formed by sputtering and the pixel electrode 53 is formed, the photolithography process and the I-etching process are performed, and the pixel electrode 53 is patterned into a pixel shape. At this time, the pixel electrode 53 is rhodium-engraved. Acid (H〇〇CC〇〇H). Here, when the thin film transistor of the n-channel type thin film transistor and the p-channel type thin film transistor is layered and connected to the wiring portion of the low-resistance metal, In the step of forming the second metal layer, in addition to the film formation step, the photolithography step, and the etching step, the photolithography step, the n+ doping step, and the resistance stripping step are added as the step of forming the capacitor portion, so that the number of steps is increased. Productive deterioration. If the capacitor portion, the gate insulating film, and the gate electrode formed by the polysilicon are to form a pixel auxiliary capacitor, before forming the gate electrode, the polysilicon layer as the capacitor portion must be doped as an n-type doping by doping implantation. The constituent gas of the impurity (PH3). Therefore, as in the above-described first embodiment, the pixel auxiliary capacitor 6 serves as the capacitor portion 22 composed of polysilicon, the gate insulating film 15, and the second metal layer of the low resistance wiring. The capacitor wiring 23 formed of 73 forms the n + doping ' required for forming the capacitance portion 22 of the pixel auxiliary electric (four) simultaneously with the source region 13 and the drain region μ of the n-channel thin germanium transistor 4 The same process is carried out. 95517. Doc -21 - 1288845 As a result, it is possible to delete the necessary capacitance forming processes, that is, the photolithography process, the n+ doping process, and the photoresist peeling process. Therefore, the number of processes can be minimized, and the gate electrode 16 can be thinned and reduced in resistance. Therefore, the liquid crystal display device 1 can be made high-definition, high in aperture ratio, low in power consumption, and can be built in. A liquid crystal display device 1 of a memory circuit or a drive circuit mounted to the TAB to date. Further, the n-channel type thin film transistor 4 and the p-channel type thin film transistor 5 have a two-layer structure of the gate electrode 16 and the wiring portion 17, respectively. As a result, a heat-resistant material is used for the gate electrode 16 which must be formed before the thermal activity, and a low-resistance material is used in the portion where the winding length of the electric valley wiring portion 23 of the pixel-assisted electric valley 6 is long. The second metal layer 73 is formed after activation. Therefore, the wiring resistance of the gate electrode 16 of each of the thin film transistors 4 and 5 can be made finer and lower in resistance. Therefore, by forming the gate electrodes 16 of the thin film transistors 4 and 5 into two layers and changing the structure of the pixel auxiliary capacitor 6, the increase in the number of steps of the array substrate 2 can be kept to a minimum. The gate electrodes 16 of the thin film transistors 4 and 5 are reduced in resistance. Next, the configuration of a liquid crystal display device of a second embodiment of the present invention will be described with reference to Figs. 11 to 19 . The liquid crystal display device 1 shown in FIGS. 11 to 19 is basically the same as the liquid crystal display device 1 shown in FIGS. 1 to 10, in which the first interlayer insulating film is formed on the gate insulating film 15 including the gate electrode 16. After the film 81, the first interlayer insulating film 81 is formed as contact holes 82, 83 which are connected to the conductive portions of the gate electrodes 16, and then the first layer 95517 including the contact holes 82, 83. . Doc -22- 1288845 On the edge film 81, the second metal layer 73 is formed into a film. In other words, the liquid crystal display device 1 divides the interlayer insulating film 31 into two layers of the first interlayer insulating film 81 and the second interlayer insulating film 84, and the first interlayer insulating film 81 and the second interlayer insulating film are formed. A second metal layer 73 is formed between the films 84. That is, the liquid crystal display device 1 is formed after the first metal layer 72 is formed, and the second metal layer 73 is formed via the first interlayer insulating film 81. The first interlayer insulating film 81 is formed by laminating on the gate insulating film 15 including the gate electrodes 16, and is provided on the first interlayer insulating film 81 on each of the gate electrodes 16 to be in contact with each other. The holes 82, 83 are oriented to penetrate the first interlayer insulating film 8 in a direction perpendicular to the direction. These contact holes 82, 83 have a width dimension equal to the width dimension of each of the gate electrodes 16. Further, the contact holes 82 and 83 form the wiring portion 17, and the wiring portions 17 are electrically connected to the gate electrodes 16, respectively. The second interlayer insulating film 84 is laminated on the first interlayer insulating film 81 including the wiring portion 17 and the capacitor wiring portion 23. Further, the second interlayer insulating film 84, the first interlayer insulating film 81 and the gate insulating film 15, and the plurality of contact holes 32, 33, 34, 35, 36. The opening is formed so as to penetrate the second interlayer insulating film 84, the first interlayer insulating film 81, and the gate insulating film 15, respectively, in a direction perpendicular to the vertical direction of the surface. Next, a method of manufacturing the array substrate of the second embodiment will be described. The step of forming the gate electrode 16 on the gate insulating film 15 is the same as the step shown in Figs. 2 to 4 of the first embodiment. Further, as shown in FIG. 12, a 50 nmi cerium oxide film is formed on the gate insulating film 15 including the gate electrodes w by a PE_CVD method to form a 95517. Doc -23- Ϊ288845 Interlayer insulating film 81. At this time, the film thickness of the first interlayer insulating film 8 is determined by the value of the electric valley of the pixel-assisted electric valley 6 being larger than the value of the product specification. Then, as shown in Fig. 13, in the photolithography process, the first interlayer insulating film 81 is opened and the contact holes μ and 83 which are bonded to the gate electrodes 16 are formed. Thereafter, as shown in FIG. 14, on the first interlayer insulating film 81 including the contact holes 82, 83, the wiring portion 17 connecting the gate electrodes 16 and the pixel auxiliary capacitor are connected by a low-resistance material film. After the first metal layer 73 of the capacitor wiring portion 23 of 6 is formed, as shown in FIG. 15, after the photolithography process, etching is performed. Here, the photolithography process and the etching process are the same as those of the first embodiment described above. Further, as shown in FIG. 16, a ruthenium oxide having a thickness of 6 Å is formed on the first interlayer insulating film 81 including the wiring portion 17 and the capacitor wiring portion 23, and a second interlayer insulating film 84 is formed. . Thereafter, as shown in FIG. 17, a plurality of contact holes 32, 33, 34, 35, 36 penetrating through the second interlayer insulating film 84, the first interlayer insulating film 81, and the gate insulating film 15 are formed by a photolithography process. . And, as shown in FIG. 18, on the second interlayer insulating film 84 including the contact holes 3 3 3, 34, 35, 36, respectively, after the conductive layer 74 which becomes the signal line wiring is formed into a film, The conductive layer 74 etches the conductive layer 74 to form the source electrodes 41 and 43, the drain electrodes 42, 44, and the extraction electrode 45. Next, as shown in FIG. 19, on the interlayer insulating film 31 including the source electrodes 41, 43, the drain electrodes 42, 44 and the extraction electrode 45, a tantalum nitride film is formed by a PE-CVD method. And a protective film 51 is formed. Thereafter, the protective film 5 is etched by a photolithography process to form a contact hole 95517. Doc - 24 - 1288845 After the hole 52, a pixel electrode 53 is formed on the protective film 51 including the contact hole 52. As described above, according to the second embodiment described above, the interlayer insulating film 31 has a two-layer structure of the first interlayer insulating film 81 and the second interlayer insulating film 84, so that contact is increased as compared with the first embodiment described above. The steps of the holes 82, 83. However, when the second metal layer 73 is engraved, the gate electrode 16 of the first metal layer 72 is protected by the first interlayer insulating film 81, so that it is not necessary to use a high selectivity margin, so the etching of the second metal layer 73 is performed. Processing becomes easy. When the gate electrode 16 of the metal layer 7 2 is engraved, the gate insulating film 1 is over-etched by 30 nm, and thus the high-performance thin film transistor 4, 5 is formed by the gate electrode 16 and the gate insulating film 15. When the gate insulating film 15 is thin, the film thickness of the gate insulating film 15 which is part of the pixel auxiliary capacitor 6 is obtained. Thinning. When the laser is formed into a polycrystalline tantalum film 71, it is feared that a protrusion is formed on the surface of the polysilicon film 71. Therefore, the gate insulating film of the portion of the capacitance portion 22 of the pixel auxiliary capacitor 6! When the film thickness of 5 is thin, it is feared that the capacitor portion 22 formed by the polysilicon film 71 and the capacitor wiring portion 23 formed by the second metal layer 73 are not sufficiently insulated, and leakage between the capacitor portion 22 and the capacitor wiring portion 23 may occur. . As a result, it is feared that the liquid crystal display device 1 generates a dot defect and the yield is lowered. Therefore, in the second embodiment described above, in the case of the liquid crystal display device 1 having a thin film thickness (e.g., 90 nm or less) of the gate insulating film 5, productivity can be particularly improved. Further, in each of the above embodiments, the capacitance between the capacitance portion 22 of the pixel storage capacitor 6 and the capacitance wiring portion 23 may be the capacitance of the circuit portion for driving the liquid crystal display device 1. 95517. Doc -25 - 1288845 As the first metal layer 72, an alloy containing molybdenum (M〇), that is, any of molybdenum-tungsten (MoW) and molybdenum-niobium (MoTa) may be used. As the second metal layer 73, an alloy containing aluminum (A1), that is, at least one of Ming (A1) and Shao-Cu (AlCu), and molybdenum (Mo), titanium (τ〇', and nitride may also be used. A laminated film of at least one of titanium (TiN). [Industrial Applicability] According to the present invention, the number of steps can be minimized, and the gate wiring can be thinned and reduced in resistance. Forming a liquid crystal display device having a thin film transistor, which can achieve a high aperture ratio, low power consumption, and a built-in memory circuit and a conventional TAB mounted driving circuit. [Simple diagram] 1 is a cross-sectional view showing a liquid crystal display device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing a state in which a first conductive layer is formed on a light-transmissive substrate of the liquid crystal display device. It is a cross-sectional view showing a state in which the source region and the drain region of the channel-type thin germanium transistor of the liquid crystal display device are partially doped. Fig. 4 shows an n-channel film which will become the same liquid crystal display device. Electricity A cross-sectional view of a portion of the source region and the drain region of the crystal, and a state in which a portion of the capacitance portion of the auxiliary capacitor is doped. FIG. 5 is a view showing a gate electrode including a gate electrode in the same liquid crystal display device. A cross-sectional view showing a state in which a second conductive layer is formed on a film. Fig. 6 is a view showing a pattern of a second conductive layer of the same liquid crystal display device 95517. Doc -26- 1288845 Description section of the state. Fig. 7 is a cross-sectional view showing a state in which an interlayer insulating film is formed on a gate insulating film including a wiring portion and a capacitor wiring portion of the liquid crystal display device. Fig. 8 is an explanatory cross-sectional view showing a state in which a contact hole is formed in the interlayer insulating film of the liquid crystal display device. Fig. 9 is an explanatory cross-sectional view showing a state in which a conductive layer formed on an interlayer insulating film including a contact hole of the liquid crystal display device is patterned. Fig. 10 is a cross-sectional view showing a state in which a protective film is formed on the interlayer insulating film including the source electrode, the drain electrode, and the extraction electrode of the liquid crystal display device. Figure 11 is a cross-sectional view showing the liquid crystal display of the second embodiment of the present invention. Fig. 12 is an explanatory cross-sectional view showing a state in which a first interlayer insulating film is formed on a gate insulating film including a gate electrode of the liquid crystal display device. Fig. 13 is an explanatory sectional view showing a state in which a contact hole is formed in the first interlayer insulating film of the liquid crystal display device. Fig. 14 is an explanatory cross-sectional view showing a state in which a second metal layer is formed on the first interlayer insulating film including the contact hole of the liquid crystal display device. Fig. 15 is a cross-sectional view showing the state in which the second metal layer of the liquid crystal display device is patterned. Fig. 16 is a cross-sectional view showing a state in which a second interlayer insulating film is formed on a gate insulating film including a wiring portion and a capacitor wiring portion of the liquid crystal display device. 95517. Doc -27- 1288845 Fig. 17 is a cross-sectional view showing a state in which a contact hole is formed in the second interlayer insulating film of the liquid crystal display device. Fig. 18 is a cross-sectional view showing a state in which a conductive layer formed on a second interlayer insulating film including a contact hole of the liquid crystal display device is patterned. Fig. 19 is a cross-sectional view showing a state in which a protective film is formed on the second interlayer insulating film including the source electrode, the drain electrode, and the extraction electrode of the liquid crystal display device. [Main component symbol description] 1 Liquid crystal display device 2 Array substrate 3, 62 Glass substrate 4 n-channel type thin film transistor 5 Ρ channel type thin film transistor 6 pixel auxiliary capacitor 11 polycrystalline second layer 12 channel region 13 / primary region 14 Gate region 15 gate insulating film 16 gate electrode 17 wiring portion 22 capacitor portion 23 capacitor wiring portion 95517doc -28- 1288845 31 interlayer insulating film 32-36, 52, 82, 83 contact hole 41, 43 source electrode 42, 44 Bipolar electrode 45 Extraction electrode 51 Protective film 53 Pixel electrode 54, 64 Orientation film 61 Counter substrate 63 Counter electrode 65 Liquid crystal 71 Polysilicon film 72 First metal layer 73 Second metal layer 74 Conductive layer 81 First interlayer insulation Film 84 second interlayer insulating film
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