TWI288454B - Wafer carrier having improved processing characteristics - Google Patents
Wafer carrier having improved processing characteristics Download PDFInfo
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- TWI288454B TWI288454B TW093106956A TW93106956A TWI288454B TW I288454 B TWI288454 B TW I288454B TW 093106956 A TW093106956 A TW 093106956A TW 93106956 A TW93106956 A TW 93106956A TW I288454 B TWI288454 B TW I288454B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67326—Horizontal carrier comprising wall type elements whereby the substrates are vertically supported, e.g. comprising sidewalls
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Abstract
Description
1288454 玖、發明說明： 【發明所屬之技術領域】 本發明一般係關於窯設備，而更明確古 、， σ〈係關於一種用 於支撐晶圓以經歷諸如曝露於一高溫處理 ， 、 ，味^^之類處理 晶圓載體。此外’本發明一般係關於使 、 處理晶圓。 頰曰曰圓載體來 【先前技術】 在此項技術中瞭解，半導體程序在包括高溫料（包括下 火、化學汽相沈積、氧化及其他）的各種處理步驟中一般= 用工件以支擇及/或傳輸半導體晶圓。在此方面，使用^平 及垂直晶圓載體（在此項技術中亦稱為晶圓舟）來支標複數 個晶圓，該等複數個晶圓一般以一怔定間距相互相隔而形 成-晶圓陣列。在此方面，該晶圓曝露於處理操作一般稱 為「分批處理」，其中同時處理複數個晶圓。 隨著電晶體關鍵尺寸、晶粒尺寸及積體電路尺寸之減 小，所處理晶圓之實際直徑不斷增加。例如，該產業已從4 英吋晶圓轉移至6英吋晶圓，而現在一般使用8英吋晶圓。 進一步，12英时（300醒）的半導體製造工廠⑽士如⑽ plant，fab)也出現於線上。隨著增加的晶圓尺寸之引入， 在該製造程序的許多階段都產生新的工程問題。 進一步，主要由矽組成之半導體晶圓正在用於形成包括 邏輯與記憶體裝置之傳統積體電路結構，而且用於形成光 電衣置例如波導夕工态及微機電系統加_mechanical1288454 玖, the invention description: [Technical field of the invention] The present invention relates generally to kiln equipment, and more specifically, σ< is related to one for supporting a wafer to undergo exposure such as exposure to a high temperature treatment, Processing wafer carriers such as ^. Further, the present invention generally relates to the fabrication and processing of wafers. Buccal round carrier [Prior Art] It is understood in the art that semiconductor programs are generally used in various processing steps including high temperature materials (including under-fire, chemical vapor deposition, oxidation, and others). / or transfer semiconductor wafers. In this regard, a plurality of wafers are calibrated using a flat and vertical wafer carrier (also referred to in the art as a wafer boat), the plurality of wafers being generally separated by a predetermined spacing - Wafer array. In this regard, the wafer exposure process is generally referred to as "batch processing" in which a plurality of wafers are processed simultaneously. As the critical dimensions of the transistor, the grain size, and the size of the integrated circuit decrease, the actual diameter of the processed wafer continues to increase. For example, the industry has moved from 4-inch wafers to 6-inch wafers, and now typically uses 8-inch wafers. Further, a 12-hour (300-wake) semiconductor manufacturing plant (10), such as (10) plant, fab) also appeared on the line. With the introduction of increased wafer size, new engineering issues arise at many stages of the manufacturing process. Further, a semiconductor wafer mainly composed of germanium is being used to form a conventional integrated circuit structure including a logic and a memory device, and is used for forming a photovoltaic device such as a waveguide and a microelectromechanical system plus _mechanical
SyStem;MEMS)。在此方面，裝置製造有時使用一延長的氧化SyStem; MEMS). In this regard, device fabrication sometimes uses an extended oxidation
O:\91\91516.DOC -6 - 1288454 步驟，在此步驟中氧化該等半導體晶圓，有時延長之時間 週期超出在傳統半導體處理中—般遇到的時間週期。例 如，常常一次將一晶圓曝露於一處理操作數日，例如以五 至十日為等級。如上面所提及，此類處理操作時常包括該 等晶圓之氧化。 x 鑒於所延長的處理時間以及所增加的晶圓尺寸，已產生 影響該等裝置之強固性及品質之技術問題。在此方面，本 發明者在經受此類處理操作後已遇到該等晶圓中之缺陷， 例如該等晶圓之局部或甚至災難性的破碎。其他缺陷包括 圍繞外部周邊的晶圓變形及缺口，特別是在接觸該晶圓载 體之點上’例如’在-水平晶圓舟之情況下的該晶圓载體 之底部支撐部分。 因此，在此項技術中需要改善晶圓載體或舟（特定言之係 水平晶圓载體）並需要提供改善裝置良率及低缺陷率之改 善的處理操作。 依據本發明之-方面提供—種晶圓載體⑽支撐複數個 晶圓，該載體包括提供於一托架内的複數個槽，該托架包 含碳化矽並具有覆蓋該碳化矽之一氧化層。 4據本u之另—方面提供—種具有複數個槽之晶圓載 體，該等複數個槽具有一特定寬度。特定言之，每一槽之 -部分具有一寬度(Ws)，其中Ws不小於130以為該等晶 圓之一厚度。 依據本I明之另-特徵，提供—種用於支撐複數個晶圓O:\91\91516.DOC -6 - 1288454 The steps in which the semiconductor wafers are oxidized, sometimes for extended periods of time beyond the time periods typically encountered in conventional semiconductor processing. For example, a wafer is often exposed to a processing operation number at a time, for example, on a scale of five to ten days. As mentioned above, such processing operations often include oxidation of such wafers. x Due to the extended processing time and increased wafer size, technical issues affecting the robustness and quality of these devices have arisen. In this regard, the inventors have encountered defects in such wafers after undergoing such processing operations, such as partial or even catastrophic fracture of such wafers. Other deficiencies include wafer deformation and nicks around the outer perimeter, particularly at the point of contact with the wafer carrier, e.g., in the case of a horizontal wafer boat, the bottom support portion of the wafer carrier. Therefore, there is a need in the art to improve wafer carriers or boats (specifically horizontal wafer carriers) and to provide improved processing operations that improve device yield and low defect rates. According to an aspect of the invention, a wafer carrier (10) supports a plurality of wafers, the carrier comprising a plurality of grooves provided in a carrier, the carrier comprising tantalum carbide and having an oxide layer covering the tantalum carbide. 4 According to another aspect of the invention, there is provided a wafer carrier having a plurality of slots, the plurality of slots having a specific width. Specifically, the - portion of each slot has a width (Ws), wherein Ws is not less than 130 to be one of the thicknesses of the crystals. According to another feature of the present invention, a plurality of wafers are provided for supporting
O:\91\91516.DOC 1288454 之晶圓载體，It等晶圓具有一半徑〜，且該晶圓載體包括 用於支撐該等晶圓之複數個槽，#中每一槽之至少一部分 具有一曲率半#rs，此半徑不小於約1.15 rw。依據本發明之 此方面之一變化，rs可具有一負值而〜具有一正值。 、依據本發明之另-方面’提供用於處理複數個晶圓之方 法其中將複數個晶圓載至具有上述任一項或所有特徵之 曰曰圓載體上，並使該等晶圓在載於該晶圓載體上時經受 一，理操作。該處理操作可為其中將該等晶圓曝露於一氧 化環境以氧化該等晶圓之一操作。 【實施方式】 項具體實施例，提供一特定的晶圓載體 依據本發明之一 以用於支撐複數個晶圓。在此方面，應注意圖i，該圖式說 明依據本發明之_項具體實施例的—晶圓載體之一透視 圖如圖所不，晶圓載體1包括一托架2，該托架2具有一般 為開放之結構並包括呈現一般為弓形之一形狀的複數個 托架臂3,且該等托架臂與複數個支撐部件整合以支撐該等 曰曰圓特定5之，提供第一、第二及第三支撐部件1〇、12 及14,每:部件經向内向突出，並且沿該等部件提供複數 個槽16。每一槽16之置放及定向使其沿固定半徑之相同弧 而定位以支撐一單一的個別晶圓。每一槽分別由第一、第 及第一礼區奴18、2〇及22組成，每一槽分別沿第一、第 二及第三支撐部件1〇、12及14定位。 如圖2所不，提供一斷面圖，其說明嚙合並载至該晶圓載 體1上面的晶圓3〇之定向。圖丨及2所說明的該晶圓載體之一O:\91\91516.DOC 1288454 wafer carrier, It and other wafers have a radius ~, and the wafer carrier includes a plurality of slots for supporting the wafers, at least a portion of each slot in # Has a curvature half #rs, this radius is not less than about 1.15 rw. According to one aspect of this aspect of the invention, rs can have a negative value and ~ have a positive value. According to another aspect of the present invention, there is provided a method for processing a plurality of wafers, wherein a plurality of wafers are carried on a circular carrier having any one or all of the above features, and the wafers are carried on The wafer carrier is subjected to a reasonable operation. The processing operation can be one in which the wafers are exposed to an oxidizing environment to oxidize one of the wafers. [Embodiment] In a specific embodiment, a specific wafer carrier is provided in accordance with one of the present invention for supporting a plurality of wafers. In this regard, attention should be paid to FIG. 1, which illustrates a perspective view of a wafer carrier in accordance with an embodiment of the present invention, the wafer carrier 1 including a carrier 2, the carrier 2 Having a generally open structure and including a plurality of bracket arms 3 that assume one of a generally arcuate shape, and the bracket arms are integrated with a plurality of support members to support the domes 5, providing a first The second and third support members 1 , 12 and 14 each protrude inwardly from the member and provide a plurality of slots 16 along the members. Each slot 16 is placed and oriented such that it is positioned along the same arc of a fixed radius to support a single individual wafer. Each slot is composed of first, first and first court slaves 18, 2 and 22, each slot being positioned along the first, second and third support members 1 , 12 and 14 respectively. As shown in Fig. 2, a cross-sectional view is provided illustrating the orientation of the wafers 3* that are engaged and loaded onto the wafer carrier 1. One of the wafer carriers illustrated in Figures 2 and 2
〇：\91\915l6.D〇C 1288454 中的晶圓载體之定向（特定言之係 如所說明，該載體支撐一般為一 般朝向為水平，並係使用 在一半導體工廠環境中）。 直立、垂直位置之晶圓。 如圖1很清楚顯示，該等样 寻僧16係配置為一線性陣列並以一 恆疋間距相互間隔。例如 ？ _ .、、、頁不弟一槽區段2〇以一恆定間 距相互間隔並為一陣列才夂彳。 口式如此，該載體線性固定該等 晶圓，形成一水平晶圓堆疊。聱 且 4寺凹槽之間距及相應地， 該等晶圓之間距，可佑赭姓a處m 康特疋應用而變動，但一般在約2 至約4 mm之一範圍内，標稱約為2.38 。 如圖2所不，該等第一、第二及第三支揮部件⑺、η及" 沿-弧32定位，該弧32具有一半徑等於該晶圓…半 徑’從而使得該等第一、第—乃筮— 弟一及弟二支撐部件依順序沿該 弧32定位而該第二支樓部件在該等第—與第三支撐部件 10 14之間/σ圓周定位。在此方面，因為該第二支樓部件 係置放於一最底部位置，即在該六點鐘位置，因此該第二 支撐部件-般支撐該晶圓重量之一較大部分。該弧32掠過 不大於180度之一角度，以便辅助該等晶圓之載入。一般 地，定位該等支撐部份以定義不大於約15()度或—般不大於 約130度之一弧32。 儘官圖1及2顯示三個支撐部件，但該晶圓載體可具有一 不同數目之支撐部件。例如，可將該第二切部件雙叉以 便形成具有不同槽區段之二不同支撐部件。在此情況下， 該等支撐部件可與該最底部六點鐘位置相等間隔。 如上面所提及，該晶圓載體具有一般為開放之一設計，〇: Orientation of the wafer carrier in \91\915l6.D〇C 1288454 (specifically, as illustrated, the carrier support is generally oriented horizontally and used in a semiconductor factory environment). Upright, vertical position wafers. As is clear from Figure 1, the finder 16 series are arranged in a linear array and spaced apart from one another by a constant spacing. E.g ? _,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, As such, the carrier linearly holds the wafers to form a horizontal wafer stack.聱 and the distance between the grooves of the 4 temples and correspondingly, the distance between the wafers can be varied, but generally within a range of about 2 to about 4 mm, nominally Is 2.38. As shown in FIG. 2, the first, second, and third support members (7), η, and " are positioned along an arc 32 having a radius equal to the radius of the wafer... such that the first The first and second support members are positioned along the arc 32 in sequence and the second branch member is positioned between the first and third support members 10 14 / σ circumference. In this regard, because the second abutment component is placed in a bottommost position, i.e., at the six o'clock position, the second support member generally supports a larger portion of the wafer weight. The arc 32 sweeps over an angle of no more than 180 degrees to aid in loading of the wafers. Typically, the support portions are positioned to define an arc 32 that is no greater than about 15 (degrees) or generally no greater than about 130 degrees. Figures 1 and 2 show three support members, but the wafer carrier can have a different number of support members. For example, the second cutting member can be bifurcated to form two different support members having different groove segments. In this case, the support members can be equally spaced from the bottommost six o'clock position. As mentioned above, the wafer carrier has a generally open design.
〇：\91\915l6.DOC -9- 1288454 該開放設計提供下面詳細說明之數項優點。—般地，定義 於該等托架臂3與該等支撐部件之間的窗口沿該托架之— 外部部分圓柱表面提供至少4G%的開放區域。—般地，該 開放區域科於⑽％。該晶圓載體之此開放設計有利地 改善该預乳化步驟期間圍繞該晶圓載體之氣體流動，以形 成一等角的、相對較均勻的氧化層。 現在來說該晶圓之材料，如上面所提及，該托架係由碳 化石夕組成。依據一項具體實施例，該碳化矽包含再結晶的 石反化矽，其係在此項技術中所瞭解之一材料。一般地，將 包含半導體級碳化矽粉之一綠色主體與燒結助劑及黏結劑 ^模‘成所需的經成形、乾燥、加熱至燃盡之一有機 黏〜劑並經熱處理以密化並再結晶該綠色主體。可使用接 下來的密化、加工步驟以達到該晶圓載體之最終尺寸。 可使用其他形式的碳化矽以替代再結晶的碳化矽或與再 結晶的碳化矽組合。例如，該碳化矽基板可藉由一轉化程 序而形成’其中藉由氣相或液相技術將一碳預成形物轉化 成石厌化矽。一般地，在此情況下，該預成形物係由一含碳 材料形成’例如半導體級石墨。進一步，在將一多孔碳化 石夕用於該晶圓載體之基底材料之情況下，該載體可充滿 石夕。此類組合特徵稱為Si_sic或矽化碳化矽。在此方面，在 形成一相對較為多孔之碳化矽基板後，接著該基板便充滿 少谷化石夕’以將該結構密化至適合用於耐火應用（例如，在半 導體處理環境中）之一程度。該矽化碳化矽可塗佈有一進一 Y的石反化石夕層，例如化學汽相沈積（chemical vapor〇:\91\915l6.DOC -9- 1288454 This open design provides several advantages as detailed below. Generally, the window defined between the bracket arms 3 and the support members provides at least 4 G% of the open area along the cylindrical surface of the bracket. In general, the open area is at (10)%. This open design of the wafer carrier advantageously improves the gas flow around the wafer carrier during the pre-emulsification step to form an equiangular, relatively uniform oxide layer. The material of the wafer is now referred to, as mentioned above, the carrier is composed of carbon carbide eve. According to a specific embodiment, the niobium carbide comprises a recrystallized stone recrystallized crucible which is one of the materials known in the art. Generally, a green body comprising a semiconductor-grade niobium carbide powder and a sintering aid and a binder are formed into a desired organic solvent, which is shaped, dried, heated to burn-off, and heat-treated to be densified and The green body is recrystallized. The subsequent densification, processing steps can be used to achieve the final dimensions of the wafer carrier. Other forms of niobium carbide may be used in place of the recrystallized tantalum carbide or in combination with the recrystallized tantalum carbide. For example, the tantalum carbide substrate can be formed by a conversion process in which a carbon preform is converted into a stone anisotropy by a gas phase or liquid phase technique. Generally, in this case, the preform is formed of a carbonaceous material, such as semiconductor grade graphite. Further, in the case where a porous carbonized stone is used for the base material of the wafer carrier, the carrier can be filled with a stone. Such combined features are referred to as Si_sic or deuterated tantalum carbide. In this aspect, after forming a relatively porous tantalum carbide substrate, the substrate is then filled with a small valley of fossils to densify the structure to a level suitable for use in refractory applications (eg, in a semiconductor processing environment). . The deuterated tantalum carbide can be coated with a Y-stone anti-fossil layer, such as chemical vapor deposition (chemical vapor deposition)
O:\91\91516.DOC 1288454 deposited ; CVD)碳化矽。 進一步’該晶圓載體可由獨立式SiC形成，該獨立式ye 係藉由CVD而形成。在此情況下，實施一延長的cvD程序 以自己形成該晶圓載體。 k供一氧化層以便覆盍該晶圓載體之碳化秒。該氧化層 可藉由在一氧化環境中該載體之氧化而形成，例如，藉由 在一含氧環境中在一升高溫度下氧化該載體，該升高溫度 為，例如，在950至約1300攝氏度之一範圍内，而更為一般 則在約1000至約1250攝氏度之一範圍内。可在一乾燥或潮 濕大氣中實施氧化，並一般實施於大氣壓力下。一潮濕環 境可藉由引入蒸汽而產生，並用來提高氧化率且改善該氧 化1之密度。在此方面，U5(rc之濕氧化可採取約Η至判 小時之等級形成一強固而厚（例如約2至3微米）的氧化層。另 -方面：此類層可採取5日之等級，例如1〇至2〇日，用於依 據-乾燥氧化處理而形成氧化層。儘管該氧化層一般係藉 由氧化而形成，但亦可沈積該氧化層（例如，藉由te〇㈣ 2體反應）。但是’為具有耐用性及強固性，較佳則係 長層。 …、 =地’該氧化層為碳切，—般為叫該氧化石夕層 可一亥晶圓载體之碳化石夕直接接 石夕)可存在於該碳化石夕與該覆罢… +間層(例如 邊覆盍虱化層之間，如 的碳化石夕之情況下_樣。 Π在充滿石夕 圖3說明在該碳化石夕晶圓載體上一氧化 與成長時間成函數關係。如長曲線，其 斤呪明，该軋化層按照一般為O:\91\91516.DOC 1288454 deposited; CVD) bismuth carbide. Further, the wafer carrier can be formed of freestanding SiC which is formed by CVD. In this case, an extended cvD program is implemented to form the wafer carrier by itself. k is provided with an oxide layer to cover the carbonization seconds of the wafer carrier. The oxide layer can be formed by oxidation of the support in an oxidizing environment, for example, by oxidizing the support at an elevated temperature in an oxygen-containing environment, for example, at 950 to about It is in the range of 1300 degrees Celsius, and more generally in the range of about 1000 to about 1250 degrees Celsius. Oxidation can be carried out in a dry or humid atmosphere and is generally carried out under atmospheric pressure. A humid environment can be created by introducing steam and used to increase the oxidation rate and improve the density of the oxidation 1. In this regard, U5 (the wet oxidation of rc can form a strong and thick (e.g., about 2 to 3 microns) oxide layer from about Η to the hour. Another aspect: such a layer can take a 5 day rating. For example, from 1 to 2 days, for forming an oxide layer according to the dry oxidation treatment. Although the oxide layer is generally formed by oxidation, the oxide layer may also be deposited (for example, by te 〇 (4) 2 body reaction However, 'for durability and strength, it is better to be long layer. ..., = ground' The oxide layer is carbon cut, which is called the carbon oxide fossil of the oxidized stone layer.接石石) can exist in the carbonized stone eve with the cover ... + interlayer (such as between the edge of the sputum layer, such as the case of carbonized stone eve - Π in the full of the stone eve Figure 3 illustrates The oxidation on the carbonized stone wafer carrier is a function of growth time. If the curve is long, it is clear, and the rolled layer is generally
O:\91\915I6.DOC 1288454 抛物線之一生長ώp , 负曲線來生長。由於下面所論述之原因，依 據本發明之一項呈辦音:^ A-r ^ 貝一體貫施例，该氧化層具有超過該曲線之 相對較快生長部分之一戶存 刀之厚度。例如，該氧化層可具有大於 約0.5微米之一真声，七序七+ 、 与度，或特定言之大於約〇·75微米，例如大 於、勺1.0U# ’以及甚至15微米。依據本發明之特定且體實 2例1氧化物具有至少2微米之—厚度，例如為約技約3 U米之等級。應注意，依據本發明之具體實施例之氧化層O:\91\915I6.DOC 1288454 One of the parabola grows ώp, a negative curve to grow. For the reasons discussed below, in accordance with one embodiment of the present invention, the oxide layer has a thickness that exceeds the thickness of one of the relatively faster growing portions of the curve. For example, the oxide layer can have a true sound greater than about 0.5 microns, a seven order seven +, a degree, or specifically greater than about 〇 75 microns, such as greater than, a spoon of 1.0 U # ' and even 15 microns. Particular and solid 2 oxides according to the invention have a thickness of at least 2 microns, for example of the order of about 3 U meters. It should be noted that the oxide layer in accordance with a specific embodiment of the present invention
係提供於該日日日«體上之_層，與可存在於該日日日圓載體I =任何原生氧化物相對’但其厚度相對較低。進一步，儘 官上述氧化層一般係藉由熱氧化技術而形成’但亦可使用 其他技術，例如直接沈積一氧化層。 已發現一乳化層 < 形成（例如藉由一熱預氧化步驟）改善 :半導體工廠環境中的程序控制。特定言之，本發明者已 發現，在該等晶圓上形成一相對較厚的氧化層之傳統氧化 處理期間’該等晶圓往往經由該氧化層在該等晶圓上的生 長及/或形成於該晶圓載體上之一氧化層而與該晶圓載體 黏接。咸信在隨後該晶圓/晶圓載體裝配件之冷卻期間，嗲 晶圓與該載體之收縮差異與熱膨脹係數之差異會引起該等 ^圓中的熱致應力。此類熱膨脹/收縮特性之差異可由純 口及結構圣異所致，且最終能造成對該等晶圓之損害。在 t端情況下，該等晶圓可藉由一裂化機制而發生災難性故 P羊。藉由併入一預氧化步驟以在該載體上形成一氧化層， 而削弱在該等晶圓之熱處理期間在該載體上一氧化層2 長，亚且減少該等晶圓與該載體之間的黏接傾向，從而辦It is provided on the day of the day «the body layer _, which may be present on the day of the day carrier I = any native oxide' but its thickness is relatively low. Further, it is desirable that the above oxide layer is formed by thermal oxidation techniques, but other techniques such as direct deposition of an oxide layer may also be used. It has been found that an emulsified layer < formation (e.g., by a thermal pre-oxidation step) is improved: program control in a semiconductor factory environment. In particular, the inventors have discovered that during conventional oxidation processing to form a relatively thick oxide layer on such wafers, the wafers tend to grow on the wafers via the oxide layer and/or An oxide layer formed on the wafer carrier is bonded to the wafer carrier. During the subsequent cooling of the wafer/wafer carrier assembly, the difference in shrinkage between the wafer and the carrier and the coefficient of thermal expansion may cause thermal stress in the circle. The difference in such thermal expansion/contraction characteristics can be caused by pure port and structural singularity and can ultimately cause damage to such wafers. In the case of the t-end, the wafers can be catastrophic by a cracking mechanism. Incorporating a pre-oxidation step to form an oxide layer on the carrier, thereby weakening the length of the oxide layer 2 on the carrier during the heat treatment of the wafers, and reducing the distance between the wafers and the carrier Adhesion tendency
O:\91\91516.D0C -12- 1288454 強程序控制及晶圓良率。 依據本么明之另一 4寸徵’該晶圓載體中的槽具有一特定 的曲率半;^ rs ’此半徑進_步增強程序控制及晶圓良率，特 定言之係在上述高溫處理期間。 如結合圖2所示，該晶圓具有一標稱半徑〜。當前最新技 術的晶圓工廠使用8英时，並且越來越多地使用12英忖（3〇〇 醜直徑）晶圓。因此，儘管較老的工廠可使用較小晶圓而 較新一代工廠則使用較大晶圓，但新工廠可使用一晶圓， 其具有等級約為15() mm之—半徑依據—項具體實施例 之一特定特徵，該槽之曲率半徑g小於約115 ^。或者 祝，用於支撐該晶圓的槽曲率半徑比該等晶圓之半徑大至 少15%。-般地，g小於約! .25 rw，例如】_35〜與ι 5〜 現在來看圖4，顯示rs約為〜之二倍。甚至進—步，該槽曲 率半徑可接近一直線（rs=無窮大）。圖5中說明此特定具體實 施例。在此情況下，槽之接觸該晶圓之一部分沿一直線延 伸0 進一步，該槽曲率之半徑可具有相反定向，即，與該晶 圓之半ferw相比較具有一負的曲率半徑。此顯示於圖6中， 其中該槽具有一般為凸起之一形狀並具有一半徑，此半徑 自該晶圓與該槽之間的接觸點起以與該晶圓半徑相反之一 方向延伸。 在該等前述具體實施例中，並不要求每—槽區段具有相 同的曲率半徑。但是，一般沿該第二支撐部件之第二槽區 段之至少一部分具有上述之一半徑特色。O:\91\91516.D0C -12- 1288454 Strong program control and wafer yield. According to another 4 inch sign of the present invention, the groove in the wafer carrier has a specific curvature half; ^ rs 'this radius _ step enhances program control and wafer yield, in particular during the above high temperature processing . As shown in connection with Figure 2, the wafer has a nominal radius ~. Current state-of-the-art wafer fabs use 8 inches and are increasingly using 12-inch (3 丑 ugly diameter) wafers. Therefore, although older plants can use smaller wafers and larger wafers use larger wafers, the new plant can use a wafer with a rating of about 15 () mm - radius basis - specific In a particular feature of one embodiment, the groove has a radius of curvature g of less than about 115^. Or, the radius of curvature of the grooves used to support the wafer is at least 15% greater than the radius of the wafers. In general, g is less than about! .25 rw, for example, _35~ and ι 5~ Now look at Figure 4, which shows that rs is about twice as much as ~. Even if the step is advanced, the groove radius can be close to the straight line (rs = infinity). This particular embodiment is illustrated in FIG. In this case, a portion of the groove contacting the wafer extends along a straight line. Further, the radius of curvature of the groove may have an opposite orientation, i.e., have a negative radius of curvature as compared to a half of the wafer. This is shown in Figure 6, wherein the groove has a generally convex shape and has a radius extending from a point of contact between the wafer and the groove to extend in a direction opposite the radius of the wafer. In the foregoing specific embodiments, the per-groove sections are not required to have the same radius of curvature. However, generally at least a portion of the second trough section along the second support member has one of the above-described radius features.
O:\91\91516.DOC -13 · 1288454 藉由提供具有上述之一曲率半徑rs之一槽部分，來最小化 该晶圓與該載體之間的潛在氧化黏接區域。如此，若在該 曰曰圓與該載體之間形成一氧化物黏接，則最小化的黏接介 面更弱且更可能在處理期間（例如，在冷卻期間）破裂，從而 削弱該晶圓中造成上述破碎的熱應力。 依據本發明之另一項具體實施例，該晶圓載體的槽之至 少一部分具有一寬度Ws大於該等晶圓之一厚度u。特定言 之，該寬度一般不小於約13〇、。依據另一項具體實施例， ws不小於1.35 tw並可在約U5 w至約15〇 w之一範圍内。在 此方面，圖7說明與該晶圓厚度w相對的該槽寬度w〆未按比 例顯示）。應注意，該等晶圓之實際厚度“可依據晶圓品牌、 所希主用途、晶圓直徑、組成（例如，絕緣體上矽（siHc〇n 〇n i_lator; S0I))等而變動。但是，晶圓—般具有在約〇·45 _ 至約0.80 mm之一範圍内之一厚度，更為一般地係在約〇.% 至約0.765 mm之間。藉由將以上相對寬度提供給該等槽， /、/、諸如1·1〇、至1·25 tw等級之較窄寬度相對，相對較厚 乳化層之形成得到該等槽中的額外空㈣助。此外，藉由 肖J弱在氧化物生長期間晶圓在該等槽内受約束之程度，晶 圓潛變變得不太& ^ 口 欠伃个太烕問碭。在此方面，使用傳統技術，該晶 Q在攻槽内所叉之約束往往使得該晶圓在高溫下潛變而造 成、在、、％ β亥外部周邊之該晶圓内缺口之形成往往形成 、不利的機械聯鎖結構。特定言之，由於該晶圓與該晶圓 載體之不同熱收縮特色而導致一經冷卻該缺口便往往口齒合 "亥槽且造成在該晶圓内施以機械應力。O:\91\91516.DOC -13 · 1288454 minimizes the potential oxidative bond area between the wafer and the carrier by providing a groove portion having one of the above radii of curvature rs. Thus, if an oxide bond is formed between the dome and the carrier, the minimized bonding interface is weaker and more likely to break during processing (eg, during cooling), thereby weakening the wafer. Causes the above-mentioned thermal stress of the fracture. In accordance with another embodiment of the present invention, at least a portion of the trench of the wafer carrier has a width Ws greater than a thickness u of the wafers. In particular, the width is generally not less than about 13 Å. According to another specific embodiment, ws is not less than 1.35 tw and may range from about U5 w to about 15 〇 w. In this regard, Figure 7 illustrates that the groove width w? as opposed to the wafer thickness w is not shown as a ratio). It should be noted that the actual thickness of the wafers may vary depending on the brand of the wafer, the intended use, the diameter of the wafer, the composition (eg, the insulator (siHc〇n 〇n i_lator; S0I)), etc. However, The wafer typically has a thickness in the range of from about 〇45 _ to about 0.80 mm, more typically between about 〇.% and about 0.765 mm. By providing the above relative width to the wafer The groove, /, /, such as 1·1 〇, to a narrow width of the level of 1 · 25 tw, the formation of a relatively thick emulsion layer to obtain additional space (four) in the grooves. In addition, by Xiao J weak in To the extent that the wafer is constrained within the slots during oxide growth, the wafer creep becomes less & 口 伃 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀 砀The constraint of the inner fork often causes the wafer to creep under high temperature, and the formation of the notch in the wafer at the outer periphery of the % 亥 往往 often forms an unfavorable mechanical interlocking structure. Specifically, due to the Different heat shrink characteristics of the wafer and the wafer carrier cause the gap to be often dried after cooling &Quot; Hai groove and causes mechanical stresses applied in the wafer.
O:\91\91516.DOC -14- 1288454 除上述該晶圓載體之具體實施例之特定特徵之外，本發 明亦提供對複數個晶圓之處理，稱為分批處理。在此方面， 一晶圓載體載有複數個晶圓，該等晶圓一般以一恆定間距 配置為一線性陣列。然後，將該晶圓/晶圓載體裝配件放置 於一爐（例如一處理管）中以作高溫處理。如上所述，一理想 的處理刼作係在該等晶圓上形成一相對較厚氧化層，其特 別適合於MEMS及光電應用。 L s上面已對本發明之具體實施例作特定說明，但應瞭 解可進仃各種修改而不致脫離本申請專利範圍之範疇。 【圖式簡單說明】 藉由茶考隨附圖式可更好地瞭解本發明，且熟習此項技 術者會更明白其許多目的、特徵及優點。 圖1為依據本發明一項具體實施例之一水平晶圓載體之 一透視圖。 圖2為依據本發明^^ Q ΜΑ命,t t ^ 項具體貫施例之一載有矽晶圓的水 平晶圓載體之一斷面圖。 圖3為5兄明在-碳化石々曰m l γ , 反化石夕日日0載體上之氧化物生長曲線之 一曲線圖。 圖4 ,、、、頁7Γ依據本發明_項具體實施例載有—半導體晶圓 之一槽的曲率半徑。 圖5顯示依據本發明s s ^ 知月另一項具體貫施例載有一半導體晶 圓之一槽的曲率半徑。 圖6綠員τγ^依據日日〇 __ ^月另一項具體貫施例載有一半導體晶 圓之一槽的曲率半徑。O:\91\91516.DOC -14- 1288454 In addition to the specific features of the specific embodiment of the wafer carrier described above, the present invention also provides for the processing of a plurality of wafers, referred to as batch processing. In this aspect, a wafer carrier carries a plurality of wafers, which are typically arranged in a linear array at a constant pitch. The wafer/wafer carrier assembly is then placed in a furnace (e.g., a processing tube) for high temperature processing. As noted above, an ideal processing technique forms a relatively thick oxide layer on the wafers, which is particularly suitable for MEMS and optoelectronic applications. The specific embodiments of the present invention have been specifically described above, but it should be understood that various modifications may be made without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood from the following description of the invention, and the <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view of a horizontal wafer carrier in accordance with an embodiment of the present invention. 2 is a cross-sectional view of a horizontal wafer carrier carrying a silicon wafer in accordance with one embodiment of the present invention. Fig. 3 is a graph showing the oxide growth curve of the 5 brothers in the carbon carbide fossil m l γ and the anti-fossil day 0 carrier. 4, 7, and 7, according to an embodiment of the present invention, carries a radius of curvature of a slot of a semiconductor wafer. Fig. 5 shows a radius of curvature of a groove of a semiconductor wafer according to another embodiment of the invention. Figure 6 Green τ γ γ ^ According to the day 〇 __ ^ month Another specific example of the embodiment of a semiconductor crystal circle of a radius of curvature.
O:\91\91516.DOC -15- 1288454 圖7顯示依據本發明之一項具體實施例，載於一槽内的晶 圓斷面厚度，其與槽寬度相對。 不同圖式中使用之相同參考符號表示類似或相同項目。 【圖式代表符號說明】 1 晶圓載體 2 托架 3 托架臂 10 第一支撐部件 12 第二支撐部件 14 第三支撐部件 16 槽 18 第一槽區段 20 第二槽區段 22 第三槽區段 30 晶圓 32 弧 O:\91\91516.DOC -16 -O:\91\91516.DOC -15- 1288454 Figure 7 shows the thickness of a circular cross-section carried in a slot, as opposed to the width of the groove, in accordance with an embodiment of the present invention. The same reference symbols are used in the different drawings to indicate similar or identical items. [Description of Symbols] 1 Wafer carrier 2 Bracket 3 Bracket arm 10 First support member 12 Second support member 14 Third support member 16 Slot 18 First groove segment 20 Second groove segment 22 Third Slot section 30 wafer 32 arc O:\91\91516.DOC -16 -
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| TWI771776B (en) * | 2019-12-05 | 2022-07-21 | 日商Ｓｕｍｃｏ股份有限公司 | Pretreatment method of heat treat furnace, heat treat furnace and wafer manufacturing method |
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| KR20060002875A (en) | 2006-01-09 |
| EP1609171A2 (en) | 2005-12-28 |
| CN1765005A (en) | 2006-04-26 |
| HK1089561A1 (en) | 2006-12-01 |
| US20040188319A1 (en) | 2004-09-30 |
| TW200425384A (en) | 2004-11-16 |
| JP2010103554A (en) | 2010-05-06 |
| KR100755196B1 (en) | 2007-09-05 |
| JP2006521689A (en) | 2006-09-21 |
| WO2004095545A3 (en) | 2005-05-12 |
| CN100390927C (en) | 2008-05-28 |
| WO2004095545A8 (en) | 2005-12-08 |
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