06349twf2.doc/006 修正日期92.12.1 玖、發明說明： 發明領域 本發明關於一種資料處理系統之裝置及其方法，尤其 是指一種適用於相乘相加指令之資料處理系統之裝置及其 方法。此資料處理系統可輕易地偵測運算溢位（〇verfl〇w) 之情形，並且能簡化計算之複雜性，以節省計算的時間。 相關習知技術說明 在資料處理的領域中，需要能夠依據儲存於不同資料 暫存器中的運算子來執行特定運算。有一種這樣的運算是 將N位元運算子(Operand)乘上一第二N位元運算子，再加 上N位元之運算’得到一 N位元的結果。另一種相似的運 算是將N位兀運算子乘上一第二n位元運算子，再加上2N 位兀運算子，即得到2N位元的結果。06349twf2.doc / 006 Modified date 92.12.1. Description of the invention: FIELD OF THE INVENTION The present invention relates to a device and method for a data processing system, and more particularly to a device and method for a data processing system suitable for multiply and add instructions. . This data processing system can easily detect the calculation overflow (〇verfl〇w), and can simplify the complexity of the calculation to save the calculation time. Description of Related Conventions In the field of data processing, it is necessary to be able to perform specific operations based on operators stored in different data registers. One such operation is to multiply the N-bit operator (Operand) by a second N-bit operator, and then add the N-bit operation 'to obtain an N-bit result. Another similar operation is to multiply the N-bit operator by a second n-bit operator and add the 2N-bit operator to get the 2N-bit result.
第1圖係表示美國第5,583,8〇4號名爲”DATA PROCESSING USING MULTI-ACCUMULATE INSTRUCTIONS”之專利之資料處理系統用之習知的相乘相 加器裝置的方塊圖。此系統能夠執行第一種NXN+2N—2N 形式的相乘相加指令，以及第二種ΝχΝ+Ν—N形式的相乘 相加指令。 此相乘相加器裝置包括一第一資料暫存器1〇，一第二 資料暫存器20，一 ΝχΝ乘法器3〇，一 2Ν+2Ν加法器4〇 以及一 Ν^Ν加法器50。乘法器30能夠計算ΝχΝ以得到具 有2Ν位兀之結果。2Ν+2Ν加法器4〇能夠計算2ν+2ν以 得到結果2Ν。Ν+Ν加法器5〇能構計算Ν+Ν以得到結果ν。 06349twf2.doc/006 修正日期92.12.1 然而，在執行N*N+N—N種類的運算時，最後結果大 於N位元大小所能表示的狀況是可能的。當這種情況發生 時，很重要的是使用者必須被通知在運算中已產生溢位 (overflow)。第1圖的相乘相加器裝置的缺點在於該裝置無 法顯示溢位狀況。本發明之相乘相加器裝置的發展是爲了 以儘可能有效率的方式提供此重要訊息給使用者。 發明綜合說明 因此，本發明之一目的在於提供一種包括一單一加法 器並能夠偵測溢位狀況及能夠執行相乘相加指令的資料處 理系統。因此，系統的架構更爲簡單，並提供有價値的溢 位訊息。 爲達成依據本發明目的的這些及其它優點，如同此處 所列舉及廣泛的描述，本發明提供一種資料處理裝置，此 裝置包括一特別暫存器組、--般暫存器組、一選擇器、FIG. 1 is a block diagram showing a conventional multiply-adder device used in a patented data processing system named "DATA PROCESSING USING MULTI-ACCUMULATE INSTRUCTIONS" No. 5,583,80. This system can execute the first multiplication and addition instruction in the form of NXN + 2N-2N, and the second multiplication and addition instruction in the form of NX × N + N-N. The multiplying and adding device includes a first data register 10, a second data register 20, an N × N multiplier 3O, a 2N + 2N adder 4O, and an N ^ N adder 50. . The multiplier 30 can calculate NχN to obtain a result having 2N bits. The 2N + 2N adder 40 can calculate 2ν + 2ν to obtain the result 2N. The N + N adder 50 can construct N + N to obtain the result ν. 06349twf2.doc / 006 Revised 92.12.1 However, when performing N * N + N—N types of operations, it is possible that the final result is larger than what can be represented by the size of N bits. When this happens, it is important that the user is notified that an overflow has occurred in the operation. The disadvantage of the multiply-adder device of Fig. 1 is that the device cannot display an overflow condition. The multiply-adder device of the present invention was developed to provide this important information to the user in the most efficient manner possible. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data processing system including a single adder, capable of detecting an overflow condition, and capable of executing a multiply-add instruction. As a result, the system architecture is simpler and provides valuable overflow information. In order to achieve these and other advantages according to the purpose of the present invention, as enumerated and described extensively herein, the present invention provides a data processing device. The device includes a special register group, a general register group, and a selector. ,
一乘法器、以及一加法器。上述之特別暫存器組係具有N 位元資料處理暫存器。上述之一般暫存器組係具有N位元 資料處理暫存器。選擇器稱合至特別暫存器組及一般暫存 益組’用以選擇特別與一^般暫存器中之一，並從所選擇之 暫存器組中輸出具有N位元之一選擇結果，其中選擇結果 及一 N位兀資料形成具有2N位元的一加法信號。乘法器 係用以接收一第一運算子以及一第二運算子，在執行乘法 運算後輸出具有2N位元的一乘法結果信號。加法器係稱 合至乘法器、選擇器以及一般暫存器組，並用以接收乘法 結果信號與加法信號，並據以執行加法運算後輸出具有2N 06349twf2.doc/006 修正日期92.12.1 位元之一加法結果信號。 上述之資料處理裝置，其中N位元資料係由一般暫存 器組所提供。 上述之資料處理裝置，其中選擇器更用以接收一種類 信號，並據以根據此種類信號選擇特殊與一般暫存器組中 之一。 上述之資料處理裝置，其中種類信號是用以指出所處 理的指令係一第一種類指令或一第二種類指令其中之一， 其中該第一類指令係執行NXN+2N—2N蓮算，而該第二種 類指令係執行NxN+N—2N運算。 上述之資料處理裝置，其中更包括一偵測裝置，耦接 至加法器，用以接收具有2N位元之該加法結果信號，並 檢查是否發生溢位狀況。 上述之資料處理裝置，其中從選擇器輸出具有N位元 之選擇結果，以及由一般暫存器組所提供之N位元資料分 別爲加法信號之一第一 N位元部份以及一第二N位元部 份’此加法結果信號包括一第三N位元部份以及一第四N 位元部份，當種類信號所要選擇的是第二種類指令時，偵 測裝置比較具有2N位元之加法信號的第一 N位兀部份以 及加法結果信號之第三N位元部份，並據以決定是否發生 溢位狀況。 上述之資料處理裝置，其中更包括一偵測裝置’稱接 至該加法器，用以接收具有2N位元之該加法結果信號’ 並檢查是否發生溢位狀況。從選擇器輸出具有N位元之選 06349twf2.doc/006 修正日期92.12.1 擇結果，以及N位元資料分別爲該加法信號之一第一 N位 元部份以及一第二N位元部份，加法結果信號包括一第三 N位元部份以及一第四N位元部份，當種類信號所要選擇 的是第二種類指令時，偵測裝置比較具有2N位元之加法 信號的第一 N位元部份以及加法結果信號之第三n位元部 份，並據以決定是否發生溢位狀況。 "" 爲達成本發明這些及其它優點，如同此處所列舉及廣 泛的描述，本發明提供一種資料處理方法，該方法適用於 具有N位元資料處理暫存器之一特殊暫存器組、具有N位 元資料處理暫存器之一般暫存器組、一選擇器、一乘法器 以及一加法器，該資料處理方法包括選擇特殊與一般暫存 器中之一，並從被選擇的暫存器組輸出具有N位元之選手睾 結果’其中輸出的選擇結果及一 N位元資料形成具有2n 位元的一加法信號；提供一第一運算子與一第二運算子， 並據以執行一乘法運算，並輸出具有2N位元結果之〜乘 法結果信號；對具有2N位元之乘法結果信號與具有2N位 元的加法信號執行一加法運算，並輸出具有2N位元結果 之一加法結果信號。 如上所述之資料處理方法，其中N位元資料係由〜般 暫存器組所提供。 如上所述之資料處理方法，其中在選擇特殊與〜般暫 存器中之一，並輸出具有N位元的選擇結果步驟中，更包 括由選擇器接收一種類信號，並據以決定選擇步驟之結 果。 Ρ 06349twf2.doc/006 修正日期92.12.1 如上所述之資料處理方法，其中種類信號是用以指出 所處理的指令係一第一種類指令或一第二種類指令其中之 一，其中該第一類指令係執行ΝχΝ+2Ν—2Ν運算，而該第 二種類指令係執行NxN+N->n運算。 如上所述之資料處理方法，其中更包括根據該加法結 果信號據以判斷是否有溢位之情形發生。其中從選擇器輸 出具有N位兀之运擇結果’以及由一^般暫存器組所提供之 N位元資料分別爲加法信號之一第一 n位元部份以及一第 二N位元部份，加法結果信號包括一第三n位元部份以及 一第四N位元部份，當種類信號所要選擇的是第二種類指 令時，偵測裝置比較具有2N位元之加法信號的第一 n位 兀部份以及加法結果信號之第三N位元部份，並據以決定 是否發生溢位狀況。 如上所述之資料處理方法，其中更包括根據該加法結 果信號據以判斷是否有溢位之情形發生。從選擇器輸出具 有N位元之該選擇結果以及N位元資料分別爲該加法信號 之一第一 N位元部份以及一第二N位元部份，加法結果信 號包括一第三N位元部份以及一第四N位元部份，當種類 信號所要選擇的是第二種類指令時，偵測裝置比較具有2n 位元之加法信號的第一 N位元部份以及加法結果信號之第 三N位元部份，並據以決定是否發生溢位狀況。 應該了解的是前述的一般性描述及以下的詳細描述都 只是實施例，並且意圖提供如發明之申請專利範圍的進_ 步解釋。 06349twf2.doc/006 修正日期92.12·1 圖式簡要說明 所附圖式是用以題供本發明的進一步了解，並構成本 發明說明書之一部份。該等圖式表示本發明之實施例及伴 隨描述用以解釋本發明之原理。於這些圖式中， 第1圖是習知資料處理系統之乘法加法器裝置的方塊 圖；以及 第2圖是本發明資料處理系統之乘法加法器裝置的方 塊圖。 圖號說明 10資料暫存器20資料暫存器3〇乘法器 40加法器 50加法器 1〇〇種類信號110特殊暫存120 —般暫 器組 存器組 130乘法器 150加法器 152加法信號154加法結 果信號 160選擇器 17〇偵測裝置200資料處理 裝置 較佳實施例說明 現在提供本發明較佳實施例詳細的參考標號，如所附 圖式所示。在圖式及說明中相同或相似的部份儘可能給於 相同的參考標號。 參照第2圖，其爲本發明一較佳實施例之具有相乘相 加運算之資料處理裝置200的方塊圖。此資料處理裝置2〇〇 包括一乘法器130、~加法器丨5〇與一選擇器16Q。資料係 06349twf2.doc/006 修正日期92.12.1 由一特殊暫存器組(Special Register Bank)ll〇及一般暫存器 組(General Register Bank)120所提供。此乘法器13〇耦合至 加法器150。特殊暫存器組11〇及一般暫存器組12〇稱合 至選擇器160。選擇器16〇耦合至加法器15〇。一般暫存= 組120也直接稱合至加法器15〇。此資料處理裝置2Q0更 包括一偵測裝置170耦合至加法器150。 此乘法器130可以使二N位元輸入信號相乘並得到一 2N位元結果。例如，ΝχΝ得到2N結果。如第2圖所示， 以E表不之第一 N位元輸入信號，此爲第一運算子 (Operand)’另外以F表示之第二N位元信號(第二運算子）， 兩者結合成爲一 2N位元之信號，並輸入乘法器丨3〇中。 乘法器13Q以一乘法演算後產生具有2N位元之乘法結果 信號。乘法器130產生的乘法結果信號在送到具有2N位 兀加法運具功能之加法器15 0中，並被加上一加法信號 (Addition Signal)152。此加法信號152也是2N位元，包含 —第一 N位元部份及一第二N位元部份。於本發明中只需 要一個加法器來提供更多想要的計算。例如，在習知技術 中，如果想要如ΝχΝ+Ν—N及ΝχΝ+2Ν—2N的計算，如習 知所示，至少需要二個加法器以完成這樣的計算。然而， 如本發明較佳實施例中的第2圖所示的電路，即可以完成 這樣的運算，底下將詳細說明。A multiplier, and an adder. The special register set mentioned above has N-bit data processing registers. The above-mentioned general register group has an N-bit data processing register. The selector is said to be combined into the special register group and the general register benefit group, which is used to select one of the special and general register, and output a selection with N bits from the selected register group. As a result, the selection result and an N-bit data form an addition signal with 2N bits. The multiplier is used to receive a first operator and a second operator, and output a multiplication result signal having 2N bits after performing the multiplication operation. The adder is called a multiplier, a selector, and a general register group, and is used to receive the multiplication result signal and the addition signal, and execute the addition operation to output 2N 06349twf2.doc / 006 Modified date 92.12.1 bits One of the addition result signals. In the above data processing device, the N-bit data is provided by a general register group. In the above data processing device, the selector is further configured to receive a type of signal and select one of the special and general register groups according to the type of signal. In the above data processing device, the type signal is used to indicate that the processed instruction is one of a first type of instruction or a second type of instruction, wherein the first type of instruction executes NXN + 2N-2N lotus calculation, and This second type of instruction performs NxN + N-2N operations. The above data processing device further includes a detection device coupled to the adder to receive the signal of the addition result having 2N bits and check whether an overflow condition occurs. The above data processing device, wherein the selection result having N bits is output from the selector, and the N bit data provided by the general register group is a first N bit portion and a second bit of the addition signal, respectively. N-bit portion 'This addition result signal includes a third N-bit portion and a fourth N-bit portion. When the second type of instruction is to be selected for the type signal, the detection device has 2N bits. The first N-bit portion of the addition signal and the third N-bit portion of the addition result signal are used to determine whether an overflow condition occurs. The above-mentioned data processing device further includes a detection device 'connected to the adder for receiving the addition result signal having 2N bits' and checking whether an overflow condition occurs. Output from the selector with N-bit selection 06349twf2.doc / 006 Modification date 92.12.1, and the N-bit data is a first N-bit portion and a second N-bit portion of the addition signal, respectively The addition result signal includes a third N-bit portion and a fourth N-bit portion. When the second type of instruction is to be selected as the type signal, the detection device compares the first and second N-bit addition signals. An N-bit portion and a third n-bit portion of the addition result signal, and determine whether an overflow condition occurs. " " In order to achieve these and other advantages of the present invention, as enumerated and described extensively herein, the present invention provides a data processing method suitable for a special register group having one N-bit data processing register. A general register group with N-bit data processing registers, a selector, a multiplier, and an adder. The data processing method includes selecting one of special and general registers, and selecting from the selected The register group outputs the test result of the player with N bits, where the output selection result and an N bit data form an addition signal with 2n bits; a first operator and a second operator are provided, and according to To perform a multiplication operation and output a ~ multiplication result signal with a 2N bit result; perform an addition operation on a multiplication result signal with a 2N bit and an addition signal with a 2N bit, and output one of the 2N bit results Add result signal. The data processing method described above, wherein the N-bit data is provided by the ~ general register group. The data processing method as described above, wherein in the step of selecting one of the special and general registers and outputting the selection result with N bits, the method further includes receiving a type of signal by the selector and determining the selection step accordingly. The result. Ρ 06349twf2.doc / 006 Modification date 92.12.1 The data processing method described above, where the type signal is used to indicate that the processed command is one of a first type of command or a second type of command, where the first The type of instruction is to perform N × N + 2N-2N operation, and the second type of instruction is to perform NxN + N-> n operation. The data processing method described above further includes determining whether an overflow occurs based on the signal of the addition result. The output of the selector with N bits is output from the selector, and the N bit data provided by the general register group is a first n bit portion and a second N bit of the addition signal, respectively. Part, the addition result signal includes a third n-bit part and a fourth N-bit part. When the second type of instruction is to be selected as the type signal, the detection device compares the addition signal with the 2N bit. The first n-bit portion and the third N-bit portion of the addition result signal are used to determine whether an overflow condition occurs. The data processing method described above further includes determining whether an overflow occurs based on the signal of the addition result. The selection result and N-bit data having N bits from the selector are respectively a first N-bit portion and a second N-bit portion of the addition signal, and the addition result signal includes a third N-bit Element and a fourth N-bit portion. When the second type of instruction is to be selected for the type signal, the detection device compares the first N-bit portion of the addition signal with 2n bits and the addition result signal. The third N-bit portion is used to determine whether an overflow condition occurs. It should be understood that the foregoing general description and the following detailed description are merely examples, and are intended to provide further explanation of the scope of patent applications such as inventions. 06349twf2.doc / 006 Date of revision 92.12 · 1 Brief description of the drawings The drawings are used for further understanding of the present invention and constitute a part of the description of the present invention. The drawings represent embodiments of the invention and the accompanying descriptions serve to explain the principles of the invention. Of these drawings, FIG. 1 is a block diagram of a multiplier adder device of a conventional data processing system; and FIG. 2 is a block diagram of a multiplier adder device of a data processing system of the present invention. Description of the drawing number 10 data register 20 data register 30 multiplier 40 adder 50 adder 100 type signal 110 special temporary storage 120-general register bank register group 130 multiplier 150 adder 152 addition signal 154 addition result signal 160 selector 170 detection device 200 data processing device preferred embodiment description Now detailed reference numerals of the preferred embodiment of the present invention are provided, as shown in the attached drawings. Wherever possible, the same or similar parts are given the same reference numerals in the drawings and the description. Referring to FIG. 2, it is a block diagram of a data processing apparatus 200 having a multiplication and addition operation according to a preferred embodiment of the present invention. This data processing device 2000 includes a multiplier 130, ~ adder 5o, and a selector 16Q. Data Department 06349twf2.doc / 006 Revised 92.12.1 Provided by a Special Register Bank 110 and a General Register Bank 120. This multiplier 130 is coupled to an adder 150. The special register group 110 and the general register group 120 are referred to as the selector 160. The selector 16o is coupled to the adder 15o. General temporary storage = group 120 is also directly weighed to adder 15〇. The data processing device 2Q0 further includes a detection device 170 coupled to the adder 150. The multiplier 130 can multiply two N-bit input signals and obtain a 2N-bit result. For example, NχN gives a 2N result. As shown in FIG. 2, the first N-bit input signal represented by E is the first N-bit signal (Operand) and the second N-bit signal (the second operator) indicated by F. Both Combined into a 2N bit signal, and input to the multiplier 30. The multiplier 13Q performs a multiplication operation to generate a multiplication result signal having 2N bits. The multiplication result signal generated by the multiplier 130 is sent to an adder 150 having a 2N-bit adder function, and is added with an addition signal 152. The addition signal 152 is also 2N bits, including a first N bit portion and a second N bit portion. Only one adder is required in the present invention to provide more desired calculations. For example, in the conventional technique, if calculations such as ΝχΝ + Ν-N and ΝχΝ + 2Ν-2N are desired, as shown in the conventional art, at least two adders are needed to complete such calculations. However, the circuit shown in Figure 2 in the preferred embodiment of the present invention can complete such operations, which will be described in detail below.
於本發明中，提供一種類信號(Class signal)100以選擇 二不同指令種類中之其中一種運算。種類信號1〇〇指示將 要運算那種指令種類，例如，如第一種類的ΝχΝ+2Ν—2N 579483 06349twf2.doc/006 修正日期92.12.1 或第二種類的ΝχΝ+Ν—N之運算。此種類信號丨⑽係由一 外部裝置提供給資料處理裝置200的解碼指令（Decoding Instruction)所設定。第一種類的運算將需要更多的計算時 間，而其可具有較精確的計算結果。而第二種類的運算， 因爲最終結果係僅N位元，因此結果較不如第一種類運算 精確，但卻較節省運算的時間。 當指令種類爲第一種類，即如果想要的計算是ΝχΝ+2Ν —2N，種類信號100使選擇器160從一般暫存器組120提 供資料給加法器150。也就是說，加法信號152的2N位元 由（N，N)表示。加法信號152的第一 N位元部份以c表示， 加法信號152的第二N位元部份以D表示。第一 N位元 部份C由一般暫存器組120提供。第二N位元部份D直 接從一般暫存器組120提供。 當指令種類爲第二種類，即如果想要的計算是ΝχΝ+Ν ->Ν ，種類信號100使選擇器160從特殊暫存器組no提 供資料給加法器150。也就是說，第一 Ν位元部份C由特 殊暫存器組110提供，而此特殊暫存器110可由使用者藉 由軟體的控制下存取。第二Ν位元部份D直接從一般暫存 器組120提供。在本發明之實施例中的資料處理裝置200， 具有2Ν位元的加法信號152則將由加法器150所運算， 而產生具有2Ν位元的加法結果(Accumulated Result)信號 154。而此實施例中，即使ΝχΝ+Ν—N之運算只需要加上 Ν位元並產生具有Ν位元之結果，也如前所述，此加法器 150仍會產生具有2Ν位元的加法結果信號154。 11 579483 06349twf2. doc/006 修正日期92.12.1 這樣的架構具有多個優點，也即爲本發明之特徵。例 如，其中一優點即可以用以監控是否有溢位（Overflow)的 情形產生，此將在底下描述。另外，另一優點即可簡化計 算的複雜性，以降低執行的時間。例如，若是欲計算之算 式如.....+XA，本發明與習知技藝之比較 &=0 將於底下描述。 在以往習知的技術，此程式語言如下： for (k=0； n; k++) {In the present invention, a class signal 100 is provided to select one of two different instruction types for operation. The type signal 100 indicates the kind of instruction to be operated, for example, the operation of the first type of ΝχΝ + 2Ν-2N 579483 06349twf2.doc / 006 the date of revision 92.12.1 or the second type of ΝχΝ + Ν-N. This type of signal is set by a decoding instruction (Decoding Instruction) provided to the data processing device 200 by an external device. The first type of operation will require more calculation time, and it may have a more accurate calculation result. In the second type of operation, because the final result is only N bits, the result is less accurate than the first type of operation, but it saves time. When the instruction type is the first type, that is, if the desired calculation is N × N + 2N-2N, the type signal 100 causes the selector 160 to provide data from the general register group 120 to the adder 150. That is, the 2N bits of the addition signal 152 are represented by (N, N). The first N-bit portion of the addition signal 152 is represented by c, and the second N-bit portion of the addition signal 152 is represented by D. The first N-bit portion C is provided by the general register group 120. The second N-bit portion D is directly provided from the general register group 120. When the instruction type is the second type, that is, if the desired calculation is N × N + N-> N, the type signal 100 causes the selector 160 to provide data to the adder 150 from the special register group no. That is, the first N bit portion C is provided by a special register group 110, and the special register 110 can be accessed by a user under the control of software. The second N bit portion D is directly provided from the general register group 120. In the data processing apparatus 200 in the embodiment of the present invention, the addition signal 152 having 2N bits will be operated by the adder 150 to generate an Accumulated Result signal 154 having 2N bits. In this embodiment, even if the operation of N × N + N-N only needs to add N bits and produce a result with N bits, as described above, the adder 150 still generates an addition result with 2N bits Signal 154. 11 579483 06349twf2. Doc / 006 Amendment date 92.12.1 Such an architecture has a number of advantages, which is a feature of the present invention. For example, one of the advantages can be used to monitor whether an overflow situation occurs, which will be described below. In addition, another advantage is that it can simplify the calculation complexity and reduce the execution time. For example, if the formula to be calculated is .... + XA, the comparison between the present invention and the conventional art & = 0 will be described below. In the conventional technique, this programming language is as follows: for (k = 0; n; k ++) {
Move Xk to R〇 Move Yk to Ri R2-R〇*R! + R2 ; MLA R2, R〇, Rl9 R2 } 其中"MLAM系用以計算NxN+N—N的指令，而經過 執行"MLA"指令之結果係具有32位元的長度。 然而，在本發明之較佳實施例中，程式語言如下： for (k=0； n; k++) {Move Xk to R〇Move Yk to Ri R2-R〇 * R! + R2; MLA R2, R〇, Rl9 R2} where " MLAM is an instruction used to calculate NxN + N—N, and after executing " MLA & quot The result of the instruction has a length of 32 bits. However, in a preferred embodiment of the present invention, the programming language is as follows: for (k = 0; n; k ++) {
Move Xk to R〇 Move Yk to (RCP , R2)=R〇*R1 + (Rcp , R2 )； MLA R2, R〇, R!，R2 } 其中"MLA"係執行ΝχΝ+Ν—N的指令，而經過執行 "MLA”指令之結果係具有64位元的長度。 在本發明的較佳實施例中，所得的結果係具有64位 元，然根據習知技術所得的結果，其長度係32位元。若 12 579483 06349twf2.doc/006 修正日期92.12.1 在習知的技術中，想到得到相同的結果，也就是64位元 的結果’則需要執行如上所述之第一種類的NxN+2N~>2N 之運算。也就是說，需要更多的計算時間。因此，如上所 述’本發明實施例若是針對相同的64位元結果，則可簡 化整個運算的複雜度，更可簡化運算的時間。 在經過加法之運算後，加法器15〇產生加法結果信號 154。加法結果信號154包括第一 n位元部份Η及第二N 位元部份I。此加法結果信號154將是資料處理裝置200 的計算結果。除此之外，此加法結果信號154也可以輸入 至一偵測裝置170中，而用以偵測溢位之情形。 當所要處理的指令種類爲第二種類，即想要的計算是 ΝχΝ+Ν-Ν的情況。偵測裝置no將比較加法結果信號154 的第一 Ν位元部份Η與加法信號152的Ν位元部份C。如 果加法結果信號154的第一 Ν位元部份Η與加法信號152 的Ν位元部份c不同，也就是說加法信號152的Ν位元 部份C在累加之後不能保持原有的値，表示本計算中產生 溢位情況。 爲淸楚起見，輸入乘法器130的二Ν位元信號分別以 Ε與F表示。ΝχΝ+Ν—Ν指令的計算可以由本發明以E*F+CD —HI實施。對NxN+2N—2N指令而言，加法器將CD加到 E*F相乘運算的結果以得到HI結果。本發明之實施例中只 執f了一種計算的型態，也就是2N+2N—2N，對N*N+N->N 種類指令，加法器將CD加到E*F相乘運算的結果以得到 HI結果。η在此狀況中是溢位指標。如果在加法運算後Η 13 579483 06349twf2.doc/006 修正日期92.12.1 不等於c，則產生溢位。 溢位指示以快速及方便的方式提供使用者有用的訊 息，而第1圖之習知相乘相加裝置卻未提供溢位指示。這 是本發明另一優點。 很明顯地，對熟悉本技藝之人士而言在不脫離本發明 範圍及精神的情況下可對本發明結構有不同的修改。基於 內容而言，本案包含落入以下本發明之申請專利範圍及其 均等物之修改及變化。 14Move Xk to R〇Move Yk to (RCP, R2) = R〇 * R1 + (Rcp, R2); MLA R2, R〇, R !, R2} where " MLA " is the execution of the instruction The result of executing the "MLA" instruction has a length of 64 bits. In a preferred embodiment of the present invention, the result obtained has a length of 64 bits. However, according to the results obtained by conventional techniques, the length is 32-bit. If 12 579483 06349twf2.doc / 006 revision date 92.12.1 In the conventional technology, the same result, that is, the 64-bit result, is thought to need to perform the first type of NxN as described above. + 2N ~ &2; 2N operation. That is, it requires more calculation time. Therefore, as described above, if the embodiment of the present invention is directed to the same 64-bit result, the complexity of the entire operation can be simplified, and the Simplify the operation time. After the addition operation, the adder 15 generates an addition result signal 154. The addition result signal 154 includes a first n-bit portion Η and a second N-bit portion I. This addition result signal 154 Will be the calculation result of the data processing device 200. In addition, this addition The fruit signal 154 can also be input to a detection device 170 to detect the overflow situation. When the type of instruction to be processed is the second type, that is, the case where the desired calculation is ΝχΝ + Ν-Ν. Detection The measuring device no will compare the first N-bit portion Η of the addition result signal 154 with the N-bit portion C of the addition signal 152. If the first N-bit portion Η of the addition result signal 154 and the N of the addition signal 152 The bit part c is different, that is, the N bit part C of the addition signal 152 cannot keep the original value after accumulation, which indicates that an overflow situation has occurred in this calculation. For the sake of clarity, the input of the multiplier 130 The two N-bit signals are represented by E and F respectively. The calculation of the ΝχΝ + Ν-Ν instruction can be implemented by the present invention as E * F + CD-HI. For the NxN + 2N-2N instruction, the adder adds CD to E * F multiplies the result of the operation to obtain the HI result. In the embodiment of the present invention, only one type of calculation is performed, that is, 2N + 2N—2N. For N * N + N-> N type instructions, addition is performed. The device adds CD to the result of the E * F multiplication operation to obtain the HI result. Η is an overflow indicator in this case. Hou Ji 13 579483 06349twf2.doc / 006 Amendment date 92.12.1 is not equal to c, then an overflow occurs. The overflow indicator provides users with useful information in a fast and convenient way, and the conventional knowledge of Figure 1 is multiplied and added together. The device does not provide an overflow indication. This is another advantage of the present invention. Obviously, those skilled in the art can make different modifications to the structure of the present invention without departing from the scope and spirit of the present invention. Based on the content, this case contains the modifications and changes that fall within the scope of the patent application of the present invention and its equivalents. 14