TW573328B - Bipolar junction transistor and manufacturing method thereof - Google Patents

Abstract

A bipolar junction transistor (BJT) and its manufacturing method are described. The manufacturing method at least comprises the steps of: providing a substrate having a base, an emitter polysilicon layer, and an insulator stacked in turn thereon, and exposing a part of the substrate, wherein there are the first electrical ions doped in the emitter polysilicon layer; forming spacers on the sides of the emitter polysilicon layer; depositing a raised base on the exposed part of the substrate by utilizing selective epitaxy deposition procedure, wherein there are the second electrical ions doped in the raised base; and forming an external base of shallow junction and deeper emitter by rapid thermal annealing (RTP) process. The present invention characterized to substitute the raised base doped with ions and the rapid thermal annealing process for ions directly implanting into the substrate, not only reduces the transient enhanced diffusion (TED), but also provides the external base of shallow junction and the deeper emitter.

Description

573328 V. Description of the invention (1) The technical field to which the invention belongs: a structure of a bipolar junction transistor (BJT) and a method for manufacturing the same, in particular, it relates to a floating layer base using doped ions (Raised Base) and Rapid Thermal Tempering (Rapid Therinal Annealing; RTA) process to form the external base of the shallow junction (ShaUOw JunctiOn), but its application is not limited to this field. Prior art: Bipolar junction transistors are one of the most important semiconductor components today. The reason why a bipolar-connected transistor is called a "bipolar" is an electronic component that uses two types of carriers, an "electron" and a "hole," to conduct current. The advantage of a bipolar junction transistor is that it is fast, but consumes a lot of energy. When the accumulation of components increases, the problem of heat dissipation becomes a big obstacle for the application of bipolar junction ^ crystal. New applications of silicon germanium (SiGe) technology and related non-: or high-performance product launches are hot topics in the semiconductor industry these days. In the past 5 to 10 years, the application of wireless and southern performance wire has gradually become Shishenhualu (GaAs) and other Group III-V compound semiconductor technology. To break through the main bottleneck of this technological leap forward, you can take advantage of the fact that the band gap of silicon germanium is smaller than that of Shi Xi, so that standard silicon crystals can be converted into heterojunction semiconductors by doping germanium. The material becomes Hetero junction Bipolar Transistor (HBT). And after completing all the component isolation processes, the silicon germanium epitaxial layer is grown on the silicon wafer. In addition, in the silicon germanium epitaxial layer, a boron-doped base npn transistor is used instead of the traditional ion implantation method. This helps reduce the base width and eliminates Gaussian distribution and implant channel effects

Page 8 573328 5. Description of the invention (2) (Channeling) and other component design restrictions. These advantages will significantly improve component performance. In order for the active base of the npn element to be confined in the germanium fossil crystal layer, the temperature of the crystal growth must be sufficiently low (about 500 ° c). Before the wafer is placed in the deposition chamber, it is immersed in a fluorinated gas (H F) solution so that its surface is coated with hydrogen atoms (Hydrogen-Terminated). Once placed in the deposition chamber, a siane gas (Si lane; Si H4) was immediately passed through for the worm crystal sequence. At the same time, germanium and other elements can be accurately doped during the epitaxial process to serve as the base of HBT. Please refer to FIG. 1 to FIG. 6, which are cross-sectional views showing a process for manufacturing a bipolar junction transistor by a conventional technique. First, a substrate is provided. The material is silicon, and the substrate 1 already has a worm crystal layer 5, a buried layer 11, a collector 13, a plurality of shallow trench isolations 12, and a plurality of The first dielectric layer 14 forms a plurality of second dielectric layers ι5, a base electrode 16, a plurality of third dielectric layers 17, a plurality of fourth dielectric layers 18, and an emitter polycrystalline silicon ( Emitter Poly-Si 1 icon) The layer 19 is on the epitaxial layer 5 and the first dielectric layer 14 as shown in the first figure, in which the material of the base 丨 6 is germanium fossil, and the emitter is polycrystalline silicon. The layer 9 has been doped with a plurality of first electrical ions. Next, a first definition step is performed, which uses a lithography process and an anisotropic etching method to remove parts of the emitter polycrystalline silicon layer 19, the fourth dielectric layer 丨 8, and the third dielectric layer 17, thereby exposing a portion The base electrode ι6 forms a structure as shown in FIG. 2. Then, the spacer 20 is formed by chemical vapor deposition and anisotropic etching, and the structure shown in FIG. 3 is completed. The material of the spacer 20 is silicon dioxide (Siiicon Dioxide; Si02). . Then, an ion implantation process is performed, and an emitter polycrystalline silicon layer with a spacer 20 is used as a cover.

Page 9 573328 V. Description of the invention (3) The screen uses a plurality of second electrical ions 21 to perform a heavy doping process on the entire wafer to form the structure shown in FIG. 4. Then, referring to FIG. 5, the second definition step is performed by using a lithography process and an anisotropic etching method to remove a portion of the base electrode 16 and expose a portion of the second dielectric layer 15. Next, a tempering process is performed to convert the exposed base 16 to an extended base 22, and to make the plurality of second electrical ions 21 in the emitter polycrystalline silicon layer 9 into the base downward. 16 to form the emitter 23, as shown in FIG.

As in the conventional manufacturing process described above, when the critical line width (Critical Diimensi ο η; CD) of the device is reduced to 180 nanometers (nm) or even smaller, the doped region in the transistor becomes shallower and shallower. , The doping ion concentration must be increased,

The shape of the dopant ion concentration distribution will change more significantly, so strictly controlling the horizontal diffusion of the junction is the key to reducing the effects of Punch Through and Short Channel (S h rt C ha η ne 1). . Although the low-energy ion implantation process and the rapid thermal tempering process can form a shallow junction, the channel effect of the ions when implanting the substrate will still cause a significant impact on the location of the ion implantation. That is, the depth of the joint will be affected. In addition, the diffusion of doped elements in the wafer is further affected by many process parameters and material characteristics. In addition to the types of doping elements, the process temperature or defect-induced transient enhanced diffusion (TED) effect of ion implantation in the base of silicon germanium will change the diffusion behavior of ions in the base. These factors affect the deepening of the junction in the extended base 22, the electron transfer speed is slower, the RC (Resistance-Capacitance) delay is larger, and the formed emitter 23 is also shallower.

Page 10 573328 V. Description of the invention (4) It is necessary to develop a double carrier-connected transistor to develop a better enhanced diffusion effect. 0 Summary of content: In view of the above invention, the junction surface of the extended base of the ion implantation base is large, and at the same time The main objective method of the present invention is to use the process of the floating layer base in the Depos iti on method, so that the floating layer base knowing technology directly uses another method of the present invention, which uses absolute selectivity. The epitaxial ions are focused on extending another aspect of the present invention, which is to use doped ions to dope into the base, the diffusion effect, and to reduce the ion implantation according to the above-mentioned process in the entire semiconductor manufacturing process. In the background of the extended base providing a shallow junction, the instantaneous enhanced diffusion and deepening caused by the double-carrier concatenation is performed, and the electron transfer speed is also shallower than that of the emitter. One of them is to provide a dual-carrier selective epitaxial deposition (Select deposited floating layer base is exposed; doped with a plurality of ions, and a plurality of ions in the penetrating doped into the base caused by ion implantation of the base In order to provide a double carrier linking edge layer and the barrier wall, the emitter multiple deposition method and the rapid thermal tempering process are used to improve the electrons. The rapid thermal return result can reduce the extension of the base into a shallow junction of the ion implanted base and the purpose. The invention provides a dual-importance method, so the process of the instantaneous pole and the deeper radio-transistor caused by the base is provided. Effect, which will affect the slower RC delay than the base of the VE Epitaxy P connected to the transistor, which is too fast in thermal tempering. As a result, the impact can be avoided. The crystal silicon layer of the transistor makes subsequent In order to transfer a plurality of speeds. The structure of the transistor, the fire process, to enhance the deep emitter instantaneous. Carrier connection transistor 573328 5. The structure of the invention (5) and its manufacturing method, this manufacturing The method includes at least the following steps: first, a substrate is provided, in which a base, an emitter polycrystalline silicon layer, and an insulating layer are sequentially stacked on the substrate, and a part of the base is exposed, wherein the emitter polycrystalline silicon layer is doped with a plurality of first Electrical ions; Next, a barrier wall is formed on both sides of the emitter polycrystalline silicon layer; Then, a selective epitaxial deposition method is used to deposit a floating layer base on the exposed part of the base, wherein the floating layer base is doped with a plurality of A second electrical ion; and a rapid thermal tempering process to form an extended base and a deeper emitter with a shallow junction. Embodiments: The present invention discloses a method for manufacturing a bipolar junction transistor, which The selective epitaxial deposition method is used to deposit the floating layer base on the exposed part of the base. The floating layer base has been doped with a plurality of ions, and is formed by a rapid thermal annealing process to form a shallow junction. Extended base and deeper emitter. In order to make the description of the present invention more detailed and complete, you can refer to the following description and cooperate with Figures 7 to 12 to illustrate a preferred embodiment of the present invention. Double carrier A cross-sectional view of the manufacture of a transistor. Please refer to FIG. 7. First, a substrate 100 is provided, which is made of silicon and has an epitaxial layer 105, a buried layer 1U, a collector 113, and a plurality of substrates 100. Shallow trench isolation 11 2 and a plurality of first dielectric layers 114 are sequentially formed on the substrate into a plurality of first dielectric layers 115, a base 116, a plurality of third dielectric layers 117, and a plurality of fourths. The dielectric layer i 丨 8, the emitter polycrystalline silicon layer i 丨 9, and the insulating layer 120 are on the substrate 100, as shown in FIG. 7, wherein the material of the base electrode ii6 is germanium fossil, The emitter polycrystalline stone layer 119 has been doped with a plurality of first electrical ions. In addition, in FIG. 7, the insulating layer 12 is covered on the emitter.

Page 12 573328 V. Description of the invention (6) The crystal chip layer 119 'is used to isolate the emitter polycrystalline silicon layer 119 during the subsequent ion implantation process. Next, the first definition step is performed, which uses a lithography process and anisotropic etching to remove parts of the insulating layer 120, the emitter polycrystalline silicon layer 119, the dielectric layer 118, and the third dielectric layer 117, thereby exposing A part of the base electrode 116 is formed as shown in FIG. 8. Then, a spacer 121 is formed by chemical vapor deposition and anisotropic etching, so that the emitter polycrystalline silicon layer 119 / the fourth dielectric layer 118 and the third dielectric layer 117 are insulated by the insulating layer 12 and the spacer i2i It is enclosed to form a structure as shown in FIG. 9, wherein the material of the partition wall 121 is silicon dioxide. After that, 'use the selective m product &' to deposit the floating layer base 122 on the exposed portion of the base 116 to form a structure as shown in FIG. 10 in which a plurality of floating layer bases 122 are doped. The second electrical ion 123, and the plurality of second s electrical ions 1 23 are P-type ions' whose material is boron (B0ron; b). Then 'Please refer to FIG. 11 for the second definition step, which uses a lithography process and anisotropic etching to remove part of the floating layer base 22 and part of the base 116' to expose part of the first Two dielectric layers lb. — The rapid thermal tempering process, by thermal diffusion, C, a plurality of second electrical ions 123 in the floating layer base 122 are doped into the base 116, so as to contact the floating layer base 122 The base electrode 116 is transformed into an extended base electrode 124 to form an emitter electrode 12 5 and a structure as shown in FIG. 12. According to the manufacturing method of the dual-carrier connection transistor provided by the present invention, at least the characteristics include that the insulating layer 120 is used to separate the emitter and the spacer 121 from each other.

Page 13 573328 V. Description of the invention (7) Layer 1 1 9 so that a plurality of second electrical ions 123 can be concentrated in the extended base 124 during the selective epitaxial deposition method and the rapid thermal tempering process. This improves the electron transfer speed. According to the manufacturing method of the double-carrier connection transistor provided by the present invention, the method also includes using a floating layer base 1 2 2 doped with a second electrical ion 1 2 3 and a rapid thermal tempering process to replace it. The conventional technique directly implants the base 1 1 6 ′ with the ion, thus reducing the second electrical ion 1 2 3 by implanting the base 1 1 6 with a transient enhanced diffusion effect. Reference is made to Figure 13 for reference, which is a preferred embodiment of the present invention. The relationship between the ice level of the joint, the concentration of implanted ions and the concentration of implanted ions

Illustration. The dashed line 126 indicates the depth of the junction and the implanted arsenic ion concentration of the double-junction transistor manufactured by the conventional technology, and the dashed line i 2 7 indicates the depth of the junction-connected transistor manufactured by the conventional technology. And the implanted boron ions are thick and solid. The solid line 1 2 8 shows the results of the connection depth of the sub-connected transistor and the concentration of arsenic ions implanted in a preferred embodiment of the present invention. 2: It shows the results of the electrical depth of the double-carrier connection and the ion concentration in the implantation shed manufactured in a preferred embodiment of the present invention. Comparing the dashed line 126 with # Li / μ in the case where the arsenic ion concentration is the same, the depth of the two ions is doped; te π ^ Θ is away from l30. Then compare the dashed line 127 and the solid line 129. At the concentration of boron ions == 深度, the difference in the depth of the two ions ... 131. its

The red and 131 in the base are due to the instantaneous enhancement of the diffusion effect of the ions directly implanted by the conventional technology, which makes the ion implantation of the crystal boat by the conventional technology deeper. This leads to the slower transfer speed of the & weighted electrons formed in the extended base, the larger the rc delay, and the shallower the emitter. Conversely, the present invention-the preferred embodiment

573328 V. Description of the invention (8) The dual-carrier thermal tempering process has a faster transfer rate than the enhanced diffusion process. According to the invention, the tempering process is included. The second electrical invention does not limit the ion species. Therefore, the invention The method exposes a part and penetrates quickly into the base. The impact of the formation. Another method of the present invention is to facilitate selective ion concentration in the base of the present invention, which uses a dopant to dope into the base diffusion effect to connect electricity. Crystal, so it can be shaped quickly, and has a large effect. In addition, the provided dual-doped material is used to place the material of the second ion here. Generally, it is based on one of the advantages of the manufacturing process. The result can be avoided. An advantage is that the insulating layer and the epitaxial deposition method are used to extend the inside of the base. An advantage is that the floating ions are lifted. As a result, a shallow junction can be formed. The ion-doped ion dopant to which the carrier is connected to the electric and electric charge is only required for the reader to be familiar with this technology. It is to provide the base layer of the floating layer in the monosexual crystal deposition so that The layer-knowledge technology directly provides a dual-load spacer wall isolation and rapid thermal return, thereby improving the floating-layer extension base for a dual-layer base and an extended base ion that rapidly reduces the ion implantation surface. Also, the floating layer of the deeper crystal substrate is incorporated into the base. One of the better people can use a double carrier connection method. The deposition connection has been doped with the complex base in the complex base, and the ion implanter is used to connect the electricity. In the process of crystal-ejecting polycrystalline spar fire, the electron transferor is connected to the electric crystal, and is rapidly tempered into the base to cause the pole and the deeper base and fast. Therefore, the above-mentioned embodiment is rapidly heated, but the base of the layer of the transistor to be implanted is exposed to several ions, and several ions are doped into the manufacturing layer of the base, so that the subsequent speed will be a plurality of speeds. The structure, the process, will enhance the emitter moment.

573328 V. Description of the invention (9) As understood by those familiar with this technology, the above is only a preferred embodiment of the present invention and is not intended to limit the scope of patent application for the present invention; all others do not depart from the scope of the present invention Equivalent changes or modifications made under the spirit of disclosure should be included in the scope of patent application described below.

Page 573328 Schematic illustration of the preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, of which: Figures 1 to 6 show the conventional technology for double loading Cross-sectional views of the fabrication of a sub-connected transistor; FIGS. 7 to 12 are cross-sectional views of the fabrication of a bi-connected transistor according to a preferred embodiment of the present invention; and FIG. Relationship between surface depth, implanted boron ion concentration, and implanted arsenic ion concentration. Comparative description of drawing numbers: 1 substrate 5 stupid layer 11 buried layer 12 shallow trench isolation 13 collector 14 first dielectric layer 15 second dielectric layer 16 base electrode 17 third dielectric layer 18 fourth dielectric layer 19 Emitter polycrystalline fragmented layer 20 Gap wall 21 Ion 22 Extended base 23 Emitter 100 Substrate 105 Stupid layer 111 Buried layer 112 Shallow trench isolation 113 Collector 114 First dielectric layer 115 Second dielectric layer 116 Base 117 Third dielectric layer 118 Fourth dielectric layer 119 Emitter polycrystalline silicon layer 120 Insulating layer 121 Gap wall

Page 17 573328 Simple illustration of the drawing 1 2 2 Floating layer base 123 Ion 124 Extended base 125 Emitter 126 Dotted line 127 Dotted line 128 Solid line 129 Solid line 130 Gap 131 Gap

(I p. 18

Claims (1)

573328 VI. Scope of patent application I. A method for manufacturing a bipolar junction transistor, at least including: exposing a part of the base: for: materials, in which a base and a plurality of dielectrics are sequentially stacked on the base Increasing, an emitter polycrystalline silicon layer and an insulating layer, and violating the electrode; forming a spacer on each side of the insulating layer, the emitter polycrystalline silicon layer and the dielectric layers; and forming a floating layer base ( Raised Base) is exposed on the part of the base electrode 'wherein the floating base electrode is doped with a plurality of ions; and a rapid thermal tempering process is performed to form an external base and an emitter The pole is in the base. 2. The method for manufacturing a bipolar junction transistor as described in item 1 of the scope of patent application, wherein the material of the base electrode is silicon germanium (Si Ge). 3. The method for manufacturing a bipolar junction transistor as described in item 1 of the scope of patent application, wherein the step of forming the base of the floating layer is performed by a selective epitaxial deposition (Selective Epitaxy Deposition) method. 4 · The method for manufacturing a bipolar junction transistor according to item 1 of the patent application, wherein the ions are P-type ions. 5. The manufacturer of the bipolar junction transistor as described in item 1 of the scope of patent application Page 19 573328 6. The scope of patent application method, in which the extended base is a shallow junction structure. 6. A method for manufacturing a bipolar junction transistor, at least comprising: providing a substrate, wherein a plurality of first dielectric layers, a base, a plurality of second dielectric layers are sequentially stacked on the substrate, A plurality of third dielectric layers, an emitter polycrystalline silicon layer, and an insulating layer; A first definition step is performed to remove part of the insulating layer, part of the emitter polycrystalline silicon layer, part of the third dielectric layers, and part of the second dielectric layers, thereby exposing a part of the base electrode. Forming a gap wall on each side of the insulating layer, the emitter polycrystalline silicon layer, the third dielectric layers and the second dielectric layers; performing a selective epitaxial deposition step to form a floating layer base On the part of the base electrode that is exposed, wherein the floating layer base has been doped with a plurality of first electrical ions; a second definition step is performed to remove part of the floating layer base and another Part of the base is used to expose part of the first dielectric layers; and a rapid thermal tempering process is performed to form an extended base and an emitter in the base. 7. The method for manufacturing a bipolar junction transistor as described in item 6 of the patent application, wherein the emitter polycrystalline silicon layer includes a plurality of second electrical ions. Page 20 6. Scope of patent application 8 · For example, the dual-load method described in item 6 of the patent scope, where the base material f is the manufacturer of the wrong / carrier-connected transistor 9 Scope method, wherein the first definition step is performed by a manufacturing process of a bi-carrier / connector crystal. The first electrical ions in the manufacturing of the bipolar junction transistor described in item 6 of the Shen / Secondary Technical Secondary School's Second Range Rule 6 using a micro-shirt process and an anisotropic method are P-type ions. (2) The method for manufacturing a bipolar junction transistor as described in item 6 of the patent application, wherein the first electrical ions are boron (B0rron; B). 12. The method for manufacturing a bipolar junction transistor described in item 6 of the scope of the patent application, wherein the second definition step is performed using a lithography process and an anisotropic #etching method. 13. The method for manufacturing a bipolar junction transistor as described in item 6 of the scope of the patent application, wherein the rapid thermal tempering process involves doping the first electrical ions into the base of the floating layer into the base. Extremely. 1 4 · The method for manufacturing a bipolar junction transistor as described in item 7 of the patent application range, wherein the rapid thermal tempering process removes the second electrical ions from the emitter polycrystal Is incorporated into the base. Page 21 573328 VI. Scope of patent application 1 5 · According to method 6 of the scope of patent application, wherein the extended base is the manufacturing of a bipolar junction transistor as described above, a shallow junction structure. ^ 6 · —A structure of a bi-carrier connection transistor, including at least: a substrate stacked in sequence-a base, a plurality of dielectric layers, a = layer and an insulating layer, and exposed-part of the Base; = wall knife is located on both sides of the insulating layer, the emitter polycrystalline silicon layer and the layer; and a floating layer base is located on the part of the base exposed. 17. The structure of the bipolar junction transistor described in item 6 of the scope of the patent application, wherein the base of the floating layer further includes a plurality of ions. 18 · The structure of the bipolar junction transistor described in item 17 of the scope of the patent application, wherein the ions are p-type ions. 19. The structure of the bipolar junction transistor described in item 16 of the scope of the patent application, wherein the base further includes an extended base and an emitter, and the extended base is located on the floating layer base. The base is below, and the emitter is located in the base below the polycrystalline layer of the emitter. 2 0. The structure of the bipolar junction transistor described in item 19 of the patent application scope, wherein the extension base is a shallow junction structure. 573328 VI. Scope of patent application 2 1. The structure of the bipolar junction transistor described in item 19 of the scope of patent application, wherein the extended base further includes a plurality of ions. 2 2. The structure of the bipolar junction transistor described in item 21 of the scope of the patent application, wherein the ions are P-type ions. Page 23