TW554424B - Method of forming a gate structure and a self-aligned contact structure - Google Patents

Abstract

A method of forming a gate structure and a self-aligned contact structure comprises the steps of: depositing a first conductive layer on a substrate; depositing a second conductive layer on the first conductive layer; depositing an insulating layer on the second conductive layer; performing photolithographic and etching steps to remove selected portions of the insulating layer; etching a portion of the second conductive layer without etching its bottom surface; etching a portion of the remaining second and first conductive layers to form gate structures; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer which covers the gate structures; removing selected portions of the dielectric layer between the gate structures so as to form self-aligned contact windows; and forming a metallization layer which covers the windows with the contact being formed at the exposed surface of the substrate between the metallization layer and the substrate.

Description

554424 A7 __B7 _ V. Description of the invention (,) Field of invention The invention generally relates to a method for forming a gate structure and a self-aligned contact window structure; in particular, the invention is a method for removing previous techniques in semiconductor manufacturing processes. The shortcomings of the gate conductor / bitline contact (GC / CB) short circuit formed in the method and the method of increasing a larger process window. BACKGROUND OF THE INVENTION Generally, a metal oxide semiconductor (MOS) device is composed of a metal layer, an oxide layer, and a substrate. Due to the poor adhesion between metal and oxide ’polycrystalline silicon is often used to replace the metal to form the conductive layer of the gate structure of the MOS device. However, the disadvantage of polycrystalline silicon is that its resistance is higher than that of metal. Although it can be doped by impurities to reduce the resistance, the resulting conductivity cannot be used as a good conductive layer in MOS devices. A common solution is to add a layer of metal sulfide on the polycrystalline fragment layer, such as a fragmented crane (WSi) layer, to improve the conductivity of the gate structure. In the prior art, a method of forming a contact window structure includes the following steps: forming a dielectric layer, forming a contact window, and forming a metal layer. When forming a metal contact between a metal layer and a substrate, the most widely used method is a self-aligned etching method. 1A to 1C show a conventional method for forming a gate structure. The process is as follows: Referring to FIG. 1A, a substrate 2 is first prepared; then, a plurality of separated gate structures are formed on the substrate 2, where each gate The pole structure includes a first conductive material layer 4, a second conductive material layer 6, an insulating layer 8 and a side wall. This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 554424 A7 B7 V. Description of the invention (2) Spacer 10. After the gate is formed, a dielectric layer 12 is formed to cover the entire substrate 2. Referring to FIG. 1B, lithography and etching steps are then performed on the dielectric layer 12 to remove a selected portion between the gate structures until the upper surface of the substrate 2 is exposed. This etching step is also effective for the insulating layer 8 and the sidewall spacer 10, but its etching rate is slow, so a part of the insulating layer 8 and the sidewall spacer 10 is also etched. As a result, a contact window 20 is formed between the gate structures, which can be self-aligned to a position where a contact region is formed on the substrate 2. As shown in the figure, the contact area is formed at the exposed surface of the substrate 2 and its width is X. Referring to FIG. 1C, a metal layer 14 of a specific thickness is then deposited on the entire surface of the entire wafer to cover the exposed surface of the dielectric layer 12, the sidewall spacer 10 and the substrate 2 of the gate structure. Thereby, a metal contact having a width X is formed between the metal layer 14 and the substrate 2 in the self-aligned contact window 20. The contact resistance value of the aforementioned self-aligned contact is proportional to the contact area (that is, the area indicated by the width X) between the metal layer 14 and the substrate 2. During the etching process, the contact area can be increased by extending the etching time. However, if the etching time is not properly controlled, this method will cause the insulating layer 8 and the sidewall spacer layer 10 to be over-etched, and the second conductive material layer 6 below it will be exposed. The exposed portion of the second conductive material layer 6 will contact the metal layer 14 at the point 16 and cause a short circuit. In order to improve the above-mentioned traditional process, the prior art US Patent No. 5,989, 987 provides an improved method for forming a self-aligned contact window structure (refer to FIGS. 2A to 2D). The method is as follows: Reference Figure 2A, first prepare a substrate 2 on top of which is a first conductive -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm); binding

554424 A7 B7 V. Description of the invention (3) Material layer 4, a second conductive material layer 6, and an insulating layer 8. The surface of the substrate 2 is etched by dry etching to form a plurality of separated gate structures. Referring to FIG. 2B, the second conductive material layer 6 is then etched with an etchant mixed with NH4OH, H202, and H20. Although the purpose of the etchant is to etch the second conductive material layer 6, the first conductive material layer 4 thereunder is also etched at a slower rate. After the etching is completed, a sidewall spacer layer 10 is formed on each gate structure. Referring to FIG. 2C, a dielectric layer 12 is then formed on the entire surface of the entire wafer to cover all the gate structures and the exposed surface of the substrate 2. Selected portions of the dielectric layer 12 between the gate structures are then removed until the upper surface of the substrate 2 is exposed. Referring to FIG. 2D, a metal layer 14 of a specific thickness is then deposited on the entire surface of the entire wafer to cover the exposed surface of the dielectric layer 12, the sidewall spacer 10 and the substrate 2 of the gate structure. Thereby, a metal contact is formed between the metal layer 14 and the substrate 2 in the self-aligned contact window 20. The advantage of the method provided by the above-mentioned prior art U.S. Patent No. 5,989,987 is that there is an additional etching step for the second conductive material layer 6, by which an etching step causes the width of the second conductive material layer 6 to be wider than the insulating layer thereon. 8 is narrow, thereby forming a larger process window to prevent the second conductive material layer 6 from short-circuiting with the metal layer 14 at the point 16. However, the method for forming a self-aligned contact window structure provided by US Patent No. 5,989, 987 has the following disadvantages: (1) the etching step for the second conductive material layer 6 will also etch the first conductive material at a slower rate Material layer 4 to make it -6-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm)!

554424

= The boundary size (ecaal dlmensiQn) decreases, the channel length (eh_ei⑹ 州 decreases, and the critical voltage (ντ) decreases; ⑺ due to the section of the second conductive material layer 6: the product becomes smaller, which causes the resistance of the interpolar conductor (3) This step will reduce the contact area between the second conductive material 6 and the first conductive material layer 4. If the contact area is reduced too much, it will cause peeling. Summary of the Invention The main purpose is to provide a method for forming gate structure and self-aligned contact window structure. The self-aligned contact window structure formed by this method can form a larger process tolerance and maintain the critical size of the first conductive material layer. , Channel length, critical voltage, cross-sectional area of tungsten silicide layer, resistance value and avoiding the peeling phenomenon between the second conductive material layer and the first conductive material layer, the method includes: (1) on the entire upper surface of a substrate Depositing a first conductive material layer; (2) depositing a second conductive material layer on the entire upper surface of the first conductive material layer; (3) depositing an insulating layer on the entire upper surface of the second conductive material layer ; ( 4) performing lithography and etching processes to remove selected portions of the insulating layer; (5) using an etchant having an etching rate higher than that of the insulating layer to etch the second conductive material Stop the etching before the material layer is etched to the lower surface of the second conductive material layer; (6) perform an etching process on the second conductive material layer and the first conductive material layer until the substrate stops etching to form a plurality of gates Electrode structure; (7) forming a sidewall spacer layer on the side walls of each gate structure; (8) forming a dielectric layer covering all gate structures; -7-This paper standard applies to Chinese National Standard (CNS) A4 size (210X297 mm) binding

k 554424 12 dielectric layer 14 metal layer 16 point 20 self-aligned contact window A7 B7 V. Description of the invention (5) (9) Remove the selected part of the dielectric layer between the gate structures until the surface of the substrate is exposed To form a self-aligned window; and (10) forming a metal layer covering the exposed surface of the dielectric layer and the sidewall spacer of the gate structure, and exposed between the metal layer and the substrate The substrate surface forms a self-aligned contact. The drawings briefly illustrate the present invention through the embodiments and the drawings to make the technical content, features, and effects of the present invention easy to understand, wherein FIG. 1A to FIG. 1C are the traditional methods of forming a self-aligned contact window structure; FIGS. 2A to 2D are methods of forming a self-aligned contact window structure in the prior art US Patent No. 5,989,987; FIGS. 3A to 3F are steps of a method of implementing a gate structure and a self-aligned contact window structure according to the present invention; The structure obtained afterwards; and FIG. 4 is a flowchart of a method for forming a gate structure and a self-aligned contact window structure according to the present invention. Schematic element symbol description 2 Substrate 4 First conductive material layer 6 Second conductive material layer 8 Insulation Layer 10 sidewall spacer -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

554424 A7 B7 V. Description of the invention (6) Detailed description of the invention The preferred embodiment of the present invention is represented by the structure shown in FIGS. 3A to 3F and the method shown in FIG. At first, a substrate 2 is prepared, and a first conductive material layer 4, a second conductive material layer 6, and an insulating layer 8 are sequentially formed thereon. As shown in Figure 4, open the gate conductor (GC) shield (step 401). This method differs from the method of forming self-aligned contacts in the prior art U.S. Patent No. 5,989,987 in that the method of the present invention does not directly etch to the surface of the substrate 2 by dry etching to form a plurality of separate gate structures, but first etches It stops at the lower surface of the insulating layer 8 (step 402), as shown in FIG. 3A. The first conductive material layer 4 may be a polysilicon or amorphous silicon layer, and the second conductive material layer 6 may be a metal fragmentation layer, such as tungsten tungsten (Wsi), and the insulating layer may be nitrogen. Siliconized (SiN) layer. The etching process may be dry etching. As shown in FIG. 3B and FIG. 4, an upper surface of the second conductive material layer 6 is then etched with an etchant (step 403). The etchant has a higher etching rate on the second conductive material layer 6 than on the insulating layer. Etching rate of 8. Note that since the second conductive material layer 6 is not etched to its lower surface, the first conductive material layer 4 is not in contact with the etchant and will not be etched. The etchant is preferably a mixed etchant of ΝΗ4ΟΗ, Η202 * Η20, its temperature is preferably about 55 ° C to 85 ° C, and the etching time is preferably about 5 to 30 minutes. The etching is isotropic etching. As shown in FIG. 3C and FIG. 4, an etching process is then performed to etch the second conductive material layer 6 and the first conductive material layer 4 until it is etched to the upper surface of the substrate (step 404). The etching process may be dry etching. -9-This paper size is applicable to Chinese National Standard (CNS) A4 (210X 297mm) m binding

Line 554424 A7 _______B7 V. Description of the invention (7) As shown in FIG. 3D and FIG. 4, after the etching is completed, a sidewall spacer layer 10 is then formed on the sidewall of each gate structure (step 405), The sidewall spacer 10 may be silicon nitride (SiN). As shown in FIGS. 3E and 4, a dielectric layer 12 ′ is formed on the entire surface of the entire wafer to cover all the self-aligned contact window structures and the exposed surface of the substrate 2. Then, the dielectric layer 12 in a selected portion between the gate structures is removed by lithography and etching until the upper surface of the substrate 2 is exposed to form a self-aligned contact window 20 (step 406). As shown in FIG. 3F and FIG. 4, a metal layer 14 of a specific thickness is then deposited on the entire surface of the entire wafer to cover the exposed surface of the dielectric layer 12, the sidewall spacer 10 of the gate structure, and the substrate 2. Thereby, a metal contact is formed between the metal layer 14 and the substrate 2 in the self-aligned contact window 20 (step 407). The method provided by the present invention can solve all the shortcomings of the traditional method of forming a self-aligned contact window structure and the method of forming a self-aligned contact window structure of the prior art US Pat. The upper half of the second conductive material layer 6 is etched, so that compared with the traditional method of forming the gate structure, a larger contact window can be caused to prevent the second conductive material layer 6 from shorting the metal layer 14 at point 16; 2) When the upper surface of the second conductive material layer 6 is etched with an etchant, the critical size is not reduced, the channel length is reduced, and the critical voltage is not etched to the first conductive material layer 4. (VT) decreases; (3) Because the contact area between the second conductive material layer 6 and the first conductive material layer 4 remains unchanged (because neither the lower half of the second conductive material layer 6 nor the first conductive material layer 4 is etched) ), So the resistance value of the gate conductor is almost unchanged; (4) It will not cause -10 when etching-this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm); · binding

554424 A7 B7 V. Description of the invention (8) The contact area between the second conductive material layer 6 and the first conductive material layer 4 is reduced, so that it does not cause peeling. The features and technical contents of the present invention have been fully disclosed as above. Any person skilled in the art can make various substitutions or modifications based on the disclosure and teachings of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the disclosed embodiments, but should cover these substitutions and modifications. -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

554424 A8 B8 C8 Patent Application Scope 1. A method for forming a gate structure, including the following steps: G) depositing a first conductive material layer on the entire upper surface of a substrate; (2) the first conductive material layer A second conductive material layer is deposited on the entire upper surface; (3) a cover layer is formed on the entire upper surface of the second conductive material layer to expose a portion of the second conductive material layer; (4) the second conductive material layer is used An etchant having a higher etching rate of the conductive material layer than the mask layer to etch the second conductive material layer and stop etching before it has etched to the lower surface of the first conductive material layer; and (5) the The second conductive material layer and the first conductive material layer are subjected to an etching process to the substrate to form a plurality of gate structures. 2 · The method for forming a gate structure as described in the first item of the patent application scope, wherein the method for forming the cover layer in step (3) includes the following steps: (a) on the entire upper surface of the second conductive material layer Depositing an insulating layer; and (b) performing a lithography and etching process to remove selected portions of the insulating layer. 3. The method for forming a gate structure according to item 2 of the scope of patent application, wherein the etching process of step (b) is dry etching. 4. The method for forming a gate structure as described in the first item of the patent application, wherein the etching in step (4) is isotropic etching. 5. The method for forming a gate structure according to item 丨 of the application, wherein the etching process in step (5) is dry etching. 6. The method for forming the gate structure as described in the first item of the scope of patent application, wherein the etchant of step (4) is NH4OH, Η202 * Η20 mixture. -12-k order This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^^ JAB c D 554424 々, patent application scope 7. For the method of forming the gate structure in item 6 of the patent application scope, where ΝΗ4ΟΗ The Η202 * Η20 hybrid is etched at a temperature of 55 ° C to 85 ° C. 8. The method for forming a gate structure according to item 7 of the application, wherein the etching time is 5 to 30 minutes. 9. A method of forming a self-aligned contact window structure, comprising the following steps: (1) depositing a first conductive material layer on an entire upper surface of a substrate; (2) over the entirety of the first conductive material layer Depositing a second conductive material layer on the surface; (3) depositing an insulating layer on the entire upper surface of the second conductive material layer; (4) performing a lithography and etching process to remove selected portions of the insulating layer; ( 5) Use an etchant with a higher etch rate for the second conductive material layer than for the insulating layer to etch the second conductive material layer, and stop etching before it has etched to the lower surface of the second conductive material layer; (6) performing an etching process on the second conductive material layer and the first conductive material layer to the substrate to form a plurality of gate structures; (7) forming a sidewall spacer layer on a sidewall of each gate structure; (8) forming a dielectric layer covering all gate structures; (9) removing selected portions of the dielectric layer between the gate structures until the surface of the substrate is exposed to form a self-aligned window; and (10) Exposed to form a dielectric layer Surface, a gate structure sidewall spacer layer is a metal layer, and is exposed between the metal of the storm and the substrate layer are formed self-aligned contact with the substrate surface. 10. The method of forming a self-aligned contact window structure as described in the scope of application for patent No. 9 -13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 554424 A8 B8 C8 ------------ D8 Patent application method, wherein the first conductive material layer is a polycrystalline silicon layer. U. The method for forming a self-contacting window structure according to item 9 of the patent application, wherein the first conductive material layer is an amorphous silicon layer. 12. The method for forming a self-aligned contact window structure according to item 9 of the application, wherein the second conductive material layer is a metal silicide layer. 13. The method of the shape & self-aligned contact 胄 structure according to item 12 of the scope of the patent application, wherein the metal silicide layer is a silicide crane layer. 14. The method of forming a self-aligned contact window structure according to item 9 of the application, wherein the insulating layer is a silicon nitride layer. 15. The method of forming a self-aligned contact window structure according to item 9 of the scope of the patent application, wherein the sidewall spacer layer is a nitrided chip layer. 16. The method for forming a self-aligned contact window structure according to item 9 of the patent application, wherein the etching process of step (4) is dry etching. 17. The method for forming a self-aligned contact window structure according to item 9 of the patent application, wherein the etching of step (5) is isotropic etching. 18. The method of forming a self-aligned contact window structure according to item 9 of the patent application, wherein the etching process of step (6) is dry etching. 19. The method for forming a self-aligned contact window structure according to item 9 of the patent application, wherein the etchant in step (5) is a mixture of h2O2 and h2O. 20. The method for forming a self-aligned contact window structure according to item 19 of the scope of patent application, wherein the NH4OH, H202 and H20 mixed system is etched at a temperature of 55 ° C to 85 ° C. 21 · Such as the method of forming self-aligned contact window structure in the scope of patent application No. 20 -14- S ® household materials (CNS) A4 size (21G X 297 public love) in this paper standard 554424 8 8 8 8 A BCD Patent application method, in which the etching time is 5 to 30 minutes 15 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)