TW432561B - Multi-chip module packaging structure - Google Patents

Abstract

A multi-chip module packaging structure comprises two semiconductor chips mounted on the upper and lower surfaces of a substrate, respectively, by an anisotropic conductive film. The multi-chip module packaging structure is connected to outside via a lead frame. Each of the upper and lower surfaces of the substrate has a plurality of chip bonding pads. The substrate has a plurality of substrate bonding pads electrically connected to the corresponding plurality of chip bonding pads. The lead frame is secured on the substrate and is electrically connected to the corresponding substrate bonding pad. Each of the two semiconductor chip has a plurality of metal bumps formed on a front side of the semiconductor chip. The plurality of metal bumps of each semiconductor chip is electrically connected to the corresponding plurality of chip bonding pads via the anisotropic conductive film. The substrate, the lead frame and the two semiconductor chips are enclosed by an encapsulation body, wherein part of the lead frame is extended from the encapsulation body for electrically connecting to the outside.

Description

-^ 4 32 5 6 1 ____ V. Description of the invention (l) Field of the invention: The present invention relates to a multi-chip package structure module (MCM), and more particularly to an anisotropic conductive adhesive layer. Multi-chip package structure 0 Prior technology: As electronic products become thinner and shorter, the package structures used to protect semiconductor wafers and provide external circuit connections also need to be thinner and thinner. Thin thin outline package structures (TSOP ) Is a representative thin package structure. The main requirement of thin and small outline package structure is thin package thickness (package thickness), the thickness of thin and small outline package structure is about 1 millimeter, and the traditional thin small outline package structure (SOP) or The thickness of the thin small outline package structure (smaU 〇utUne Jjlead (S0J)) is about 2.5 to 3.5 millimeters: the hemp package structure has developed into one of the mainstream technologies, and related :: Hi Hi 也It has matured, so it has a cost advantage, and it is easy to be more. With the miniaturization and high package structure in many electronic devices, the limitation of the operation speed of two or more chip sets can be minimized. The length of the inter-chip connection lines decreases. The most common multi-chip package structure ^ With the increase in operating speed requirements, multi-chips are becoming more attractive. The multi-chip package structure is combined into a single package structure, so that the system's multi-chip package structure can reduce low signal delay and access time. Side-by-side polycrystalline

Seoul 4 32 5 6 1_ V. Description of the invention (2) The chip package structure is to mount two or more wafers side by side on the main mounting surface of a common substrate. The connection between the chip and the conductive lines on the common substrate is generally by wire bonding. However, the disadvantage of the side-by-side multi-chip package structure is that the packaging efficiency is too low, because the available chip mounting area is limited to only one side of the common substrate. Therefore, the semiconductor industry has developed a multi-chip package structure 100 (see the first figure) in which chips are mounted on both sides of a common substrate, respectively. However, a disadvantage of the two-sided multi-chip package structure 100 is that the package thickness cannot be reduced because the sealing compound 110 must free up space to accommodate bonding wires 120 and 130. If the connection between the crystal > ΐ and the conductive lines on the common substrate is flip-chip (f 1 ip ch i ρ), although it can reduce the package thickness, it is better to fill an underfill between the wafer and the common substrate. (underfi 1 1) is used to seal the gap between the wafer and the common substrate and reduce the stress on the solder ball connection (this is due to the different thermal expansion coefficients between the wafer and the common substrate). Since the underfilling step is time consuming and the underfill is expensive, it will increase manufacturing costs. Summary of the invention: The main object of the present invention is to provide a multi-chip package structure whose thickness can be reduced to about one millimeter, thereby being able to be manufactured by a manufacturing process using a conventional thin and small-profile package structure, thereby reducing manufacturing costs. A multi-chip package structure according to a preferred embodiment of the present invention mainly includes two semiconductor wafers mounted on an upper surface and a lower surface of a substrate by using an anisotropic conductive adhesive layer, respectively. versus

^ 4 32 5 6 1 V. Description of the invention (3) External connection. A plurality of chip bonding pads are provided on the upper surface and the lower surface of the substrate, and the substrate is provided with a plurality of substrate contact pads electrically connected to the corresponding plurality of chip bonding pads-the wire The frame is fixed on the substrate and is electrically connected to the corresponding substrate pad. The two semiconductor wafers each have a plurality of metal bumps on the front side of the two semiconductor wafers. The plurality of metal bumps of each semiconductor wafer are electrically connected to the corresponding plurality of wafer connection pads through the anisotropic conductive adhesive layer. The substrate, the lead frame, and the two semiconductor wafers are covered with a colloid, and a portion of the lead frame is extended from the encapsulant for electrical communication with the outside world. According to the multi-chip package structure of the preferred embodiment of the present invention, since the connection between the wafer and the wafer connection pad on the substrate is through the anisotropic conductive adhesive layer, the thickness of the multi-chip package structure can be reduced to about one millimeter. Therefore, it can be manufactured by using the conventional thin and small outline package construction process technology, and thus the manufacturing cost is low. Illustrative description: In order to make the above and other objects, features, and advantages of the present invention obvious, the following describes the preferred embodiments of the present invention in detail with the attached _ as follows. Gangbu 'Figure 1: Figure 2: Removing the sealant Figure 3: Sectional cross-section showing the conventional multi-chip according to the present invention Top view of the first preferred embodiment of the package structure according to the present invention Diagram; polycrystalline package structure of the embodiment; chip package structure of the embodiment;

432561 V. Description of the invention (4) FIG. 4 is a partially enlarged cross-sectional view of the first preferred embodiment of the present invention; and FIG. 5 is a multi-chip package structure with the seal removed according to the second preferred embodiment of the present invention. Top view after the colloid 0 Drawing number description • 100 multi-chip package structure 110 sealing compound 120 connection line 130 connection line 200 multi-chip package structure 210 substrate 2 12 chip connection pad 214 substrate pad 220 lead frame 222 lead 224 gold wire 230 semiconductor Wafer 232 Metal bump 234 Anisotropic conductive adhesive layer 240 Semiconductor wafer 242 Metal bump 244 Anisotropic conductive adhesive layer 246 Conductive particles 250 Sealing compound 300 Multi-chip package structure 330 Chip 332 Chip 340 Chip 342 The second figure and the first ~ solid, which are according to the first preferred embodiment of the present invention The polycrystalline wafer packaging structure 2000 of the embodiment mainly includes a substrate 210, a lead frame 220, two semiconductor wafers 230, 240, and a colloid 250. A plurality of wafer connection pads 2 12 are provided on the upper surface and the lower surface of the substrate 2 10 (see the fourth figure). A plurality of substrates are provided on the upper surface of the substrate 2 1 0

Page 7'βά325β 1 V. Description of the invention (5) Solder pads 2 14 Electrically connected to the corresponding plurality of chip connection pads 212 »The lead frame 220 includes a plurality of wires 222 with inner lead portions and An outer lead portion. The inner leg portions of the plurality of wires 22 are fixed on an upper surface of the substrate 2i with an insulating layer. It can be understood that the inner leg portions of the plurality of wires 2 2 2 may also be fixed on the surface of the substrate 210 with a non-conductive adhesive such as epoxy. The inner leg portion of each of the wires 2 2 2 is connected to the corresponding substrate pad 214 by a connecting wire (such as a gold wire 224). The two semiconductor wafers 230, 240 'have a plurality of metal bumps 232, 242 (refer to the fourth figure) on the front sides of the two semiconductor wafers 230, 240. The plurality of metal bumps 232 and 242 of the two semiconductor wafers 230 and 240 are electrically connected to the upper and lower surfaces of the substrate 210 through a plurality of wafer connection pads 212 via anisotropic conductive adhesive layers 234 and 244 (refer to Four pictures). The substrate 210, the lead frame 220, and the two semiconductor wafers 230 and 240 are covered with a gel 250, wherein the outer legs of the plurality of leads 22 2 of the lead frame 2 20 extend outward from the sealing gel 2 50 Used for electrical communication with the outside world. Please refer to the second and third drawings again. The substrate 2 10 is made of a non-conductive material [such as FR-4 glass-epoxy or polyimide]. The lead frame 220 is preferably made of copper, iron, nickel or an alloy thereof. In addition, the plurality of wires 222 may be plated with a highly conductive material such as silver, copper, gold or palladium. The material of the sealing compound 250 is an insulating material, and a preferred molding compound is CEL-9200XU plastic provided by Hitachi Chemical Company. Please refer to the fourth figure again, the two semiconductor wafers 2 3 0, 2 4 0

P43256 1 V. Description of the invention (6) The bumps 232 and 242 are provided on the wafer pads (not shown in the figure) to connect the internal circuits. The metal bumps 232 and 2 42 can be formed by a conventional C4 (Controlled Collapse Chip Connection) process. The metal bumps 232 and 242 are preferably stud bumps formed by a conventional wire bonding technique.

It is known that the anisotropic adhesive suitable for forming the anisotropic conductive adhesive layers 234 and 244 is a "z-axis anisotropic adhesive", which is filled with low-concentration conductive particles 2 4 6 (refer to the fourth圊) and make them not contact each other in the X y plane. Therefore, compressing the substance in the z direction will establish a conductive path. The "z-axis anisotropic glue" can be a sticky paste or a film. The two (paste or film) "z-axis anisotropic adhesives" can be thermoplastic or thermoset. Thermoplastic anisotropic rubber is heated and softened before being used for cooling and solidification. The thermosetting anisotropic adhesive needs to be heated at 100-300 ° C for several minutes to one hour or more to cure it. D The wafers 330 and 340 used are the second best according to the present invention. Top view of the multi-chip package structure 300 of the embodiment after the sealing compound is removed. The multi-chip package structure 300 is the same as the multi-chip package structure 100 in the second and third diagrams except that the two wafers 33 0, 3 40, and 3 32, 342 replace the chips 23 0, 240. . It can be understood that the substrate used in the multi-chip package structure 300 includes a circuit layout including pins and 332, 342. The multi-chip package structure according to the present invention is designed. The connection is through the anisotropic conductive adhesive layer, so the package is thick

432561 V. Description of the invention (7) The degree can be reduced to about one millimeter, so that it can be manufactured by the process technology of the conventional thin and small outline package structure, thereby reducing the manufacturing cost. In addition, the multi-chip package structure according to the present invention does not require an expensive underfill (under ί i 1 1), so the manufacturing cost can be reduced. Β Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. For example, according to the multi-chip package structure of the present invention, although a multi-chip package structure including two or four semiconductor wafers is a preferred embodiment, it is understood that the multi-chip package structure according to the present invention may also include More than one semiconductor wafer. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

靥 4 32 5 6 1 VI. Patent Application Scope 1. A multi-chip package structure, which includes: a substrate with an upper surface and a lower surface. The upper and lower surfaces of the substrate are each provided with a plurality of crystal moon connections. A pad, the substrate is provided with a plurality of substrate pads electrically connected to the corresponding plurality of chip connection pads; a lead frame comprising a plurality of wires having an inner leg portion and an outer leg portion, and the inner leg portions of the plurality of leads are connected Fixed on the substrate and electrically connected to the corresponding substrate pad; two semiconductor wafers each having a plurality of metal bumps on its front side, and the front sides of the two semiconductor wafers are respectively fixed by an anisotropic conductive adhesive layer A plurality of metal bumps on the upper surface and lower surface of the substrate and connecting the semiconductor wafer to the plurality of wafer connection pads of the substrate; and a piece of gel covering the substrate, the lead frame, and the two semiconductor wafers, wherein the lead frame The outer legs of the plurality of wires extend outward from the sealing gel for electrical communication with the outside world. 2. The multi-chip package structure according to item 1 of the patent application scope, wherein the thickness of the package structure is less than 1 mm. Page 11