TW429346B - Multi-level memory device having an ECC circuit - Google Patents

Multi-level memory device having an ECC circuit

Info

Publication number
TW429346B
TW429346B TW088108483A TW88108483A TW429346B TW 429346 B TW429346 B TW 429346B TW 088108483 A TW088108483 A TW 088108483A TW 88108483 A TW88108483 A TW 88108483A TW 429346 B TW429346 B TW 429346B
Authority
TW
Taiwan
Prior art keywords
read
data
memory device
memory cells
level memory
Prior art date
Application number
TW088108483A
Other languages
English (en)
Inventor
Hiroyuki Matsubara
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW429346B publication Critical patent/TW429346B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
TW088108483A 1998-05-22 1999-05-21 Multi-level memory device having an ECC circuit TW429346B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10158561A JPH11339496A (ja) 1998-05-22 1998-05-22 多値セルのｅｃｃ回路

Publications (1)

Publication Number Publication Date
TW429346B true TW429346B (en) 2001-04-11

Family

ID=15674402

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088108483A TW429346B (en) 1998-05-22 1999-05-21 Multi-level memory device having an ECC circuit

Country Status (3)

Country Link
JP (1) JPH11339496A (zh)
KR (1) KR100293066B1 (zh)
TW (1) TW429346B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6990623B2 (en) 2001-05-16 2006-01-24 Fujitsu Limited Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function
JP4437519B2 (ja) * 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
US7966547B2 (en) * 2007-07-02 2011-06-21 International Business Machines Corporation Multi-bit error correction scheme in multi-level memory storage system
KR101506655B1 (ko) 2008-05-15 2015-03-30 삼성전자주식회사 메모리 장치 및 메모리 데이터 오류 관리 방법
CN103473146B (zh) 2012-06-06 2017-04-19 慧荣科技股份有限公司 存储器控制方法、存储器控制器以及电子装置
CN104794019B (zh) * 2015-04-17 2017-12-05 深圳市江波龙电子有限公司 一种嵌入式存储器的数据保护方法及装置

Also Published As

Publication number Publication date
KR100293066B1 (ko) 2001-06-15
JPH11339496A (ja) 1999-12-10
KR19990088497A (ko) 1999-12-27

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees