TW393769B - A DRAM cell structure and method serving the function of charging bipolar amplification - Google Patents

Abstract

A dram cell structure having charge amplification is disclosed. The DRAM cell has a capacitor to store an electrical charge. The DRAM cell further has a MOS transistor. The gate of the MOS transistor is coupled to a word line control to activate and deactivate the MOS transistor. The drain MOS transistor is coupled to one plate of the capacitor. The DRAM cell has a bipolar transistor to amplify the electrical charge stored on the capacitor. The bipolar transistor has a base that is the source for the MOS transistor. The base of the bipolar transistor is formed by masking and implanting a material of the first conductivity type adjacent to the gate to form the base. The collector of the bipolar transistor is the semiconductor substrate. The bipolar transistor has an emitter coupled to a bit-lines control which when activated will sense the charge amplified by the bipolar transistor. The emitter is formed by masking and implanting a material of the second conductivity type within the material of the first conductivity type. The emitter is implanting to ensure a large overlap of the gate of the emitter. The overlap of the gate of the emitter will ensure generation of gate induced drain leakage current to discharge the storage capacitor during writing of a logical ""0"" to the storage capacitor.

Description

A7 B7 V. Description of the Invention (/) Background of the Invention The present invention relates to a dynamic random access memory (DRAM). More specifically, it relates to the structure and function of the charge amplification function of the dynamic random access memory (DRAM). Production method. Description of Related Art In this technology, the structures and manufacturing methods of dynamic random access memory (DRAM) cells and dynamic random access memory (DRAM) arrays are well known. In the prior art, a typical cell structure of a high-density dynamic random access memory (DRAM), as shown in FIG. 1a, is a transistor M11 for switching charge and a storage capacitor C15 for storing charge. Composed of. As shown in FIG. 1b, the transistor M110 is an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) manufactured in a triple-well region. A deep N-wel 1 35 is formed in the p-type substrate 30. The region of the deep n-type well 35 is formed by the opening of insulation formed by local oxidation of silicon substrate (LOCOS). In the deep n-type well 35, a shallower P-type well 40 will be formed. The gate 60 of the n-type metal-oxide-semiconductor half-field-effect transistor Ml 10 will be formed using a conductive material, such as polycrystalline silicon, stacked on the insulating gate oxide layer 55, and is used to define the drain of the n-type metal-oxide-semiconductor half-field effect transistor Ml 10 The channel area between the electrode 50 and the source electrode 80. The capacitor C 15 is formed by placing a conductive metal on the dielectric 70 stacked on the n + drain 80 of the transistor M10 and connected to the substrate bias voltage source Vs s 75. Capacitor C 15 is shown. The special structure of capacitor C 15 is well known and described by B. El-Kareh et al., "The Evolution Of DRAM Cell Technology", Solid This paper size applies to the Chinese national standard (CNS> A4 size (21〇 > < 29)) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -n > ^ 1 ^ (·. -a-il ^ in · * ———— tm i — HI 1 ^ 1 In ----mhs_l 1 ^ 1 —-It m ^^ 1 1 ^ 1 Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperative A7 _B7 V. Description of invention (>)

State Technology, Mayl997, ρ · 89-101.) — In the text. In order to maintain a minimum storage capacitance of 30-40fF for a cell, dynamic random access memory cell structures have led to complex semiconductor processes to develop these structures. After inverting the relevant polarity and operating bias, it is of course possible to use the consistent dynamic random access memory cell of the p-type metal-oxide-semiconductor field-effect transistor (P-MOS). The deep n-type well 35 is normally biased to the power supply voltage Vcc (meaning the highest potential on the wafer), and the P-type well 40 is biased to the substrate's bias power source Vss 75 (meaning the lowest potential on the wafer). The bias power source Vs s 75 of the substrate can be biased below the ground point (minus potential), so that the leakage current through the transmission transistor M10 can be reduced. The presence of a charge in the storage capacitor C 15 represents a logical &quot; 1 &quot;, and the lack of charge represents a logical &quot; 0 &quot;. The storage capacitor C 15 is connected to the n + drain 80 of the transistor M10, and the other n + source 50 of the transistor M10 is connected to a bit-line that controls reading and writing of the dynamic random access memory cell. Vbit 25. The gate of the M0S transistor Ml 10 is connected to the word line Vword which controls the selection of the dynamic random access memory cell. As shown in FIG. 2, the dynamic random access memory cells Cell 11 200, Cell 12 205, Cell 21 210, Cell 22 215, are arranged in an array of columns (word lines WL0, WL1, WL2, and WL3) and rows (bit lines BL0 and BL1). A popular dynamic random access memory array is a folded bit line structure. Each pair of bit lines BL0 and BL1 is connected to a sense amplifier 220. One of the bit lines BL0 or BL1 is used as a reference bias, and the other bit line BL1 or BL0 is used as a bit line to sense when performing a read operation. . During the writing operation, the bit lines BL0 and BL1 are charged to Vcc while writing logic &quot; 0 &quot; when writing logic &quot; 0 &quot;. When this paper is compliant, the Chinese National Standard (CNS) A4 specification (210x29k centimeters) ^^--1 .---- C Pack ------- Order ----- 《眯-. (Please read the notes on the back before filling out this page) Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed A7 B7 V. Description of the invention (}) Charged to Vss. The selected word line WLO, WL1, WL2, or WL3 is charged to Vcc, so that all transistors connected to the same column are turned on and the capacitors of each cell are charged to Vc c or Vs s respectively to represent &quot; Γ or "&quot; information. Before the read operation starts, the bit lines BLO and BL1 are first charged to a voltage of Vcc / 2. When a cell is read, the selected word lines WLO, WL1, WL2, Or the voltage of WL3 rises to Vcc so that all transistors connected to word line WLO, WL1, WL2, or WL3 are turned on. "Each sense amplifier 220 detects the charge stored in capacitor C with respect to the relevant bit line BLO and BL1 voltages. (Meaning Vcc / 2). Because the memory cell capacitance 値 is smaller than the bit line capacitance 値 (<10%), the signal present at the input of the sense amplifier 220 is very small (~ 100-00mV). In all DRAM generations, the minimum storage capacitor must be 30-40fF as described above to maintain the characteristics of read operation. The demand for large storage capacitors in traditional single transistor cells has led to high and multilayer stacking Deep or deep Containers have become one of the main size limitations in dynamic random access memory technology. Therefore, reforms must be made to reduce the need for storage capacitors in dynamic random access memory cells. Single dynamic random access memory in the prior art A bipolar transistor is added to the cell, as shown in Figure 3a, which is used as a charge amplification of the dynamic random access memory cell. A dynamic random access memory cell with a charge amplification function, as shown in Figures 3a and 3b, is Published in U.S. Patent No. 4,677,589 (Haskell et al.) And U.S. Patent No. 5,363,325 (Sunouchi et al.). The structure of this unit is similar to that shown in Figures 1a and 1b. The n-type metal-oxide half field effect transistor Ml 300 enters or switches as a charge. The capacitor C 305 flows out. However, the transistor Q1 310 develops as a charge amplified by the capacitor-V · deaf 4 (please read the note on the back before filling this page)

This paper size applies the Chinese national standard (CNS &gt; A4 specification (210X29 mm) & A7 B7. 5. The signal of invention description (+), and allows less charge to be presented while still detecting logic &lt; Γ or Logic &quot; 0 &quot;. When the bit line Vbit 320 is connected to the Vcc voltage level, a logic &apos; write operation occurs. This will allow the p / formed by the emitter-base of the bipolar transistor Q1 310 The n junction 350 is turned on, so the capacitor C 305 is charged until the voltage is close to the power supply voltage Vcc. When the cell is to be written into logic &quot; 0 &quot;, the bipolar transistor Q1 310 will not be turned on and any capacitor C 305 will present The charge must be discharged from the capacitor C 315 through a parasitic path. This will cause the logic "0" write operation to be very slow. The structure of the bipolar transistor Q1 310 is to form an n-type metal-oxygen half field-effect transistor Ml In the N-type source region of 300,-is formed by diffusing the ρ + -type emitter 352. The bipolar transistor Q1 310 is therefore η-type metal-oxygen half field effect transistor Ml 300 as the ρ + -type emitter 352, N-type base 350 (also n-type metal-oxide half field-effect transistor) The source of the bulk Ml 300, and the fused well of the p-well 340 as the collector. &Quot; A Complementary Gain Cell Technology For Sub-lv Supply Dram's &quot;, Shukuuri et al., Digest of IEDM, p. 1006, 1992) and &quot; Semi-static complementary gain dynamic random access memory cell for ultra-low voltage operation &quot; (&quot; Super-Low-Voltage Operation Of Semi -Static Complementary Gain DRAM Memory Cell &quot;, Shukuri et al., Digest of VLSI Technology Symposium, p.23, 1993) describes a dynamic random access memory cell incorporating a charge amplification function. The complementary cell has an η Type metal oxide half field effect transistor and a rho type metal oxide half field effect transistor with a floating gate structure as a storage node. The floating gate stores the generation (please read the precautions on the back before filling this page). Order纸张 Printed paper size by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, using the Chinese National Standard (0 milk) 8 4 size (210 father 29 mm) A7 _B7____ V. Description of the invention (夂) The charge of table logic "Γ" or logic "0 &"; and causes the threshold voltage of P-type metal-oxide-semiconductor half-effect transistor to shift to allow logic "Γ" or logic &quot; 0 &quot; reading. &quot; SGT Gain Cell for Ultra High Density Dynamic Random Access Memory &quot; (&quot; A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Dram's &quot;, M. Terauchi et. A1 ., Digest of VLSI Technology Symposium, p.21, 1993)-This article published a wrap-around gate transistor gain unit. The wrap-around gate transistor unit has an n-type metal-oxide-semiconductor field-effect transistor, a junction field-effect transistor (JFET), and a charge storage capacitor. The beta charge storage capacitor is controlled by the gate of the junction field-effect transistor. form. &quot; A Novel Merged Gain Cell For Logic Compatible High Density DRAM's &quot;, M. Mukai et. al., Digest of VLSI Technology Symposium, P.155, 1997) —This article describes a p-type metal-oxide-semiconductor half-field-effect transistor, an n-type metal-oxide-semiconductor half-field-effect transistor, an n-type junction field-effect transistor, and a The second bit line is a fused dynamic random access memory cell. P-type metal-oxide-semiconductor half-field-effect transistors control charge transfer. Η-type metal-oxide-semiconductor half-field-effect transistors are used for charge storage and reading transistors, and n-type junction field-effect transistors are used to control read current. Charge storage occurs in the channel region of the n-type metal-oxide-semiconductor field-effect transistor.

The read and write operations of the dynamic random access memory cells of Shukuri et al., M. Terauchi et al., And M. Mukai et al. Are operated by separate transistors and bit lines in order to avoid the problems shown in Figures 3a and 3a above. 3b bipolar / gold paper size applies to Chinese national standards (CNS &gt; 8 4 specifications (210 × 29 · ^ cent)) (Please read the precautions on the back before filling this page) Printed by the cooperative A7 B7 Printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (t) The slow discharge rate of the oxygen semitransistor gain unit. US Patent No. 5066607 (Banerj ee) proposed a dual transistor gain type dynamics Random access memory unit. The dual transistor dynamic random access memory unit has a high-quality transmission transistor and a large capacitor storage unit. The gate of the gain transistor is connected between the storage unit and the transmission transistor for reading. The charge of the storage cell is amplified during operation. U.S. Patent No. 4,791,611 (Eldin et al.) Has published a device comprising a bipolar transistor, a junction field effect transistor, and a A capacitor memory unit. The capacitor includes a metal-oxide half field effect transistor operating in accumulation mode. The bipolar transistor controls the writing of the capacitor and the interface field effect transistor control data is read from the capacitor. Brief description of the invention The purpose of the present invention is to provide a dynamic random access memory cell structure with a charge amplification function. Another object of the present invention is to provide a dynamic random access memory cell structure with a fast write operation. In order to accomplish these and other purposes , DRAM cells are manufactured in a DRAM cell array on a semiconductor substrate. DRAM cells have a charge storage capacitor to store the charge of a bit that can represent digital data The storage capacitor has a first electrode plate and a second electrode plate connected to a bias voltage source of the substrate. The dynamic random access memory cell has a metal-oxide-semiconductor field-effect transistor. Control the action and non-action of this metal oxide half field effect transistor. Metal oxide half field effect The drain of the crystal is connected to the first electrode plate of the charge storage capacitor. After the well-known formation method of the well area and the local silicon dioxide (LOCOS) spacer, the semiconductor {Please read the precautions on the back before reading Fill in this page) Packing. The size of the paper is applicable to the Chinese national standard (CNS &gt; Λ4 specification (2 丨 0X29 ^ · centi) A7 _ B7_ V. Description of the invention (γ) A thin layer of sand dioxide is grown on the substrate. A gate oxide is formed. A mask is then deposited on the gate oxide and a conductive material, such as polycrystalline silicon, is etched to form the gate. The dynamic random access memory cell has a bipolar transistor to amplify the charge storage capacitor. Stored charge. This bipolar transistor has a base β that has the same function as the source of the metal-oxide half field effect transistor. The first ion is implanted with a photomask to form the base of the bipolar transistor. A first material of a first conductivity type is planted near the oxide to form a base. The base ion implantation has high energy and large angle to provide large current gain of the bipolar transistor. The collector of the bipolar transistor is formed from the base material of the semiconductor substrate and is connected to the substrate bias voltage source. The emitter of the bipolar transistor is connected to the bit line when it is operable to control the charge sensing amplified by the bipolar transistor. The emitter is formed by arranging a second ion implantation mask and implanting a second material of the second conductivity type in the first material of the first conductivity type and a region near the gate. The ion implantation of the second material of the second conductivity type has a high dose and a high tilt angle to ensure that the emitters overlap and cover the gates. The large overlap of the emitters on the gate is to ensure that the gate causes the drain leakage current in the area of the semiconductor wafer's overlap and coverage. This can provide the storage capacitor discharge when writing logic &quot; 0 &quot; to the storage capacitor. . Brief description of the legends Figures 1a and 1b are diagrammatic and sectional views, respectively, showing a conventional dynamic random access memory cell in the prior art. Figure 2 shows the foldable bit line dynamic random access memory node in the prior art (please read the precautions on the back before filling this page)-

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the 1T line [This paper size applies to the Chinese National Standard (CNS &gt; A4 specification (210X2 flutter mm)) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 Storage capacitors 35 Deep n-type wells 55 Gate oxide layer 80 Drain 75 Substrate bias voltage source 45 Field oxide layer 25 Word line A7 B7 V. Schematic diagram of the description of the invention (Figures 3a and 3b) A conventional dynamic random access memory unit with a charge amplifying function in the technology. Fig. 4 shows a cross-sectional view of a dynamic random access memory unit with a charge amplifying function in the present invention. Fig. 5 shows a charge amplifying function in the present invention. Schematic diagram of a dynamic random access memory cell array. Figures 6a and 6b show a schematic diagram of a dynamic random access memory cell with a charge amplification function in the present invention during a read operation. Figures 7a and 7b show the present invention. A circular diagram of a dynamic random access memory cell with a charge amplifying function in the invention during the write operation. Figures 7c and 7d show the charge in the invention Cross-sectional view and energy of a dynamic random access memory unit with amplifying function when writing to 0 Figure 8 shows the process flow of a dynamic random access memory unit with a charge amplifying function in the present invention. 10 Metal Oxide Half Field Effect Transistor 30 p-type substrate 40 p-type well 60 gate electrode 50 source electrode 70 dielectric 20-bit line This paper size is applicable to Chinese National Standard (CNS) Α4 specification (210X2 magic male director) • Wear '(Please read the note on the back before filling this page)

A7 B7 V. Description of Invention (Gas)

Ml η-type metal-oxide-semiconductor half-effect transistor Q1 bipolar ρηρ transistor 200, 205, 210, 215 dynamic random access memory cell 220 sense amplifier 300 metal-oxide-semiconductor half-effect transistor (please read the precautions on the back before filling (This page)-Installation. Order Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, 310 Bipolar Transistors 305 315 Storage Capacitors 330 ρ Type Substrates 335 Deep η Type Wells 340 ρ Type Wells / Collector 355 Gate Oxide 360 Gates 380 drain 350 source / N-type base 375 substrate bias voltage source 370 dielectric 345 field oxide layer 320 bit line 325 word line 350 ρ / η junction 352 ρ + type emitter 400 ρ type base Material 405 deep η-type well 410 ρ-type well / collector 440 gate oxide layer 460 gate 435 drain electrode 420 source / N-type base 430 insulation interval 455 dielectric 415 field oxide layer 452 P + type emitter 470 475 overlapping covers 465 channels 500, 505, 510, 515 array structure of dynamic random access memory cells 600 current Ibit 700 reverse channel 605 voltage Vc 710 electric field ε 750 electron e- 755 valence band Ev 760 conductive band Ec paper Standards apply Chinese national standards (&lt;:?) 8 4 Specifications (210 father 29 ^ cent) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ V. Description of the invention (π) Detailed description of the invention The structure of the dynamic random access memory unit of the present invention is shown in Figure 4, and A schematic diagram of its lumped components is shown in Figure 3a. The structure of the dynamic random access memory cell of the present invention has a "fusion type" transistor and a storage capacitor located at the front end of the triple well region as described above. &quot; Fusion type &quot; The transistor is similar to a typical n-type metal-oxide semi-transistor except that the bit line Vbi t320 is connected to a dual ion implanted p + emitter 425 / n-base-420, which can generate a parasitic Bipolar pnP transistor Q1 310. The parasitic bipolar pnp transistor Q1 310 is formed of a p + emitter 425, an n-type base 420, and a p-type well collector 410. The parasitic bipolar ρηρ transistor Q1 310 is fused with the η-type metal-oxide semiconductor transistor Ml 300 (the η-base electrode 420 is also the source of the η-type metal-oxide semiconductor transistor Ml 300). During read and write operations, the n-type base 420 is in a floating state. The storage capacitor C305 is connected to the n-type metal-oxide semiconductor Ml 300 drain. During the reading operation, the parasitic bipolar ρηρ transistor Q1 310 is used to amplify the charge stored in the capacitor, as if the charge was increased by a current gain (β) of the parasitic bipolar ρηρ transistor Q1 310. Therefore, the minimum unit capacitor required is greatly reduced. This will reduce the height of the above-mentioned stacked capacitors or the depth of trench capacitors. The structure and manufacturing process of the dynamic random access memory cell of the present invention can be understood from FIG. 4 and FIG. 8. The schematic diagram of its collection elements is again shown in Figure 3a. The structure of the dynamic random access memory cell of the present invention has a cell area, which is an area defined by an opening when the substrate is locally oxidized (LOCOS) isolated 801. The formation of the triple well region 802 begins by diffusing n-type material into the cell region to form a deep n-well region 405. Deep η-type well area 405 (Please read the precautions on the back before filling in this page) 丨 Binding and ordering Γ This paper size applies to China National Standard (CNS) Α4 specification (21〇 × 2 good mm) A7 B7 Intellectual property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of the People's Republic of China. 5. Description of the invention (&quot;) Connected to the power supply voltage source ^ in the later stage of the process, bias the deep η well area 405 to reduce the flow to the P-type substrate 4 〇〇 leakage current and noise coupling from peripheral circuits to dynamic random access memory cells. The P-type material is then diffused into the deep n-type well region 405 to form a P-type well region 410. The p-well area 410 is connected to the metal connected to the substrate bias voltage source Vss375 in a later process 806. The substrate bias voltage source Vss375 is generally the lowest voltage in the memory array. Biasing the P-type well region 410 to the substrate bias voltage source Vss375 further reduces the capacitance of the bit line and serves as the collector of the ρηρ bipolar transistor to be formed in the subsequent process. The additional n-type material will be diffused into the deep n-well region 405 to build a P-type metal-oxide semiconductor in the peripheral circuit. Accordingly, it seems that including this step makes the process description of the DRAM cell array more complete. The formation of the transistor 803 in the cell region starts by growing the gate oxide 440 in the region as the channel 465 of the n-type metal-oxide semiconductor transistor Ml 300 and forming a polycrystalline silicon gate 460 over the channel 465 in the gate region. The fusion-type ρηρ transistor Q1 310 is achieved by implanting an η-type material to form an η-type base 420. The ion implantation of the n-type base 420 is performed by implanting phosphorus (P31) atoms at a implantation energy between 50KeV and 10OKeV until the n-type base has an electron density of about 10E13 to 10E14 per cubic centimeter. The implantation energy of the η-type base must be high enough and the inclination angle of the implant must be large enough so that the η-type base is deeper than the P + emitter. This allows the fused ηp transistor Q1 310 to have a high current gain (々). Then, the P + emitter 425 of the fusion-type ρηρ transistor Q1 310 is continued to be formed by planting a ρ-type material on the η-type base 420 region. The implantation of the P + emitter 425 is implanted with the implantation energy of boron fluoride (BF2) in lOKeV until the P + emitter 425 has approximately 10E15 to 10E16 per cubic centimeter (please read the precautions on the back before filling this page) ) Binding. Order _ The size of the paper is applicable to the Chinese national standard (€?) 8 4 specifications (210 fathers and 2 marriages). The Intellectual Property Bureau of the Ministry of Economic Affairs, employee consumption cooperation Du printed A7 B7 V. Description of the invention (/ &gt; ) Hole density. The ion implantation of the P + emitter 425 requires a high dose and a large inclination angle to ensure that the P + emitter 425 and the hafnium region 460 overlap sufficiently to cover OV2 475. The n-type metal-oxide semiconductor transistor Ml 300 and the dynamic random access memory array peripheral control circuit have all the drains of the transistors through the P-type and n-type low doping concentration (ldd) masks and ion implantation And formed. The ldd spacer oxide is deposited and etched on the edge of the gate. The n + and p + masks and etching complete the formation of the n + drain of the n-type metal-oxide semiconductor transistor. The bit 804 forms a bit line Vbit320 and is connected to the p + emitter 425. The process of forming and connecting bit lines is well known in the art. In addition, 805 forms a storage capacitor C305. As shown in FIG. 4, the structure of the storage capacitor C305 has a dielectric layer overlying the drain of the n-type metal-oxide semiconductor Ml300. A metal layer is stacked on the dielectric layer and connected to the substrate 400 bias voltage source Vs s 375. This structure will be exemplified. The formation of the storage capacitor C305 as a stacked capacitor or a trench capacitor is well known in the art. Taking the trench capacitor as an example, it will be formed after the formation of the triple well region 802 and before the formation of the electric crystal 803. Finally, the back-end process 806 will provide contact points and interconnected metal wires to provide internal connections to the DRAM array, internal connections to peripheral control circuits, and to connect the DRAM array to external circuits. Required for contact pads. The storage capacitor C305 has been described as a standard stacked or trench capacitor. However, the charge amplification function of the ρηρ transistor allows the storage capacitor C305 to be reduced to a standard metal-oxide semiconductor transistor gate-to-source and gate-to-gate. Capacitance of the drain. This will simplify the manufacturing process to a standard CMOS logic process. From FIG. 5, the array structure of the dynamic random access memory cell in the present invention (please read the precautions on the back before filling this page)

Is. Installed.

.1T line · This paper size is applicable to China National Standard (CNS) A4 (210X297mm) Ά7 B7 V. Description of the invention (丨〉)

Cellll 500, Celll2 505, Cell21 510 &apos; Cell22 515, may be folded bit line arrays known in the art. As shown in FIG. 4, the gate of each cell n-type metal-oxide semiconductor transistor Ml 300 is connected to the word line Vword. The multiple word lines WL0, WL1, WL2, and WL3 will be connected to peripheral control circuits to select the dynamic random access memory cells Cellll 500, Celll2 505, Cell21 510, Cell22 515. The p + emitter 425 of the bipolar pnp transistor Q1 310 is connected to the bit lines BL0 and BL1 as described above. Bit lines BL0 and BL1 will be connected to peripheral control circuits to control the selection of rows WL0, WL1, WL2, and WL3 in the dynamic random access memory array. The complete dynamic random access memory cells Cellll 500, Celll2 505, Cell21 510, Cell22 515 will be placed in the deep n-well area 405. The bias of the deep n-type well area 405 will isolate the noise generated by the peripheral control circuit from the array of dynamic random access memory cells. In order to understand the dynamic random access memory of the present invention during the read operation, For unit operation, reference is now made to Figures 6a and 6b. As shown in Fig. 6a, when the logic "?" Is read, the storage capacitor C305 is charged to a voltage level of Vc 605 close to the power supply voltage source Vcc. The word line voltage Vword 325 is at the level of the power supply voltage source Vcc and the voltage level of the bit line Vbit 320 is first charged to Vcc / 2, which is half of the power supply voltage source level. When the word line voltage Vword 325 is at the level of the power supply voltage source Vcc, the n-type metal-oxide-semiconductor Ml 300 will be in the on state, so the voltage Vc605 existing on the storage capacitor C305 is placed at the base of the pnp transistor Q1 310 420 on. The pnp transistor Q1 310 will be in the non-conducting state, and no current Ibit 000 will flow through the bit line Vbit. This will be controlled by the peripheral located in the dynamic random access memory array (please read the note on the back before filling this page) 丨 Installation_

'1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. The paper size is applicable to China National Standard (CNS) 8-4 specifications (210 × 291 mm) A7 B7 V. Description of the invention (if) The sense amplifier of the circuit is detected as logic & quot Γ. Reference is now made to Figure 6b to understand the operation of the slave RAM read logic &quot; 0 &quot;. The voltage Vc605 on the storage capacitor C305 is close to 0V. Once again the word line voltage Vword 325 will be at a level close to the power supply voltage source Vcc. The voltage level of the bit line Vbit 320 is also charged to Vcc / 2, which is half of the power supply voltage source level. The n-type metal-oxide-semiconductor Ml 300 will be in an on state and the voltage Vc605 on the storage capacitor C305 will be placed on the base 420 of the pnp transistor Q1 310. pnp transistor Q1 310 will turn on the current Ibit 600 to the maximum achievable current level Imax »This bit line current level Ibit will represent the logic detected by the sense amplifier &quot; 0 &quot; 〇 Now refer to Figures 7a, 7b, 7c And 7d to understand the write operation from the dynamic random access memory cell. Fig. 7a shows the situation of the dynamic random access memory cell write logic &quot; Γ. The word line voltage Vword 325 will be set as the power supply voltage source Vcc to turn on the n-type metal-oxide semiconductor transistor Ml300. The voltage of the bit line Vbit 320 will also be set to the level of the power supply voltage source Vcc. If the storage capacitor C305 has been discharged close to the 0V level, the p / n interface of the emitter-base interface of the pnp transistor Q1 310 will become forward biased and charge the storage capacitor C305 close to the power supply voltage source Vcc. Level. However, 'if the storage capacitor C305 has been charged to the level of the power supply voltage source Vcc, it will not respond to this change. The operation of the read logic M1 &quot; logic &quot; 〇 &quot; and the write logic &quot; Γ of the dynamic random access memory cell of the present invention is not different from that shown in the prior art. The logic &quot; 0 &quot; writing action described below is different. Now refer to Figure 7d to understand the writing logic from the dynamic random access memory unit &quot; 0 &quot; (Please read the precautions on the back before filling out this page)-Binding-Order the paper printed by the Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs Standards are applicable to Chinese National Standard (CNS) A4 specifications (210 × 29ΤΪΪ) A7 B7___ V. Operation of the invention (&lt;). The word line voltage Vword 325 will be set as the power supply voltage source Vcc to make the n-type metal-oxide half-electricity The crystal Ml 300 is turned on. The voltage of the bit line Vbit 320 is set to 0V. Under this bias, the pnp transistor Q1 310 will be in the non-conducting state. If the storage capacitor C305 has been discharged to the 0V level Vc 605, This unit has been set to logic &quot; 〇 &quot; and no response is required. However, if the storage capacitor C305 is charged to a voltage level Vc 605 close to the power supply voltage source Vcc, the pnp transistor Q1 310 will be located at On state. In order to overcome the slow discharge of storage capacitor C305 due to leakage current in the prior art, a gate-induced drain leakage (GIDL) current will cause 7c and 7d to understand the gate-induced drain leakage (GIDL) effect. The overlapping portions of the gate on the n-type base 420 and p + emitter 425, 0V1 470 and 0V2 475, will allow electrons e- A current is generated on the surface of the P + emitter 425 and flows to the n-type base 420 through the channel 465 to discharge the storage capacitor C315. The electric field ε 710 generated by the word line voltage Vword 325 will cause the electrons to pass between the band and the band The penetration occurs at the interface of the P + emitter 425. The gate oxide 440 must be thin enough so that the vertical electric field ε 710 is large enough (&gt; 2 MeV / cm) to trigger the band-to-band penetration. This will cause and increase the junction leakage current to flow through the reversed biased P + emitter 425 and n-type base 420 diodes. Or as shown in Figure 7d, through the energy band-to-energy band penetration mechanism, ad valorem The electron e-750 generated by the electric band Εν 755 to the conductive band Ec 760 passes through the empty layer 715 on the surface of the P + emitter 425 and will flow in the region of the n-type base 420 and flow to the n-type gold through the reverse channel 700 Oxygen semi-transistor Ml 300 has a drain 435 to achieve the discharge of storage capacitor C315. Anyone familiar with the technology knows that the material Invert the type to use P-type gold (please read the precautions on the back before filling this page)---I fy, • (^^^ 1 ^^^ 1 In if a ^^ i · —l · _ HI ^^^ 1 .n equipment

-, 1T line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese national standards (CNS &gt; A4 size (210X291 ^ cent) A7 B7 V. Description of the invention (A) Oxygen semi-transistors and npn transistors The structure and operation of the present invention can be maintained by appropriately changing the bias power supply. Although the present invention specifically shows and describes the selected embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the present invention. The spirit and scope of the invention. (Please read the precautions on the back before filling out this page.)-Binding. Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with China National Standard (CNS) A4 specifications (210X2 «% • cents)

Claims (1)

A8 B8 C8 D8 * i »'· · &lt; · · · ···. 6. Scope of Patent Application (Amended Patent Application Model No. 870100530) (1) A method for manufacturing a plurality of dynamic random access memory cells, wherein each dynamic random access memory β cell has a first metal-oxide semi-transistor, a bipolar transistor, and a storage electrode. The aforementioned method The following steps are included: a) providing a semiconducting hip chip; b) selectively growing an isolation slaughter on the aforementioned semiconducting wafer to define the aforementioned dynamic dynamic access memory on the semiconductor wafer Body unit; c) forming a plurality of deep well regions of the first conductivity type in the area defined by the aforementioned isolation 1E; d) forming a plurality of wells of the first conductivity type and the second conductivity type in the plurality of deep wells B described above e) forming the aforesaid metal-oxide semi-electrode sauce and the aforesaid bipolar transistor by the following steps: depositing and etching the gate oxide on a plurality of well regions of the second conductivity type on the aforementioned semiconductor wafer, On the aforementioned semiconductor crystal Sink up, mask, and etch out the first polycrystalline silicon layer to form the gate of each of the dynamic random access memory Si-cell metal-oxide semi-electric hips, and place the first ion: and oxidize the aforementioned gate A first material is implanted near the object to form the base of the aforementioned bipolar transistor hip, wherein the ion implantation has an energy ratio of 1: 1 and a large angle, and a second ion implantation photomask is placed in the The first material of the aforementioned first conductivity type and the second material of the second conductivity type are implanted near the aforementioned gate oxide to form the former paper size applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the precautions on the back before filling out this page) Order: --r ------ line The first A8 B8 C8 D8 * i »'· · &lt; · · · ··· ...... 6. Scope of Patent Application (Case No. 870105030) ) 1. A manufacturing method of many dynamic random access memory cells, in which each dynamic random access memory β sheet Each has a first metal-oxide semiconductor transistor, a bipolar transistor, and a storage electrode. The foregoing method includes the following steps: a) providing a semiconductor hip chip; b) on the semiconductor chip Selectively grow an isolation barrier to define the aforementioned plurality of dynamic on-access memory cells on the aforementioned semiconductor wafer; c) form a plurality of first conductive types within the area defined by the aforementioned isolation 1E Deep well area; d) forming a plurality of wells of the first conductive type and the second conductive type in the plurality of deep wells B described above; e) forming the aforementioned gold-oxygen semi-electric crystal sauce and the aforementioned bipolar transistor hip by the following steps : Depositing and etching gate oxide on a plurality of well regions of the second conductivity type on the aforementioned semiconductor wafer, sinking, masking, and etching the first polycrystalline silicon layer on the aforementioned semiconductor wafer to form each A dynamic random access memory gate of the metal oxide semi-transistor of the Yi Si unit, the first ion is placed: and a first conductive material is implanted near the aforementioned gate oxide to form the aforementioned bipolar transistor Hip base , Wherein the ion implantation has a high energy ratio 1: and a large angle, a second ion implantation photomask is placed and implanted near the first material of the aforementioned first conductive type and the aforementioned gate oxide The second material of the second conductivity type is formed to the size of the paper before the application of Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order:- r ------ line Λ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on the surface of the ion implant mask. The first printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, A8 B8 C8 D8. The emitter of a bipolar transistor, wherein the ion implantation of the second material of the second conductive type has a high agent 1: to ensure that the aforementioned emitter and the aforementioned gate have a large area of overlapping coverage and placement Ion implanted photomask and implanted the first conductive type of low doping concentration drain to form a dynamic random access memory cell metal-oxide semiconductor transistor Conductive type drain and source electrodes, with ion cloth A photoresist is planted and a second conductive type low doping concentration drain and source is formed to form a second conductive type drain and source of the peripheral metal-oxide semiconductor, and the insulation is deposited and etched back. Materials to form a low-doping concentration drain electrode, and an ion implantation mask and then a first conductive type material and a second conductive type material to complete the dynamic random access memory cell gold Formation of the drain electrode of the oxygen semiconductor and the drain electrode of the first and second conductive types of the surrounding gold-oxygen semiconductor; 0 A plurality of bit lines are formed on the aforementioned semiconductor wafer, of which a single A bit line is connected to the emitter of the bipolar transistor of each DRAM cell in each poly-RAM memory cell: g) Electrical hybrids are formed in many dynamic memory cells And h) a Jin-Jin interconnector to connect the poly-dynamic random access memory hip unit as a memory hip array and connect the memory array to a peripheral circuit formed by the first and second peripheral metal-oxide semiconductor hips 2 .As one of the scope of patent application A method for manufacturing a plurality of dynamic random access memory cells, wherein when the aforementioned bipolar transistor is formed, the ion implantation used to form the aforementioned base has an energy setting and a large angle to provide a large current increase. ys). (Please read the precautions on the back before filling in this page) SJ · —— &quot; ------ line—f-· 1 n 1 nn ti amaw Mmaw Mi This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A8B8C8D8 6. Scope of patent application (please read the precautions on the back before filling this page) As in the patent application scope of item 1, a method of manufacturing a large number of dynamic random access memory hundred million box units, where When forming the aforementioned bipolar transistor β, the ion used to form the aforementioned emitter is implanted with a material of the second conductive type to ensure that the aforementioned emitter and gate have a large area. Overlapping. 4. A method for manufacturing a plurality of dynamic random access memory cells according to item 3 of the patent application, wherein the large area of the aforementioned emitter and the aforementioned gate is overlapped to ensure that The gate-induced drain leakage current is generated in the aforementioned overlapped coverage area, so that when the &quot; 〇 &quot; is written to the aforementioned storage capacitor, the aforementioned amount of electricity is lost. 1. A method for manufacturing a plurality of dynamic random access memory sauce cells according to item 1 of the scope of patent application, wherein when forming the aforementioned bipolar transistor, the ion implantation used to form the aforementioned base electrode The placement range is about SOKeV to about 10OKeV by implanting phosphorus atoms (P31), and the concentration in the base is about 10E13 to 10E14 electrons per cubic centimeter. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. For example, a method for manufacturing a plurality of dynamic random access memory cells in the scope of patent application, wherein said bipolar transistor is used to form a bipolar transistor Although the above-mentioned ionized ion cloth is achieved by the energy range of about 箩 OKeV, the fluorinated ionization is achieved. »To the aforementioned emitter, the degree of electricity in China and Australia reaches about 10E15 to 10E16 holes per cubic centimeter." 7. 1 of a method for manufacturing a plurality of dynamic random access memory hip units *, wherein the storage capacitor is a capacitor formed from a stack type capacitor, a channel capacitor, and the first dynamic random access memory unit. The size of the paper between the gate and source of the two metal-oxide semi-transistor is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) A8 B8 C8 D8 Selected. 8.—A device for making a single dynamic aging memory cell in a memory sauce cell array on a semi-conductive saucer, including: a) a storage for storing electric charge representing digital data bits The capacitor has a first electrode plate and a second electrode plate connected to the bias voltage source of the substrate; W—a metal oxide semi-electric crystal sauce, which includes a gate connected to control the operation of the foregoing metal oxide semi-transistor or not. The zigzag line, the drain electrode is connected to the first electrode plate of the storage capacitor, and the source electrode, wherein the foregoing gate electrode is formed by: sinking on the aforementioned semiconductor wafer, light army, and etching an insulating layer to Forming a gate oxide between the aforementioned drain and the aforementioned source, and immersing, etching, and etching a conductive material such as polycrystalline silicon on the aforementioned gate oxide to form the aforementioned gate; 0—a bipolar transistor «, used to amplify the charge stored in the aforementioned instrument storage capacitor, and has @ 81 for the aforementioned function of the source of the metal-oxide semiconductor transistor» 81 * and formed in the following steps: Place the first Ion implantation photomask The first material of the first conductive type is implanted near the foregoing gate oxide to form the aforementioned base, wherein the ion implantation has a high energy placement and a large angle, and is composed of the volume of the aforementioned semiconductor substrate The collector formed by the material is connected to the substrate bias power source and the emitter connected to the bit line. When the bit line operates, the charge amplified by the aforementioned bipolar transistor can be detected. The following steps are formed: This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * »ij .rll · — I 111.I — ΙΓΙ Printed A8, B8, C8, D8 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the scope of the patent application is to place a second ion implanted photomask and place it in the first of the aforementioned first conductive types. A second material of the second conductivity type is implanted near the foregoing gate oxide and the foregoing gate oxide to form the foregoing emitter, wherein the second conductivity type is the ion cloth of the second material Gao gate having the dose to ensure the ownership of very large classes and the domain of the heavy ft drum. 9. A device for manufacturing a single dynamic random access memory cell in a dynamic random access memory value cell array on a half-lead hip substrate according to item 8 of the scope of patent application, wherein said bipolar In the case of a transistor, the ion implant used to form the aforementioned base has a chirp energy and a large angle to provide a large current gain. 10. The device of a single imaginary random access memory cell in a dynamic random access memory cell array manufactured on a half-lead substrate, as described in item 8 of the scope of patent application, wherein said bipolar When the transistor is used, the ionic implant used to form the aforementioned emitter is implanted with a second conductive type of material, to ensure that the aforementioned emitter and the aforementioned gate are covered with a large area. 11. A device for manufacturing a single dynamic random access memory cell in a dynamic random access memory cell array on a semiconductor substrate according to item 10 of the patent application, wherein the aforementioned emitter and the aforementioned The overlapping coverage of the large gate area of the gate is to ensure that a gate-induced drain leakage current is generated in the aforementioned recapture area of the aforementioned semiconductor wafer, so that it is difficult to write &quot; 0 &quot; to the aforementioned storage capacitor. Miscellaneous electric power. 12. A device of a single dynamic random access memory beta cell in a dynamic random access memory beta cell array manufactured on a half-guide substrate, such as item 8 of the patent application, wherein said bipolar When the transistor is prepared, it is used to shape 24 (please read the precautions on the back before filling this page) A Order -----_------ line — {---- II ,,-This paper The standard is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A8B8C8D8 /. The patent application for the ion implantation in the aforementioned base is based on the ability of 1: 1:10 OKeV to approximately 10 OKeV Atomic (P31), to reach the aforementioned base with a concentration of about 10E13 to 10E14 electrons per cubic centimeter "13. For example, a dynamic random access memory fabricated on a semiconductor substrate in the scope of patent application No. 8 镫A device for accessing a memory cell by a single vision machine in a cell array, wherein the ion implantation used to form the aforementioned emitter when forming the aforementioned bipolar transistor is based on the ability of Dong Fan to draw approximately lOKeV Plant boron fluoride (BF2) until the concentration in the emitter is about 10E1 to 10E15 square centimeters Lai hole and reach. 14. A device of a single dynamic random access memory hip unit in a dynamic random access memory cell array manufactured on a semiconductor substrate according to item 8 of the scope of patent application, wherein said storage capacitor is a stack capacitor The drain capacitor is selected from the group consisting of a gate and source and drain capacitors of a second metal-oxide-semiconductor transistor formed in the aforementioned dynamic random access memory cell. (Please read the notes on the back before filling out this page) Λ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 25 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)-~ n II ( I in ϋ ϋ I in 1 nnn IIIII ϋ II nn I