TW202217994A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202217994A
TW202217994A TW110130418A TW110130418A TW202217994A TW 202217994 A TW202217994 A TW 202217994A TW 110130418 A TW110130418 A TW 110130418A TW 110130418 A TW110130418 A TW 110130418A TW 202217994 A TW202217994 A TW 202217994A
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Taiwan
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source
layer
fin structure
fin
drain
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TW110130418A
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楊智銓
林京毅
蘇信文
林士豪
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台灣積體電路製造股份有限公司
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Abstract

方法和裝置提供設置在基底上的第一鰭片結構、第二鰭片結構和第三鰭片結構。介電鰭片係形成在第一鰭片結構與第二鰭片結構之間，且導線係形成在第二鰭片結構與第三鰭片結構之間。

Description

半導體裝置
本發明係有關於一種半導體裝置及其製造方法，特別是有關於具有嵌入式導線的半導體裝置及其製造方法。
半導體積體電路(integrated circuit，IC)產業已歷經了指數式成長。積體電路材料及設計之技術的進步造成積體電路世代的產生，每一世代的電路比前一世代更小且更複雜。在積體電路的發展過程中，通常增加了功能密度(即每晶片面積中互連的裝置數量)，而降低了幾何尺寸(即使用製程所能創造的最小組件(或線路))。這種微縮化製程一般可藉由增加生產效率及降低相關成本以提供許多利益。這樣的微縮化也增加了積體電路之生產和製程的複雜度。
舉例而言，隨著積體電路(IC)技術朝向更小的技術節點發展，開始導入多閘極裝置以增加閘極-通道耦合、降低關閉狀態(off-state)的電流，以及降低短通道效應(short-channel effect，SCE)。通常將多閘極裝置視作具有閘極結構或其部分設置於通道區之多側上的裝置。鰭式場效電晶體(fin-like field effect transistor，FinFET)是多閘極裝置的一個範例，其已成為在高效能與低漏電的應用中常見且有潛力的候選。鰭式場效電晶體具有由閘極包覆多側的抬升通道(例如閘極包覆從基底延伸之半導體材料的「鰭片(fin)」的頂部及側壁)。另一種多閘極裝置類型包含環繞式閘極電晶體(surrounding gate transistor，SGT)或全繞式閘極(gate-all-around，GAA)電晶體，其閘極結構環繞通道區。全繞式閘極電晶體的通道區可由奈米線(nanowire)、奈米片(nanosheet)或其他奈米結構形成，因此，可將此電晶體稱為奈米線電晶體或奈米片電晶體。
縮小裝置尺寸的一項挑戰在於經由縮小尺寸之部件仍能維持足夠的效能。舉例而言，隨著製程規模的縮小，互連線路變得越來越小。較小的互連線路會表現出較大的電阻，這會對裝置效能產生衝擊。因此，儘管形成裝置的傳統方法對於它們原先預期的目標通常已足夠，但它們仍未在各方面都完全令人滿意。
在一示範態樣中，本發明實施例係關於半導體裝置。裝置包含從基底延伸的第一鰭片結構、第二鰭片結構和第三鰭片結構。第一源極/汲極部件係形成在第一鰭片結構上。第二源極/汲極部件係形成在第二鰭片結構上。第三源極/汲極部件係形成在第三鰭片結構上。介電分離結構在第一源極/汲極部件與第二源極/汲極部件之間延伸。導線係設置在第二源極/汲極部件與第三源極/汲極部件之間。
在另一較廣的實施例中，半導體裝置包含具有第一電晶體和第二電晶體的記憶體單元。第一電晶體的第一源極/汲極部件係形成在凹陷的第一鰭片結構上。第二電晶體的第二源極/汲極部件係形成在凹陷的第二鰭片結構上。電源線係設置在第一源極/汲極部件與第二源極/汲極部件之間。
在此處討論的另一實施例中提供方法。方法包含提供設置在基底上的第一鰭片結構、第二鰭片結構和第三鰭片結構。在第一鰭片結構與第二鰭片結構之間形成介電鰭片。在第二鰭片結構與第三鰭片結構之間形成導線。方法包含形成延伸至第二鰭片結構、導線和第三鰭片結構上的閘極結構。將第一鰭片結構、第二鰭片結構和第三鰭片結構各自的源極/汲極區凹陷。分別在第一鰭片結構、第二鰭片結構和第三鰭片結構上磊晶成長第一源極/汲極部件、第二源極/汲極部件和第三源極/汲極部件。
以下揭露提供了許多不同的實施例或範例，用於實施提供之主題的不同部件(feature)。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明的實施例。舉例而言，以下敘述中提及第一部件形成於第二部件上或上方，可能包含第一與第二部件直接接觸的實施例，也可能包含額外的部件形成於第一與第二部件之間，使得第一與第二部件不直接接觸的實施例。此外，本發明實施例在各種範例中可能重複參考數字及/或字母，此重複是為了簡化和清楚的目的，並非在討論的各種實施例及/或組態之間指定其關係。
再者，在此可使用空間相對用詞，例如「在……下方」、「在……下」、「下方的」、「在……上」、「上方的」及類似的用詞以助於描述圖中所示之其中一個元件或部件相對於另一(些)元件或部件之間的關係。這些空間相對用詞係用以涵蓋圖式所描繪的方向以外，使用中或操作中之裝置的不同方向。設備可能被轉向(旋轉90度或其他方向)，且可與其相應地解釋在此使用之空間相對描述。再者，除非另有說明，當用「約」、「大約」及相似的用詞來描述一個數字或一個數字範圍時，所述用詞涵蓋在所述數字之+/- 10%內的數字。舉例而言，用詞「約5 nm」可涵蓋4.5 nm至5.5 nm的尺寸範圍。
如上所述，多閘極電晶體也可指鰭式場效電晶體(FinFET)、環繞式閘極電晶體(SGT)、全繞式閘極(GAA)電晶體、奈米片電晶體或奈米線電晶體。它們可為N型或P型。儘管在此討論的實施方式為全繞式閘極電晶體，但重要的是，要注意本發明實施例也適用於其他裝置組態，包含但不限於鰭式場效電晶體裝置。舉例而言，以下討論的鰭片結構212係指具有通道和犧牲層交替之堆疊的全繞式閘極裝置，也可為鰭式場效電晶體裝置的鰭片結構(例如矽鰭片)。
本發明實施例大體上關於提供互連線路在主動區之間的區域且延伸至基底上的裝置和方法，互連線路例如在源極/汲極部件之間並與源極/汲極部件共平面，以及在閘極結構之間及/或與閘極結構共平面。這是指將導線嵌入於裝置中。
本發明實施例認為當裝置縮小時，傳送訊號及/或電力往返電晶體或前述之組件的金屬化層變得越來越小，因此增加電阻。對於一些裝置類型，這種增加的電阻有害於裝置效能。舉例而言，縮小靜態隨機存取記憶體(static random access memory；SRAM)單元(cell)意味著增加SRAM電源線的電阻。對於SRAM裝置，Vccmin為維持SRAM運作所需的最低電壓。隨著金屬化層(包含傳送Vcc之電源線)的縮小，線路的電阻也隨之增加。由於IR壓降較大的緣故，如此增加的電阻可能衝擊電壓Vcc。可能因此增加Vccmin及/或使SRAM的運作(例如讀取或寫入)失敗。舉例而言，一些實施例中，離單元最遠的金屬化線路可能大幅下降，導致SRAM的運作(例如寫入)失敗。
本發明實施例的製程和結構能夠改善裝置結構的效能，例如包含縮小及/或改善標準單元之效能。如上所討論，在此討論的某些實施例係以全繞式閘極(GAA)電晶體的方式呈現，然而，可理解在此討論的方法和結構也可應用於其他結構，例如鰭式場效電晶體的鰭片結構。再者，以下討論的內容為本發明實施例關於SRAM裝置之某些態樣的實施方式(例如見第15圖)，然而，其他裝置類型也可從本發明實施例的態樣中受益。
本文討論之嵌入式金屬化線路適合傳送電力或其他訊號往返基底上的裝置，且金屬化線路可形成於基底上的一或多個位置。在一些以下討論的實施例中，形成金屬化線路使得在電晶體的源極/汲極區形成裝置的接觸。在一些以下討論的實施例中，形成金屬化線路使得在IC的虛設區中形成閘極結構或相鄰於閘極結構的接觸。虛設區中的閘極結構可提供對金屬化線路之連接的傳導路徑，但並非功能性電晶體的功能性閘極。如此對於電晶體之源極/汲極和虛設裝置之閘極的配置可一起用於佈線橫跨晶圓的單一金屬化線路(例如Vdd或Vss)，或用於佈線橫跨晶圓的這些金屬化線路中的單一者以及此單一金屬化線路的多個接觸。換言之，可獨立實施在源極/汲極部件之間且與源極/汲極部件耦接的金屬化線路。可獨立實施在虛設區中閘極結構之間且與閘極結構耦接的金屬化線路。
現在參見第1圖，顯示製造半導體裝置200的方法100，半導體裝置200的部分剖面示意圖顯示於第2、3、4、5、6、7、8、9A、10B、11、12A、12B、13A、13C、15A和15B圖中，半導體裝置200的部分透視圖顯示於第10A、13B和14A圖中，且與半導體裝置200相關的佈局部分俯視圖顯示於第9B、10C、14B和15C圖中。方法100僅為例示，並非用以將本發明實施例限定於本文明確顯示出的內容。可在方法100的前、中、後提供額外的步驟，且可取代、消除或移動方法之額外實施例中的一些敘述的步驟。為了簡化，本文並未詳細描述所有的步驟。除了在本發明實施例之圖式中明確顯示出的內容之外，半導體裝置200可包含額外的電晶體、雙極性接面電晶體、電阻、電容、二極體、熔絲等。除非另有說明或描述，否則本發明實施例通篇使用相似的參考數字來表示相似的部件。
方法100始於方框102，在此步驟中接收基底。參見第2圖的範例，提供基底202。在一實施例中，基底202可為矽(Si)基底。一些其他的實施例中，基底202可包含其他半導體，例如鍺(Ge)、矽鍺(SiGe)或III-V族半導體材料。III-V族半導體材料的範例可包含砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)、磷化鎵砷(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、磷化鎵銦(GaInP)和砷化銦鎵(InGaAs)。基底202也可包含絕緣層，例如氧化矽層，以具有絕緣層上覆矽(silicon-on-insulator，SOI)結構或絕緣層上覆鍺(germanium-on-insulator，GOI)結構。一些實施例中，基底202可包含一或多個井區，例如摻雜N型摻質(即磷(P)或砷(As))的N型井區或摻雜P型摻質(即硼(B))的P型井區，以形成不同類型的裝置。可使用離子植入或熱擴散以形成N型井區和P型井區的摻雜。
依然參見第2圖，可在基底202上設置堆疊204。堆疊204可包含由複數個犧牲層206交錯的複數個通道層208。通道層208和犧牲層206可具有不同的半導體成分。犧牲層206和通道層208係一個接著一個交替沉積以形成堆疊204。一些實施方式中，通道層208係由矽(Si)形成，且犧牲層206係由矽鍺(SiGe)形成。一些實施方式中，犧牲層206中額外的鍺含量得以在實質上不損害通道層208的情況下，選擇性地移除或凹陷犧牲層206，如下所討論。一些實施例中，可使用磊晶製程來沉積材料，以形成包含犧牲層206和通道層208的堆疊204。示範的技術包含化學氣相沉積(chemical vapor deposition；CVD)沉積技術(例如氣相磊晶(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuum CVD；UHV-CVD)、分子束磊晶(molecular beam epitaxy；MBE)及/或其他合適的製程，但不限於此。注意在第2圖中顯示四(4)層犧牲層206和三(3)層通道層208交替且垂直地配置。然而，這僅出於說明之目的，並非用以限定申請專利範圍中具體記載的內容。層的數量取決於半導體裝置200之通道構件的期望數量。一些實施例中，通道層208的數量在2與10之間。為了圖案化之目的，可在堆疊204上設置硬遮罩層210。硬遮罩層210可為單層或多層。在一實施方式中，硬遮罩層210包含氧化矽層和氮化矽層。
方法100接著進行方框104，在此步驟中形成複數個鰭片結構。一些實施方式中，形成介於鰭片結構之間的隔離部件，例如在鰭片結構的下部分。每一個鰭片結構定義在基底上的一個主動區。參見第3圖的範例，形成鰭片結構212。儘管顯示了五(5)個鰭片結構，但這僅出於說明之目的，並非用以限定申請專利範圍中具體記載的內容。可使用包含光學微影和蝕刻製程之合適的製程來製造鰭片結構212。光學微影製程可包含在基底202上形成光阻層，將光阻層對圖案進行曝光，實施曝光後烘烤(post-exposure bake)製程，以及對光阻層進行顯影以形成包含光阻層的遮罩元件。一些實施例中，遮罩元件更包含硬遮罩層210。一些實施例中，可使用電子束(e-beam)微影製程對光阻層進行圖案化以形成遮罩元件。隨著技術節點的降低，可使用包含雙重圖案化或多重圖案化製程之合適的製程以將鰭片結構212圖案化。一般而言，雙重圖案化或多重圖案化製程結合光學微影和自對準製程，得以形成例如具有間距小於使用單一、直接地光學微影製程可獲得的間距的圖案。舉例而言，在一實施例中，在基底上形成材料層，並使用光學微影製程將材料層圖案化。使用自對準製程在圖案化的材料層旁形成間隙物。然後移除材料層，並使用剩餘的間隙物或心軸(mandrel)將鰭片結構圖案化。
上述之遮罩元件可接著在蝕刻鰭片結構212時用於保護基底202及/或堆疊204的區域。可使用乾式蝕刻(例如化學氧化物移除)、濕式蝕刻、反應式離子蝕刻(reactive ion etching，RIE)及/或其他合適的製程來蝕刻凹陷。也可使用方法的許多其他實施例以在基底202上形成鰭片結構212。
鰭片結構212在基底202上垂直地(Y方向)延伸，且其長度從基底202沿著Z方向延伸(例如延伸進入第3圖的頁面中)。每一個鰭片結構212包含從基底202形成的基座部分，標示為202A，以及從堆疊204的材料形成的上覆部分。每一個鰭片結構212與鄰近的鰭片結構在X方向上間隔一段距離。在一實施例中，第一個鰭片212-1是用以形成NFET裝置，接下來的兩個鰭片212-2和212-3是用以形成PFET裝置，以及隨後的兩個鰭片212-4和212-5是用以形成NFET裝置。然而，其他配置也是可能的。
繼續參見第3圖的範例，形成介於鰭片結構212之間的隔離部件203，也稱為淺溝槽隔離(shallow trench isolation；STI)部件。隔離部件203介於鰭片結構的底部區域之間。隔離部件203可包含先在基底202上沉積的介電材料，並以介電材料填充鰭片結構212之間的溝槽。一些實施例中，介電材料可包含SiO 2、氮化矽、氮氧化矽、摻氟矽酸鹽玻璃(fluorine-doped silicate glass；FSG)、低介電常數(low-k)的介電質、前述之組合及/或其他本技術領域中已知合適的材料。在各種範例中，介電材料的沉積可藉由CVD製程、次大氣壓CVD(subatmospheric CVD；SACVD)製程、流動式CVD製程、原子層沉積(atomic layer deposition；ALD)製程、物理氣相沉積(physical vapor deposition；PVD)製程或其他合適的製程。隔離部件203可包含多層結構。在沉積隔離部件203的絕緣材料之後，可實施化學機械平坦化製程以及隨後的回蝕刻(etch back)製程，以提供在隔離部件203頂面上延伸之鰭片結構212的上部分。一些實施例中，可在基底上及/或在基底內，額外地或替代地形成場氧化物(field oxide)、局部矽氧化(local oxidation of silicon；LOCOS)部件及/或其他合適的隔離部件。
方法100接著進行方框106，於此步驟中在鰭片結構上形成包覆層。可在每一個鰭片結構上形成包覆層。參見第4圖的範例，在每一個鰭片結構212上形成包覆層402。一些實施例中，包覆層402可具有與犧牲層206相似的成分。一些實施方式中，包覆層402同樣是犧牲層。在一實施例中，由矽鍺(SiGe)形成包覆層402。一些實施方式中，包覆層402和犧牲層206包含的成分，在隨後製程中藉由單一蝕刻劑來露出(release)通道層208的期間，可選擇性地移除犧牲層206和包覆層402，如下所述。在一實施例中，包覆層402的磊晶成長可使用氣相磊晶(vapor-phase epitaxy；VPE)、分子束磊晶(molecular beam epitaxy；MBE)或其他合適的製程。在一實施例中，包覆層402的形成可使用沉積製程，例如CVD製程、次大氣壓CVD(SACVD)製程、流動式CVD製程、ALD製程、PVD製程或其他合適的製程。在沉積之後，一些實施例中，方框106的操作可包含回蝕刻製程以移除包覆層402的材料，例如共形地(conformally)沉積在隔離部件203上之包覆層402的材料。一些實施例中，包覆層402的厚度在大約9 nm與大約12 nm之間。
方法100接著進行方框108，於此步驟中在鰭片結構上沉積第一介電層，藉此內襯相鄰的鰭片結構之間的開口。第一介電層為形成分離結構之複數層中的一者，分離結構也稱為介電鰭片，在相鄰的主動區之間，以下會進一步討論。參見第5圖的範例，沉積第一介電層502。一些實施例中，第一介電層502可包含高介電常數(high-k)的介電質。在一實施例中，第一介電層502可為氮化矽、碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)或前述之組合。一些實施例中，介電層502包含HfO 2、HfSiO、HfSiO 4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlO x、ZrO、ZrO 2、ZrSiO 2、AlO、AlSiO、Al 2O 3、TiO、TiO 2、LaO、LaSiO、Ta 2O 3、Ta 2O 5、Y 2O 3、SrTiO 3、BaZrO、BaTiO 3、(Ba,Sr)TiO 3、HfO 2-Al 2O 3、其他合適的高介電常數介電材料或前述之組合。第一介電層502的沉積可使用CVD、ALD或其他合適的製程。
方法100接著進行方框110，於此步驟中在第一介電層上形成介於第一組鰭片結構之間的第二介電層。參見第6圖的範例，形成介於鰭片212-1與212-2之間，且也介於鰭片212-3與212-4之間的介電層602。可自相鄰的鰭片212-2與212-3之間，以及相鄰的鰭片212-4與212-5之間省略介電層602。在一實施例中，鰭片212-2和212-3提供第一裝置類型(例如PFET)，且鰭片212-4和212-5提供第二裝置(例如NFET)。
一些實施例中，介電層602可為氧化物成分。使用流動式(flowable)化學氣相沉積(chemical vapor deposition；CVD)製程及/或其他製程，提供像是高深寬比沉積製程(high aspect ratio deposition process；HARP)之合適的間隙填充技術，以形成介電層602。一些實施方式中，可沉積液態的可流動氧化物材料，使其流入鰭片212之間的溝槽。一些實施例中，氧化物包含含有矽和氧的合適材料。可例如藉由退火及/或UV輻射來固化氧化物材料。一些實施方式中，沉積製程過度填充顯示的溝槽。在沉積之後，可實施像是化學機械研磨(chemical mechanical polish，CMP)的平坦化製程。在一實施例中，包覆層402為這樣的平坦化提供合適的蝕刻停止層。
一些實施方式中，在形成介電層602的期間，以遮罩層(未繪示)來覆蓋鄰近鰭片212-2與212-3之間以及鄰近鰭片212-4與212-5之間的間隔，以避免介電層602形成在選定的空間內。隨後可移除遮罩層。在另一實施方式中，一開始可將介電層602沉積在鄰近鰭片212-2與212-3之間以及鄰近鰭片212-4與212-5之間，隨後藉由合適的蝕刻製程將其移除。
方法100接著進行方框112，於此步驟中形成介於第二組鰭片結構之間的導線。在一實施例中，可在為同類型電晶體(例如NFET或PFET)之各主動區設計的兩個鰭片結構之間形成導線。可在鰭片之間的開口內，未形成方框110之第二介電層的位置形成導線。一些實施例中，在方框110的步驟之前先實施方框112的步驟，例如將導線圖案化於第二組鰭片結構之間，隨後在剩餘的鰭片結構之間形成方框110的介電層。
參見第7圖的範例，在第一介電層502上，分別在鰭片212-2與212-3之間以及鰭片212-4與212-5之間形成導線702。導線702可包含鎢、釕、鈷、鉭、鈦、銅、前述之組合及/或其他合適的材料。導線702可包含多層結構。一些實施例中，形成導線702之導電材料係沉積在基底上，且過度填充鰭片(鰭片結構212)之間的間隔。在沉積之後，可將裝置平坦化以移除鰭片(鰭片結構212)上的導電材料。可藉由ALD、電鍍、CVD及/或其他合適的製程來沉積導電材料。
如以下關於第14B和14C圖所討論的，一些實施例中，可在虛設區中(例如裝置200之佈局無功能性裝置的區域)，在第一個鰭片結構212與第二個鰭片結構212之間沉積導電材料。可將導電材料定位在虛設區中前述之第一個鰭片結構212與第二個鰭片結構212之間的位置，使得隨後在導線702上且相鄰於導線702形成兩個鰭片之間的閘極線路，如下所討論。
方法100接著進行方框114，於此步驟中修整先前形成在鰭片之間的層，且在第二介電層和導線上形成第三介電層。一些實施例中，方框114包含選擇性蝕刻第二介電層及/或導線以形成開口，其中第三介電層將形成於前述的開口中。參見第8圖的範例，形成開口802。一些實施例中，蝕刻製程係用以選擇性移除部分的第二介電層602及/或導線702。一些實施例中，並未蝕刻第一介電層502。一些實施例中，在同時或分開實施第二介電層602和導線702之蝕刻的情況下，使用遮罩元件來保護部分的裝置200。蝕刻製程為乾式蝕刻製程、濕式蝕刻製程或前述之組合。
參見第9A圖的範例，在第一介電層502和第二介電層602上，且在開口802內沉積介電層或蓋層902。一些實施例中，蓋層902可包含高介電常數的介電材料，例如金屬氧化物。高介電常數的介電材料係指與二氧化矽之介電常數(~3.9)相比，具有較高之介電常數的介電材料。合適之高介電常數的介電材料可包含氧化鉿、氧化鋯、氧化鈦、氧化鉭或氧化鋁。一些實施例中，蓋層902可具有與第一介電層502相同的成分。一些實施例中，蓋層902的沉積可使用CVD、流動式CVD及/或其他合適的沉積方法，隨後可藉由像是CMP製程的平坦化製程以提供第9A圖中顯示的平坦頂面。
第一介電層502、第二介電層602和第三介電層902在選定的鰭片結構之間形成分離結構，也稱為介電鰭片904。在所示的實施方式中，介電鰭片904係顯示在鰭片212-1與212-2之間，以及在鰭片212-3與212-4之間。
第三介電層902也形成在導線702上，且位於選定的鰭片結構之間。介電層902可適當地將導線702與上方的結構絕緣，上方的結構包含例如隨後形成的閘極結構。
第9B圖顯示裝置200之一部分的實施例的俯視圖，包含鰭片212-1至212-5、介電鰭片904和導線702。第9B圖的佈局進一步顯示裝置200之額外的部分，在一些實施例中為第二單元，且此第二單元實質上相似於第8圖顯示之裝置200。一些實施例中，這些單元為SRAM單元。在進一步的實施例中，導線702-1提供Vdd連接。在進一步的實施例中，導線702-2提供Vss連接。要注意的是，導線702係配置為與鰭片結構212平行延伸。
方法100接著進行方框116，於此步驟中，方法在鰭片結構各自的通道區上提供複數個閘極結構。在一實施例中，方法100提供替代閘極製程，且在方框116之步驟中形成的閘極結構為隨後將由金屬閘極結構取代的犧牲或虛設閘極，如下關於方框130所討論的部分。可將虛設閘極放置在鰭片結構的通道區上，介於鰭片結構的兩個源極/汲極區之間的區域。當實施更進一步的製程時，虛設閘極可保護鰭片結構的通道區，隨後再以下面討論的功能性閘極取代虛設閘極。然而其他製程和組態也可能用於形成裝置200。參見第10A和10C圖的範例，形成虛設閘極結構1002。要注意的是，虛設閘極出現在第10B圖包含之剖面示意圖的平面外，第10B圖係提供鰭片結構212的源極/汲極區的剖面示意圖。雖然在一些實施方式中，虛設閘極(虛設閘極結構1002)係顯示為長度沿著X方向延伸的連續結構，然而虛設閘極1002可包含不只一個閘極區段。
每一個虛設閘極結構1002可包含虛設介電層和虛設閘極電極。一些實施例中，虛設閘極結構1002的形成可藉由各種製程步驟，例如層的沉積、圖案化、蝕刻和其他合適的製程步驟。示範之層的沉積製程包含低壓CVD、CVD、電漿輔助CVD(plasma-enhanced CVD；PECVD)、PVD、ALD、加熱氧化、電子束蒸鍍或其他合適的沉積技術，或者前述之組合。圖案化製程可包含微影製程(例如光學微影或電子束微影)，微影製程可進一步包含光阻塗布(例如旋轉塗布)、軟烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、清洗、烘乾(例如旋轉烘乾及/或硬烤)、其他合適的微影技術及/或前述之組合。一些實施例中，蝕刻製程可包含乾式蝕刻(例如RIE蝕刻)、濕式蝕刻及/或其他蝕刻方法。一些實施例中，虛設介電層可包含氧化矽，且虛設電極層可包含多晶矽(polysilicon)。虛設閘極結構1002可包含沿其側壁沉積的一或多個閘極間隙物。
方法100接著進行方框118，於此步驟中，將相鄰於虛設閘極結構之鰭片結構的源極/汲極區凹陷。蝕刻鰭片結構以形成溝槽或開口，其中源極/汲極部件將形成於前述的溝槽或開口中，如下參見方框126所討論的部分。參見第10A和10B圖範例，藉由將鰭片結構212的源極/汲極區凹陷以形成溝槽1004。溝槽1004分別標記為1004-1、1004-2、1004-3、1004-4和1004-5。可藉由乾式蝕刻製程及/或其他合適的蝕刻製程來形成溝槽1004。舉例而言，乾式蝕刻製程可實施含氧氣體、氫、含氟氣體(例如CF 4、SF 6、CH 2F 2、CHF 3及/或C 2F 6)、含氯氣體(例如Cl 2、CHCl 3、CCl 4及/或BCl 3)、含溴氣體(例如HBr及/或CHBR 3)、含碘氣體、其他合適的氣體及/或電漿，及/或前述之組合。一些實施例中，在形成鰭片結構212之源極/汲極區的凹陷期間，同時也從鰭片結構212的源極/汲極區移除包覆層402。溝槽1004暴露出凹陷之鰭片結構212的頂面，以及隔離部件203之頂面的相鄰區域。
第10C圖顯示裝置200的之佈局俯視圖的實施例。如圖所示，虛設閘極結構1002垂直延伸至主動區、鰭片結構212和導線702。
方法100接著進行方框120，於此步驟中在裝置上形成遮罩元件。當在上述方框112之步驟形成的導線上提供一或多個開口時，遮罩元件可用來保護裝置的區域。參見第11圖的範例，在裝置200上形成遮罩元件1102，且遮罩元件1102具有在導線702上的開口1104。遮罩元件1102的形成可藉由合適的光學微影製程。光學微影製程可包含在基底202上形成光阻層，將光阻層對圖案進行曝光，實施曝光後烘烤製程，以及對光阻層進行顯影以形成包含光阻層的遮罩元件1102。一些實施例中，遮罩元件包含硬遮罩材料。一些實施例中，可使用電子束(e-beam)微影製程對光阻層進行圖案化以形成遮罩元件。開口1104可與鰭片212之主動區平行延伸。一些實施例中，開口1104具有寬度(垂直於鰭片212延伸的方向，例如在第11圖之X方向上的寬度)，此開口的寬度實質上等於隔離部件203在鰭片結構212之間延伸的寬度。
方法100接著進行方框122，於此步驟中移除相鄰於導線的第一介電層。一些實施例中，在方框120的遮罩元件中提供的開口內移除第一介電層。可藉由選擇性蝕刻移除第一介電層，同時保留導線。一些實施例中，此蝕刻提供SiN、SiCN的第一介電層對於導線之導線材料的選擇性蝕刻。此蝕刻可採用合適的氮化物蝕刻劑，例如碳-氟成分。此蝕刻可為濕式蝕刻、乾式蝕刻及/或其他合適的蝕刻製程。一些實施例中，此蝕刻為濕式蝕刻和乾式蝕刻的組合。參見第12A圖的範例，移除在遮罩元件1102之開口1104中的第一介電層502。一些實施例中，保留在導線702正下方的介電層502。
舉例而言，一些實施例中，在完成蝕刻製程之後，保留在導線702下方之第一介電層502的剩餘部分502’。這部分顯示於第12B圖中。
方法100接著進行方框124，於此步驟中形成相鄰於導線的導電襯層。一些實施例中，導電襯層為矽化物層，例如TiSi。一些實施例中，導電襯層可為其他的導電成分。參見第13A、13B和13C圖的範例，形成導電襯層1304。一些實施例中，導電襯層1304可為TiSi。第13C圖提供接續第12B圖的實施例和剩餘部分502’。
方法100接著進行方框126，於此步驟中，在凹陷的鰭片結構上成長源極和汲極部件。可在包含凹陷之鰭片結構頂面的晶種區域上磊晶成長源極/汲極部件。一些實施例中，磊晶製程可為氣相磊晶(VPE)、超高真空CVD(UHV-CVD)、分子束磊晶(MBE)及/或其他合適的製程。參見第13A和13B圖的範例，在相應之凹陷的鰭片結構212上分別形成標記為1302-1、1302-2、1302-3、1302-4和1302-5的源極/汲極部件1302。可磊晶成長源極/汲極部件1302並對其適度地摻雜以提供相關的導電類型(N型或P型)。在各種實施例中，成長源極/汲極部件1302的半導體材料層可包含Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、SiP、SiC及/或其他合適的材料。可藉由一或多個磊晶製程來形成源極/汲極部件1302。一些實施例中，可在磊晶製程期間對源極/汲極部件1302進行原位(in-situ)摻雜。舉例而言，一些實施例中，可對磊晶成長的SiGe源極/汲極部件摻雜硼。一些例子中，可對磊晶成長的Si磊晶源極/汲極部件摻雜碳以形成Si:C源極/汲極部件，摻雜磷以形成Si:P源極/汲極部件，或者摻雜碳和磷兩者以形成SiCP源極/汲極部件。一些實施例中，並未對源極/汲極部件1302進行原位摻雜，取而代之的是，實施植入製程以摻雜源極/汲極部件1302。一些實施例中，可在分開的製程系列中分別形成N型和P型源極/汲極部件，以實施源極/汲極部件1302的形成。
在一實施例中，源極/汲極部件1302-2和1302-3為第一類型之裝置(例如PFET)的源極/汲極部件。在進一步的實施例中，源極/汲極部件1302-1、1302-4和1302-5為第二類型之裝置(例如NFET)的源極/汲極部件。或者，其他組態的裝置類型也是可能的。由於某些源極/汲極部件1302與其他的源極/汲極部件1302不同，它們可使用遮罩層以分別形成。
要注意在一些實施例中，相鄰於通道區形成內間隙物。舉例而言，使用第10A圖的範例，可稍微凹陷鄰接溝槽1004之暴露的犧牲層206，並形成內間隙物(例如介電材料，未繪示)。
一些實施例中，在方框126的步驟後至少實施部分的方框124。一些實施例中，導電襯層為矽化物層，且藉由源極/汲極部件1302之半導體材料與相鄰的導線702相互作用而形成。舉例而言，一些實施例中，在源極/汲極部件1302上沉積含鈦層(或其他金屬)。實施退火以提供矽鈦化合物。
方法100接著進行方框128，於此步驟中移除虛設閘極，並露出通道層。方法100接著進行方框128，於此步驟中移除虛設閘極，並在鰭片結構的通道區內露出堆疊的通道層。虛設閘極的移除及/或通道層的露出可包含一或多個蝕刻步驟。一些實施例中，選擇性濕式蝕刻包含APM蝕刻(例如氫氧化銨-過氧化氫-水的混合物)。一些實施例中，犧牲層206和包覆層402係由矽鍺形成，在包含對矽鍺進行氧化的選擇性移除後，接著移除矽鍺氧化物。舉例而言，可藉由臭氧清洗來實施前述之氧化，然後藉由像是NH 4OH的蝕刻劑來移除矽鍺氧化物。
方法100接著進行方框130，於此步驟中形成金屬閘極結構。金屬閘極結構係形成在鰭片結構的通道區上。參見第14A和14B圖的範例，在裝置上形成金屬閘極結構1400。
參見第14A和14B圖的範例，在鰭片結構212的通道區上形成取代虛設閘極結構1002的金屬閘極結構1400。
一些實施例中，金屬閘極結構包含閘極介電層和形成在閘極介電層上的閘極電極。一些實施例中，閘極介電層可包含界面層和高介電常數的介電層。在此使用和描述之高介電常數的閘極介電質包含具有高介電常數的介電材料，例如高於熱氧化矽的介電常數(~3.9)。界面層可包含像是氧化矽、鉿矽酸鹽或氮氧化矽的介電材料。界面層的沉積可使用化學氧化、加熱氧化、原子層沉積(atomic layer deposition；ALD)、化學氣相沉積(chemical vapor deposition；CVD)及/或其他合適的方法。高介電常數的介電層可包含像是氧化鉿的高介電常數介電層。或者，高介電常數的介電層可包含其他高介電常數的介電質，例如氧化鉿(HfO)、氧化鈦(TiO 2)、氧化鉿鋯(HfZrO)、氧化鉭(Ta 2O 5)、氧化鉿矽(HfSiO 4)、氧化鋯(ZrO 2)、氧化鋯矽(ZrSiO 2)、氧化鑭(La 2O 3)、氧化鋁(Al 2O 3)、氧化鋯(ZrO)、氧化釔(Y 2O 3)、SrTiO 3(STO)、BaTiO 3(BTO)、BaZrO、氧化鉿鑭(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、(Ba,Sr)TiO 3(BST)、氮化矽(SiN)、氮氧化矽(SiON)、前述之組合或其他合適的材料。可藉由ALD、物理氣相沉積(physical vapor deposition；PVD)、CVD、氧化及/或其他合適之方法來形成高介電常數的介電層。
金屬閘極結構1400的閘極電極可包含多層結構，例如具有選定功函數以增加裝置效能之金屬層(功函數金屬層)、襯層、潤濕層、黏著層、金屬合金或金屬矽化物的各種組合。舉例來說，閘極電極可為氮化鈦(TiN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、碳化鋁鉭(TaAlC)、碳氮化鉭(TaCN)、鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化矽鉭(TaSiN)、銅(Cu)、其他耐火金屬或其他合適的金屬材料，或者前述之組合。在各種實施例中，閘極結構之閘極電極的形成可藉由ALD、PVD、CVD、電子束蒸鍍或其他合適的製程。在各種實施例中，可實施平坦化製程，例如CMP製程，移除過量的材料以提供閘極結構實質上平坦的頂面。某些金屬閘極結構係耦接在一起。介電鰭片904可作為相鄰金屬閘極結構之間的分離結構。這也顯示在第15A圖的剖面示意圖中。導線702可例如藉由介電層902與金屬閘極結構1400絕緣。
一些實施例中，裝置之虛設區中的閘極結構並非結果形成之IC(包含裝置200)中的功能性閘極結構，可形成與導線702相鄰的閘極結構1400’。第15B圖係關於某些閘極結構的說明，在這種情況下導線702可介於閘極之間且與閘極電性耦接。第15C圖顯示包含閘極結構1400’之虛設區1404的佈局俯視圖。閘極結構1400’可與導線702接合。在一實施例中，將導孔1408形成至閘極結構1400’以及導線702。一些實施例中，此處的導線702係提供電源線或電源線之一部分的佈線，例如Vss或Vdd。
第15B圖顯示的配置具有從一個鰭片延伸至另一個鰭片的閘極結構1400’，以及介於兩個鰭片之間的導線702(即頂部區域耦接延伸至導線702上的閘極結構)，導線702可提供在相同的鰭片212上源極/汲極區鄰接導線(即鰭片212-2和212-3，或者鰭片212-4和212-5)的地方或可為裝置200的不同部分。
方法100接著進行方框132，於此步驟中進一步實施後續的製程。後續的製程可例如包含沉積額外的接觸蝕刻停止層(contact etch stop layer；CESL)，沉積額外的層間介電(interlayer dielectric；ILD)層和上覆的導電部件，導電部件例如接觸導孔和金屬化線路。一些實施例中，由第15A和15B圖的介電層1406來顯示中間的接觸蝕刻停止層。接觸蝕刻停止層可包含氮化矽、氧化矽、氮氧化矽及/或其他本技術領域中已知的材料。接觸蝕刻停止層1406的沉積可使用ALD、電漿輔助CVD(PECVD)及/或其他合適的沉積或氧化製程。一些實施例中，可在與第15B圖之金屬化物1410相鄰的接觸蝕刻停止層上沉積層間介電層。一些實施例中，層間介電層包含的材料例如為正矽酸四乙酯(tetraethylorthosilicate；TEOS)氧化物、未經摻雜的矽酸鹽玻璃或經摻雜的氧化矽，像是硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)、熔融矽石玻璃(fused silica glass；FSG)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、摻硼矽玻璃(boron doped silicon glass；BSG)及/或其他合適的介電材料。可在隨後的製程中提供穿過介電層的接觸部件，包含含有第15A和15B圖之接觸導孔1408的接觸部件。導孔1408互連至金屬化物1410，金屬化物1410可稱為M0。
注意在上述之方法100的實施例中，導線702係在源極/汲極部件之前形成。或者在一些實施方式中，介電鰭片904係形成在每一個源極/汲極部件1302之間，包含例如在源極/汲極部件1302-2與1302-3之間。在成長源極/汲極部件之後，形成遮罩元件以在設置於源極/汲極部件之間的某些介電鰭片904上提供開口，例如在源極/汲極部件1302-2與1302-3之間的開口，以及源極/汲極部件1302-4與源極/汲極部件1302-5上的開口。然後從這些區域移除介電鰭片904，並在因介電鰭片904之移除而形成的開口中形成實質上與導線702相似的導線702和導電襯層1304。一些實施方式中，結果形成之裝置實質上與第13A圖相似，且方法由此繼續。
一些實施例中，上述的導電層702提供IC或IC之一部分的訊號或電源線。除了在隨後之申請專利範圍中具體記載的內容之外，半導體裝置200的確切功能不限於現在描述的主題。然而，作為一個範例，在某些實施方式中，可提供導線702於與SRAM裝置相關的線路。舉例而言，在一實施方式中，半導體裝置200包含SRAM，其可包含許多SRAM單元，例如第16圖所示之六電晶體(6T)單埠(SP)SRAM單元1600。參見第16圖，六電晶體單埠SRAM單元1600包含兩個PMOSFET(例如上述的P型GAA電晶體或P型FinFET)，作為上拉(pull-up)電晶體PU-1和PU-2；兩個NMOSFET(例如上述的N型GAA電晶體或N型FinFET)，作為下拉(pull-down)電晶體PD-1和PD-2；以及兩個NMOSFET(例如N型FinFET或N型GAA電晶體)，作為傳送閘(pass-gate)電晶體PG-1和PG-2。上拉電晶體PU-1與下拉電晶體PD-1耦接以形成反向器(inverter)。上拉電晶體PU-2與下拉電晶體PD-2耦接以形成另一反向器。這兩個反向器跨越耦接在一起以形成儲存單元。第16圖進一步顯示字元線(word line；WL)、位元線(bit line；BL)和反位元線(bit line bar，BLB)，用以存取SRAM單元1600的儲存單元。圖中也顯示電源線Vss和Vdd(Vcc)。在一實施例中，形成分別包含鰭片212-4與212-5之主動區的下拉電晶體PD-1與PD-2。在一實施例中，下拉電晶體PD-1與PD-2耦接至Vss，在一些實施方式中例如像是導線702-2的導線702。在一實施例中，上拉電晶體PU-1與PU-2分別包含鰭片212-2與212-3的主動區。在一實施例中，上拉電晶體PU-1與PU-2耦接至Vcc/Vdd，在一些實施方式中例如像是導線702-1。
上述形成金屬化線路的實施例可用於Vcc或Vdd的連接。然而，如第16圖所示，像是SRAM單元 1600的裝置具有額外的訊號線。在某些設計中，其他線路也可使用上述的方法和結構來形成，包含但不限於位元線。舉例而言，若訊號線要與主動區(例如鰭片結構)平行延伸，則適合提供嵌入主動區之間的金屬化物，如本文所提供的。再者，SRAM的實施方式僅為例示，其他裝置類型也能適用。
在一示範態樣中，本發明實施例係關於半導體裝置。裝置包含從基底延伸的第一鰭片結構、第二鰭片結構和第三鰭片結構。第一源極/汲極部件係形成在第一鰭片結構上。第二源極/汲極部件係形成在第二鰭片結構上。第三源極/汲極部件係形成在第三鰭片結構上。介電分離結構在第一源極/汲極部件與第二源極/汲極部件之間延伸。導線係設置在第二源極/汲極部件與第三源極/汲極部件之間。
在進一步的實施例中，在第一鰭片結構與第二鰭片結構之間提供第一淺溝槽隔離(shallow trench isolation；STI)部件。第二淺溝槽隔離部件在第二鰭片結構與第三鰭片結構之間延伸。在一實施例中，介電分離結構係設置在第一淺溝槽隔離部件上。在一實施例中，導線係設置在第二淺溝槽隔離部件上。一些實施方式中，第一源極/汲極部件為第一導電類型，且第二源極/汲極部件和第三源極/汲極部件為第二導電類型。
在一實施例中，導線分別與第一鰭片結構、第二鰭片結構和第三鰭片結構平行延伸。一些實施方式中，導線包含導電襯層。導電襯層可為矽化物成分。在一實施例中，在第一鰭片結構、第二鰭片結構和第三鰭片結構中的至少兩者上形成金屬閘極結構，金屬閘極結構可延伸至導線上。
在另一較廣的實施例中，半導體裝置包含具有第一電晶體和第二電晶體的記憶體單元。第一電晶體的第一源極/汲極部件係形成在凹陷的第一鰭片結構上。第二電晶體的第二源極/汲極部件係形成在凹陷的第二鰭片結構上。電源線係設置在第一源極/汲極部件與第二源極/汲極部件之間。
一些實施方式中，第一源極/汲極部件和第二源極/汲極部件分別包含磊晶成長的矽。在一實施例中，第一電晶體和第二電晶體為相同的導電類型(例如N型或P型)。在一實施例中，電源線傳送Vcc。在一實施例中，電源線傳送Vss。一些實施方式中，裝置更包含虛設區，具有第一虛設閘極和連接至第一虛設閘極的第二虛設閘極，以及另一電源線，設置在第一虛設閘極與第二虛設閘極之間。
在此處討論的另一實施例中提供方法。方法包含提供設置在基底上的第一鰭片結構、第二鰭片結構和第三鰭片結構。在第一鰭片結構與第二鰭片結構之間形成介電鰭片。在第二鰭片結構與第三鰭片結構之間形成導線。方法包含形成延伸至第二鰭片結構、導線和第三鰭片結構上的閘極結構。將第一鰭片結構、第二鰭片結構和第三鰭片結構各自的源極/汲極區凹陷。分別在第一鰭片結構、第二鰭片結構和第三鰭片結構上磊晶成長第一源極/汲極部件、第二源極/汲極部件和第三源極/汲極部件。
在進一步的實施例中，在方法的磊晶成長部分之後，移除閘極結構並形成金屬閘極結構。在一實施例中，形成介電鰭片包含：沉積第一介電層；沉積第二介電層；回蝕刻第二介電層的一部分；以及在第一介電層和第二介電層上沉積高介電常數的介電層。
一些實施例中，方法更包含在第一鰭片結構與第二鰭片結構之間，且在第二鰭片結構與第三鰭片結構之間形成多個淺溝槽隔離(STI)部件。介電鰭片可形成在這些淺溝槽隔離部件的其中一者上，且導線係形成在這些淺溝槽隔離部件的另一者上。一些實施方式中，方法包含在形成閘極結構之後，在導線與磊晶成長的第二源極/汲極部件上形成矽化物層。
前述內文概述了許多實施例的部件，以使本技術領域中具有通常知識者可以更佳地了解本發明實施例的各種態樣。本技術領域中具有通常知識者應可理解他們可使用本發明實施例為基礎來設計或修改其他製程及結構，以達到相同的目的及/或達到與在此介紹的實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的架構並未背離本發明實施例的精神與範圍。而在不背離本發明實施例的精神與範圍之前提下，他們可對本文進行各種改變、替換或變更。
100:方法 102:方框 104:方框 106:方框 108:方框 110:方框 112:方框 114:方框 116:方框 118:方框 120:方框 122:方框 124:方框 126:方框 128:方框 130:方框 132:方框 200:半導體裝置 202:基底 202A:基座部分 203:隔離部件 204:堆疊 206:犧牲層 208:通道層 210:硬遮罩層 212:鰭片結構 212-1:鰭片 212-2:鰭片 212-3:鰭片 212-4:鰭片 212-5:鰭片 402:包覆層 502:介電層 502’:剩餘部分 602:介電層 702:導線 702-1:導線 702-2:導線 802:開口 902:蓋層 904:介電鰭片 1002:虛設閘極結構 1004:溝槽 1004-1:溝槽 1004-2:溝槽 1004-3:溝槽 1004-4:溝槽 1004-5:溝槽 1102:遮罩元件 1104:開口 1302:源極/汲極部件 1302-1:源極/汲極部件 1302-2:源極/汲極部件 1302-3:源極/汲極部件 1302-4:源極/汲極部件 1302-5:源極/汲極部件 1304:導電襯層 1400:金屬閘極結構 1400’:閘極結構 1404:虛設區 1406:接觸蝕刻停止層 1408:導孔 1410:金屬化物 1600:SRAM單元 PD-1:下拉電晶體 PD-2:下拉電晶體 PG-1:傳送閘電晶體 PG-2:傳送閘電晶體 PU-1:上拉電晶體 PU-2:上拉電晶體
從以下的詳述配合所附圖式可更加理解本發明實施例。要強調的是，根據工業上的標準做法，各個部件並未按照比例繪製，且僅用於說明之目的。事實上，為了能清楚地討論，可任意地放大或縮小各個部件的尺寸。 第1圖是根據本發明實施例的一或多個態樣，顯示半導體裝置之形成方法的流程圖。 第2、3、4、5、6、7、8、9A、10B、11、12A、13A、15A和15B圖是根據本發明實施例的一或多個態樣，顯示在依照第1圖之方法的製程期間結構的部分剖面示意圖。 第12B和13C圖是根據本發明實施例的一或多個態樣，顯示在依照第1圖之方法的製程期間結構之變化的部分剖面示意圖。 第9B、10C、14B和15C圖是根據本發明實施例的一或多個態樣，顯示依照第1圖之方法，與製程相關之佈局(layout)的部分俯視圖。 第10A、13B和14A圖是根據本發明實施例的一或多個態樣，顯示依照第1圖之方法，與製程相關的部分透視圖。 第16圖是使用本發明實施例的態樣，在一些實施例中可實施的裝置示意圖。
無
212:鰭片結構
702:導線
1400:金屬閘極結構
1400’:閘極結構
1404:虛設區
1408:導孔

Claims (1)

  1. 一種半導體裝置，包括： 一第一鰭片結構、一第二鰭片結構和一第三鰭片結構，從一基底延伸； 一第一源極/汲極部件，在該第一鰭片結構上； 一第二源極/汲極部件，在該第二鰭片結構上； 一第三源極/汲極部件，在該第三鰭片結構上； 一介電分離結構，在該第一源極/汲極部件與該第二源極/汲極部件之間延伸；以及 一導線，在該第二源極/汲極部件與該第三源極/汲極部件之間。
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