TW201707071A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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TW201707071A
TW201707071A TW104143212A TW104143212A TW201707071A TW 201707071 A TW201707071 A TW 201707071A TW 104143212 A TW104143212 A TW 104143212A TW 104143212 A TW104143212 A TW 104143212A TW 201707071 A TW201707071 A TW 201707071A
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Taiwan
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insulating film
gate insulating
metal
film
gate electrode
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TW104143212A
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Chinese (zh)
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Yoshitake Kato
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Renesas Electronics Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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Abstract

To improve characteristics of a semiconductor device. In a semiconductor device (MISFET) having a gate electrode GE that is formed on a nitride semiconductor layer CH with a gate insulating film GI therebetween, the gate insulating film GI is configured such that the gate insulating film has a first gate insulating film (oxide film formed of a first metal) GIa formed on the nitride semiconductor layer CH, and a second gate insulating film (oxide film formed of a second metal) GIb. The second metal (for instance, Hf) has a lower electronegativity than the first metal (for instance, Al). In this manner, a threshold voltage (Vth) can be shifted in the positive direction by having the electronegativity of the second metal lower than the electronegativity of the first metal. Furthermore, the gate electrode GE is configured such that the gate electrode has a first gate electrode (nitride film formed of a third metal) GEa formed on the second gate insulating film GIb, and a second gate electrode (fourth metal) GEb. Consequently, oxygen is prevented from diffusing to the gate insulating film GI, and fluctuation of the threshold voltage (Vth) can be reduced.

Description

半導體裝置及半導體裝置之製造方法 Semiconductor device and method of manufacturing the same

本發明係關於一種半導體裝置及半導體裝置之製造方法，例如可於使用氮化物半導體之半導體裝置及其製造方法中適宜地利用。 The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and can be suitably used, for example, in a semiconductor device using a nitride semiconductor and a method of manufacturing the same.

近年來，使用具有大於Si之帶隙的III-V族化合物之半導體裝置受到關注。其中，使用氮化鎵(GaN)等氮化物半導體之半導體裝置具有高速且低損耗地動作之特性。又，使用氮化鎵系氮化物半導體之功率MISFET(Metal Insulator Semiconductor Field Effect Transistor，金屬絕緣半導體場效電晶體)能夠實現常斷開動作，其之開發得到推進。 In recent years, semiconductor devices using a group III-V compound having a band gap larger than Si have been attracting attention. Among them, a semiconductor device using a nitride semiconductor such as gallium nitride (GaN) has a characteristic of operating at high speed and low loss. Further, the power MISFET (Metal Insulator Semiconductor Field Effect Transistor) using a gallium nitride nitride semiconductor can realize a normally-off operation, and the development thereof has been advanced.

例如，於以下之專利文獻1(日本專利特開2014-183125號公報)中揭示一種常斷開型半導體裝置，其包含：由i-GaN而形成之電子移行層、由AlGaN而形成之電子供給層、源極電極、汲極電極、及形成於絕緣膜上之閘極電極。閘極電極係使用Ni/Au，藉由舉離法而形成。 For example, a normally-off type semiconductor device including an electron transition layer formed of i-GaN and an electron supply formed of AlGaN is disclosed in Patent Document 1 (Japanese Laid-Open Patent Publication No. 2014-183125). a layer, a source electrode, a drain electrode, and a gate electrode formed on the insulating film. The gate electrode was formed by lift-off method using Ni/Au.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本專利特開2014-183125號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2014-183125

本發明者從事如上所述之使用氮化物半導體之半導體裝置之研究開發，關於常斷開型半導體裝置之特性提高而進行了銳意研究。於其過程中，判明關於使用氮化物半導體之半導體裝置及半導體裝置之 製造方法，存在進一步改善之餘地。 The present inventors conducted research and development of a semiconductor device using a nitride semiconductor as described above, and conducted intensive studies on the improvement of characteristics of a normally-off type semiconductor device. In the process, it was found that a semiconductor device and a semiconductor device using a nitride semiconductor There is room for further improvement in the manufacturing method.

其他課題與新穎之特徵可根據本說明書之記載及隨附圖式而變得明瞭。 Other matters and novel features will become apparent from the description and the accompanying drawings.

於本案中所揭示之實施形態中，若簡單地說明代表性者之概要，則如下所示。 In the embodiment disclosed in the present disclosure, the outline of a representative person will be briefly described as follows.

本案中所揭示之一實施形態中所示之半導體裝置包含第1閘極絕緣膜、第2閘極絕緣膜、第1閘極電極及第2閘極電極。並且，第1閘極絕緣膜係含有第1金屬之氧化膜或含有矽之氧化膜，第2閘極絕緣膜係含有第2金屬之氧化膜，第2金屬之陰電性小於第1金屬或矽之陰電性。又，第1閘極電極係含有第3金屬之氮化膜，第2閘極電極包含第4金屬。 The semiconductor device shown in one embodiment of the present invention includes a first gate insulating film, a second gate insulating film, a first gate electrode, and a second gate electrode. Further, the first gate insulating film contains an oxide film of a first metal or an oxide film containing germanium, and the second gate insulating film contains an oxide film of a second metal, and the second metal has a lower electrical property than the first metal or The yin of electricity. Further, the first gate electrode includes a nitride film of a third metal, and the second gate electrode includes a fourth metal.

本案中所揭示之一實施形態中所示之半導體裝置之製造方法包含於氮化物半導體層上形成包含含有第1金屬之氧化膜或含有矽之氧化膜的第1閘極絕緣膜之步驟。並且，包含於第1閘極絕緣膜上形成包含第2金屬之氧化膜的第2閘極絕緣膜之步驟、及於第2閘極絕緣膜上形成包含含有第3金屬之氮化膜的第1閘極電極之步驟。進而，包含於第1閘極電極上形成包含第4金屬之第2閘極電極之步驟。並且，第1閘極絕緣膜係含有第1金屬之氧化膜或含有矽之氧化膜，第2閘極絕緣膜係含有第2金屬之氧化膜，第2金屬之陰電性小於第1金屬或矽之陰電性。 The method for fabricating a semiconductor device according to one embodiment disclosed in the present invention includes the step of forming a first gate insulating film including an oxide film containing a first metal or an oxide film containing germanium on the nitride semiconductor layer. Further, a step of forming a second gate insulating film including an oxide film of the second metal on the first gate insulating film, and a step of forming a nitride film containing the third metal on the second gate insulating film 1 step of the gate electrode. Further, a step of forming a second gate electrode including the fourth metal is formed on the first gate electrode. Further, the first gate insulating film contains an oxide film of a first metal or an oxide film containing germanium, and the second gate insulating film contains an oxide film of a second metal, and the second metal has a lower electrical property than the first metal or The yin of electricity.

藉由本案中所揭示之以下所示之代表性實施形態中所示之半導體裝置，能夠使半導體裝置之特性提高。 The characteristics of the semiconductor device can be improved by the semiconductor device shown in the representative embodiment shown below in the present disclosure.

藉由本案中所揭示之以下所示之代表性實施形態中所示之半導體裝置之製造方法，能夠製造特性良好之半導體裝置。 A semiconductor device having excellent characteristics can be manufactured by the method of manufacturing a semiconductor device shown in the representative embodiment shown below.

2DEG‧‧‧二維電子氣 2DEG‧‧‧Two-dimensional electronic gas

BA‧‧‧障壁層 BA‧‧ ‧ barrier layer

BU‧‧‧緩衝層 BU‧‧‧ buffer layer

CH‧‧‧通道層 CH‧‧‧ channel layer

DE‧‧‧汲極電極 DE‧‧‧汲 electrode

DL‧‧‧汲極線 DL‧‧‧汲polar line

DR‧‧‧汲極區域 DR‧‧‧Bungee area

GE‧‧‧閘極電極 GE‧‧‧gate electrode

GEa‧‧‧第1閘極電極 GEa‧‧1st gate electrode

GEb‧‧‧第2閘極電極 GEb‧‧‧2nd gate electrode

GI‧‧‧閘極絕緣膜 GI‧‧‧gate insulating film

GIa‧‧‧第1閘極絕緣膜 GIa‧‧1 first gate insulating film

GIb‧‧‧第2閘極絕緣膜 GIb‧‧‧2nd gate insulating film

GIu‧‧‧第3閘極絕緣膜 GIu‧‧3rd gate insulating film

IF‧‧‧絕緣膜 IF‧‧‧Insulation film

IL1‧‧‧絕緣層 IL1‧‧‧Insulation

IL2‧‧‧絕緣層 IL2‧‧‧Insulation

NUC‧‧‧核生成層 NUC‧‧‧ nuclear generation layer

PG‧‧‧插塞 PG‧‧‧ plug

S‧‧‧基板 S‧‧‧Substrate

SE‧‧‧源極電極 SE‧‧‧ source electrode

SL‧‧‧源極線 SL‧‧‧ source line

SR‧‧‧源極區域 SR‧‧‧ source area

STR‧‧‧應變緩和層 STR‧‧‧ strain relief layer

T‧‧‧溝 T‧‧‧Ditch

圖1係表示實施形態1之半導體裝置之構成之剖視圖。 Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment.

圖2係表示實施形態1之半導體裝置之其他構成之剖視圖。 Fig. 2 is a cross-sectional view showing another configuration of the semiconductor device of the first embodiment.

圖3係表示實施形態1之半導體裝置之比較例1之構成之剖視圖。 Fig. 3 is a cross-sectional view showing the configuration of a comparative example 1 of the semiconductor device of the first embodiment.

圖4係表示實施形態1之半導體裝置之比較例2之構成之剖視圖。 Fig. 4 is a cross-sectional view showing the configuration of a comparative example 2 of the semiconductor device of the first embodiment.

圖5(a)~(c)係表示樣品1~4中之氧濃度分佈之圖。 Fig. 5 (a) to (c) are graphs showing the oxygen concentration distribution in the samples 1 to 4.

圖6係表示實施形態1之半導體裝置之製造步驟之剖視圖。 Fig. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment.

圖7係表示實施形態1之半導體裝置之製造步驟之剖視圖，且係表示繼圖6之後之製造步驟之剖視圖。 Fig. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 6.

圖8係表示實施形態1之半導體裝置之製造步驟之剖視圖，且係表示繼圖7之後之製造步驟之剖視圖。 Fig. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 7.

圖9係表示實施形態1之半導體裝置之製造步驟之剖視圖，且係表示繼圖8之後之製造步驟之剖視圖。 Fig. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 8.

圖10係表示實施形態1之半導體裝置之製造步驟之剖視圖，且係表示繼圖9之後之製造步驟之剖視圖。 Fig. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 9.

圖11係表示實施形態1之半導體裝置之製造步驟之剖視圖，且係表示繼圖10之後之製造步驟之剖視圖。 Fig. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 10.

圖12係表示實施形態1之半導體裝置之特徵性構成之剖視圖。 Fig. 12 is a cross-sectional view showing a characteristic configuration of a semiconductor device of the first embodiment.

圖13係表示實施形態2之半導體裝置之構成之剖視圖。 Figure 13 is a cross-sectional view showing the configuration of a semiconductor device of a second embodiment.

圖14係表示實施形態2之半導體裝置之製造步驟之剖視圖。 Fig. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.

圖15係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖14之後之製造步驟之剖視圖。 Fig. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 14.

圖16係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖15之後之製造步驟之剖視圖。 Fig. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 15.

圖17係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖16之後之製造步驟之剖視圖。 Fig. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 16.

圖18係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖17之後之製造步驟之剖視圖。 Fig. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 17.

圖19係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖18之後之製造步驟之剖視圖。 Fig. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 18.

圖20係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖19之後之製造步驟之剖視圖。 Fig. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 19.

圖21係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖20之後之製造步驟之剖視圖。 Fig. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 20.

圖22係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖21之後之製造步驟之剖視圖。 Fig. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 21.

圖23係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖22之後之製造步驟之剖視圖。 Fig. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 22;

圖24係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖23之後之製造步驟之剖視圖。 Fig. 24 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 23.

圖25係表示實施形態2之半導體裝置之製造步驟之剖視圖，且係表示繼圖24之後之製造步驟之剖視圖。 Fig. 25 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step subsequent to Fig. 24.

圖26係表示實施形態2之半導體裝置之構成之俯視圖之一例。 Fig. 26 is a plan view showing an example of a configuration of a semiconductor device according to a second embodiment;

圖27係表示實施形態2之半導體裝置之構成之剖視圖。 Figure 27 is a cross-sectional view showing the configuration of a semiconductor device of a second embodiment.

圖28係表示實施形態3之半導體裝置之構成之剖視圖。 Figure 28 is a cross-sectional view showing the configuration of a semiconductor device of a third embodiment.

圖29係表示閘極絕緣膜之積層效果之曲線圖。 Fig. 29 is a graph showing the effect of lamination of a gate insulating film.

圖30係表示實施形態4之半導體裝置之構成之剖視圖。 Figure 30 is a cross-sectional view showing the configuration of a semiconductor device of a fourth embodiment.

圖31係表示實施形態5之半導體裝置之構成之剖視圖。 Figure 31 is a cross-sectional view showing the configuration of a semiconductor device of a fifth embodiment.

圖32係表示實施形態6之半導體裝置之構成之剖視圖。 Figure 32 is a cross-sectional view showing the configuration of a semiconductor device of a sixth embodiment.

於以下實施形態中，為了方便起見，必要時分割為複數個部分(section)或實施形態而進行說明，但除了特別明示之情形以外，該等 並非互無關係，其中一者與另一者之一部分或全部之變化例、應用例、詳細說明、補充說明等有關。又，於以下之實施形態中，於提及要素數等(包括個數、數值、量、範圍等)之情形時，除了特別明示之情形及原理上明確地限定為特定數之情形等以外，並不限定為該特定數，可為特定數以上或以下。 In the following embodiments, for the sake of convenience, it is described as being divided into a plurality of sections or embodiments as necessary, but except for the case where it is specifically stated, They are not related to each other, and one of them is related to some or all of the changes, application examples, detailed explanations, supplementary explanations, etc. of one of the other. In addition, in the following embodiments, when the number of elements (including the number, the numerical value, the quantity, the range, and the like) is mentioned, the case where the specific number is explicitly defined, the principle is clearly defined as a specific number, and the like. It is not limited to the specific number, and may be a specific number or more.

進而，於以下之實施形態中，其構成要素(亦包括要素步驟等)除了特別明示之情形及原理上明確地認為必須之情形等以外，並非一定為必須者。同樣地，於以下之實施形態中，於提及構成要素等之形狀、位置關係等時，除了特別明示之情形及原理上明確地認為並非如此之情形等以外，包括實質上與其形狀等近似或類似者等。關於上述數等(包括個數、數值、量、範圍等)，此方面亦同樣。 Further, in the following embodiments, the constituent elements (including the element steps and the like) are not necessarily essential except for the case where it is expressly considered necessary in the case of the case and the principle. Similarly, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are mentioned, except for the case where it is expressly considered to be not the case, and the like, it is substantially similar to the shape or the like. Similar to others. The same applies to the above numbers (including numbers, values, quantities, ranges, etc.).

以下，基於圖式對實施形態加以詳細說明。再者，於用以說明實施形態之所有圖中，對具有同一功能之構件標註同一或相關之符號，省略其重複說明。又，於存在複數個類似之構件(部位)之情形時，有對總稱之符號追加記號而表示個別或特定之部位之情形。又，於以下之實施形態中，除了特別必要時以外，原則上並不重複同一或同樣之部分之說明。 Hereinafter, embodiments will be described in detail based on the drawings. In the drawings, the same or similar reference numerals will be given to the members having the same functions, and the repeated description thereof will be omitted. Further, when there are a plurality of similar members (parts), there is a case where a symbol is added to the general name to indicate an individual or a specific portion. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle unless it is particularly necessary.

又，於實施形態中所使用之圖式中，即使是剖視圖，亦存在為了使圖式易於觀看而省略影線之情形。又，即使是俯視圖，亦存在為了使圖式易於觀看而標註影線之情形。 Further, in the drawings used in the embodiment, even in the cross-sectional view, there is a case where the hatching is omitted in order to make the drawing easy to see. Further, even in a plan view, there is a case where a hatch is marked in order to make the drawing easy to see.

又，於剖視圖及俯視圖中，各部位之大小並不與實際器件(device)對應，存在為了使圖式易懂而相對放大地表示特定部位之情形。又，於剖視圖與俯視圖對應之情形時，亦存在為了使圖式易懂而相對放大地表示特定部位之情形。 Further, in the cross-sectional view and the plan view, the size of each part does not correspond to an actual device, and there is a case where a specific portion is relatively enlarged in order to make the drawing easy to understand. Further, in the case where the cross-sectional view corresponds to the plan view, there is a case where the specific portion is relatively enlarged in order to make the drawing easy to understand.

(實施形態1) (Embodiment 1)

以下，一面參照圖式一面對本實施形態之半導體裝置加以詳細 說明。 Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to FIG. Description.

[構造說明] [structural description]

圖1係表示本實施形態之半導體裝置之構成之剖視圖。圖1中所示之半導體裝置係使用氮化物半導體之MIS(Metal Insulator Semiconductor，金屬絕緣半導體)型之場效電晶體(FET；Field Effect Transistor)。圖1係示意性地表示例如由圖2之虛線所圍之矩形部分之構成之圖。圖2係表示本實施形態之半導體裝置之其他構成之剖視圖。關於如圖2所示之半導體裝置，藉由實施形態2而加以詳細說明。圖3係表示本實施形態之半導體裝置之比較例1之構成之剖視圖。圖4係表示本實施形態之半導體裝置之比較例2之構成之剖視圖。 Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device of the embodiment. The semiconductor device shown in FIG. 1 is a MIS (Metal Insulator Semiconductor) type field effect transistor (FET). Fig. 1 is a view schematically showing the configuration of a rectangular portion surrounded by a broken line of Fig. 2, for example. Fig. 2 is a cross-sectional view showing another configuration of the semiconductor device of the embodiment. The semiconductor device shown in FIG. 2 will be described in detail by the second embodiment. Fig. 3 is a cross-sectional view showing the configuration of a comparative example 1 of the semiconductor device of the embodiment. Fig. 4 is a cross-sectional view showing the configuration of a comparative example 2 of the semiconductor device of the embodiment.

如圖1所示，於本實施形態之半導體裝置中，包含介隔閘極絕緣膜GI配置於包含氮化物半導體之通道層CH上之閘極電極GE。 As shown in FIG. 1, the semiconductor device of the present embodiment includes a gate electrode GE in which a barrier gate insulating film GI is disposed on a channel layer CH including a nitride semiconductor.

此處，閘極絕緣膜GI包含形成於通道層CH上之第1閘極絕緣膜GIa、與形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。又，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、與形成於第1閘極電極GEa上之第2閘極電極GEb。 Here, the gate insulating film GI includes the first gate insulating film GIa formed on the channel layer CH and the second gate insulating film GIb formed on the first gate insulating film GIa. Further, the gate electrode GE includes a first gate electrode GEa formed on the second gate insulating film GIb and a second gate electrode GEb formed on the first gate electrode GEa.

以下，關於閘極絕緣膜GI(GIa、GIb)及閘極電極GE(GEa、GEb)而加以說明。 Hereinafter, the gate insulating film GI (GIa, GIb) and the gate electrode GE (GEa, GEb) will be described.

如上所述，閘極絕緣膜GI包含形成於通道層CH上之第1閘極絕緣膜GIa、與形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。第1閘極絕緣膜GIa包含第1金屬之氧化物(含有第1金屬之氧化物、第1金屬之氧化膜)。第2閘極絕緣膜GIb包含第2金屬之氧化物(含有第2金屬之氧化物、第2金屬之氧化膜)。並且，第2金屬之陰電性低於第1金屬之陰電性。 As described above, the gate insulating film GI includes the first gate insulating film GIa formed on the channel layer CH and the second gate insulating film GIb formed on the first gate insulating film GIa. The first gate insulating film GIa includes an oxide of the first metal (containing an oxide of the first metal and an oxide film of the first metal). The second gate insulating film GIb includes an oxide of the second metal (including an oxide of the second metal and an oxide film of the second metal). Further, the cathode of the second metal is lower than the cathode of the first metal.

又，第1閘極絕緣膜GIa並非對通道層(氮化物半導體)CH進行熱氧化而形成之膜，而是藉由所謂堆積法(沈積法)而形成之膜。 Further, the first gate insulating film GIa is not a film formed by thermally oxidizing the channel layer (nitride semiconductor) CH, but is formed by a so-called deposition method (deposition method).

第1金屬例如為鋁(Al)。於此情形時，第1金屬之氧化物成為氧化鋁(Al2O3)。 The first metal is, for example, aluminum (Al). In this case, the oxide of the first metal becomes alumina (Al 2 O 3 ).

第2金屬係選自Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上之元素。於此情形時，第2金屬之氧化物例如成為氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鉭(Ta2O5)、氧化鈦(TiO2)、氧化鈮(Nb2O5)、氧化鑭(La2O3)、氧化釔(Y2O3)、氧化鎂(MgO)。第2金屬與氧之組成比並不限於上述者。又，作為第2金屬，亦可包含2種以上之元素。於此情形時，成為2種金屬與氧之化合物。其中，於此情形時，必須2種以上元素之陰電性均低於第1金屬之陰電性。然而，含有雜質程度之金屬(例如0.01%濃度以下之金屬)於製造上不可避免，因此存在不論陰電性之大小為多少均含有雜質程度之金屬之情況。 The second metal is one or more elements selected from the group consisting of Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. In this case, the oxide of the second metal is, for example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), or antimony oxide (Nb 2 O 5 ). ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO). The composition ratio of the second metal to oxygen is not limited to the above. Further, as the second metal, two or more elements may be contained. In this case, it is a compound of two kinds of metals and oxygen. In this case, it is necessary that the cathode electrical properties of the two or more elements are lower than the cathode electrical properties of the first metal. However, a metal containing a degree of impurities (for example, a metal having a concentration of 0.01% or less) is unavoidable in production, and therefore there is a case where a metal having a degree of impurities is contained regardless of the size of the anion.

如上所述，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、與形成於第1閘極電極GEa上之第2閘極電極GEb。 As described above, the gate electrode GE includes the first gate electrode GEa formed on the second gate insulating film GIb and the second gate electrode GEb formed on the first gate electrode GEa.

第1閘極電極GEa係第3金屬之氮化物。作為第3金屬，可使用Ti、Ta、W等。於此情形時，第3金屬之氮化物(含有第3金屬之氮化物、第3金屬之氮化膜)成為TiN、TaN、WN。作為第3金屬，較佳為具有導電性、加工性高、氧之吸收性或供給性低之金屬。於此方面而言，作為第3金屬，較佳為使用Ti。 The first gate electrode GEa is a nitride of a third metal. As the third metal, Ti, Ta, W, or the like can be used. In this case, the nitride of the third metal (the nitride containing the third metal and the nitride film of the third metal) is TiN, TaN, and WN. As the third metal, a metal having high conductivity, high workability, and low oxygen absorption or supply property is preferable. In this regard, as the third metal, Ti is preferably used.

第2閘極電極GEb包含第4金屬。作為第4金屬，可使用W、Ru、Ir。作為第4金屬，較佳為即使於氧化後亦具有導電性、加工性高、阻擋氧向下層之第1閘極電極GEa滲入者。於此方面而言，作為第4金屬，較佳為使用W。 The second gate electrode GEb includes a fourth metal. As the fourth metal, W, Ru, and Ir can be used. As the fourth metal, it is preferable to have conductivity, high workability even after oxidation, and to infiltrate the first gate electrode GEa which blocks the lower layer of oxygen. In this regard, as the fourth metal, W is preferably used.

如上所述，作為閘極絕緣膜GI，積層使用陰電性不同之第1金屬及第2金屬之各自之氧化物，於上層配置陰電性低之第2金屬之氧化膜，因此能夠使閾值電壓(Vth)為正(Vth>0)(閘極絕緣膜之積層效果)。 As described above, as the gate insulating film GI, oxides of the first metal and the second metal having different anisoelectric properties are laminated, and an oxide film of the second metal having a low cathode property is disposed in the upper layer, so that the threshold value can be set. The voltage (Vth) is positive (Vth>0) (layering effect of the gate insulating film).

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，於上層配置第4金屬，因此能夠防止氧向閘極絕緣膜GI擴散，減低閾值電壓(Vth)之不均一。特別是即使經過後述之退火處理，亦能夠減低氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is placed on the upper layer. Therefore, it is possible to prevent oxygen from diffusing into the gate insulating film GI and to reduce the unevenness of the threshold voltage (Vth). . In particular, even after the annealing treatment described later, it is possible to reduce the diffusion of oxygen and maintain the layering effect of the gate insulating film.

作為第3金屬之氮化膜(MN)，較佳為第3金屬(M)與氮(N)之比(化學計量比)N/M為1以上。如上所述，藉由使第3金屬(M)與氮(N)之比(化學計量比)N/M大於1(富氮)，能夠於可於晶粒與晶粒之間的晶界(grain boundary)產生之懸鍵上鍵結氮(N)，減低與氧之反應性(亦稱為氧之引入)。第3金屬(M)與氮(N)之比例如可藉由XPS(X-ray Photoelectron Spectroscopy，X射線光電子光譜法)而測定。根據本發明者之研究，於使用氮化鈦膜(TiN膜)作為第3金屬之氮化膜(MN)之情形時，TiN之Ti與N之比N/Ti最大可設為1.2左右。因此，較佳為1<N/Ti≦1.2。 As the nitride film (MN) of the third metal, the ratio (stoichiometric ratio) N/M of the third metal (M) to nitrogen (N) is preferably 1 or more. As described above, by making the ratio (stoichiometric ratio) N/M of the third metal (M) to nitrogen (N) larger than 1 (nitrogen-rich), it is possible to form grain boundaries between crystal grains and crystal grains ( Grain boundary) The nitrogen bond (N) is bonded to the dangling bond to reduce the reactivity with oxygen (also known as the introduction of oxygen). The ratio of the third metal (M) to nitrogen (N) can be measured, for example, by XPS (X-ray Photoelectron Spectroscopy). According to the study of the present inventors, when a titanium nitride film (TiN film) is used as the nitride film (MN) of the third metal, the ratio of Ti to N of TiN, N/Ti, can be set to about 1.2 at the maximum. Therefore, it is preferably 1 < N / Ti ≦ 1.2.

作為第4金屬之膜厚，較佳為50nm以上。第4金屬如上所述具有防止氧自閘極電極GE之表面向第1閘極電極GEa擴散之作用。若將50nm左右之膜厚之第4金屬(第2閘極電極GEb)積層於第1閘極電極GEa上，則能夠將閘極電極GE之表面之氧濃度於第1閘極電極GEa之表面降低1位左右。因此，藉由將第4金屬(例如鎢膜(W膜))之膜厚設為50nm以上，能夠有效地抑制氧向第1閘極電極GEa擴散。 The film thickness of the fourth metal is preferably 50 nm or more. As described above, the fourth metal has a function of preventing oxygen from diffusing from the surface of the gate electrode GE to the first gate electrode GEa. When the fourth metal (second gate electrode GEb) having a film thickness of about 50 nm is laminated on the first gate electrode GEa, the oxygen concentration on the surface of the gate electrode GE can be made on the surface of the first gate electrode GEa. Lower about 1 bit. Therefore, by setting the film thickness of the fourth metal (for example, the tungsten film (W film)) to 50 nm or more, it is possible to effectively suppress the diffusion of oxygen to the first gate electrode GEa.

例如，於以單層使用氧化鋁膜作為閘極絕緣膜GI之比較例1(圖3)之情形時，閾值電壓(Vth)成為負(Vth<0)。若閾值電壓(Vth)成為負(Vth<0)，則成為常導通狀態。相對於此，如圖4中所示之比較例2般，於閘極絕緣膜GI中，使用氧化鋁(Al2O3)作為第1閘極絕緣膜GIa，使用氧化鉿(HfO2)作為其上層之第2閘極絕緣膜GIb之情形時，Hf之陰電性低於Al，因此能夠使閾值電壓(Vth)為正(Vth>0)(閘極絕緣膜之積層效果)。 For example, in the case of Comparative Example 1 (FIG. 3) in which a single-layer aluminum oxide film is used as the gate insulating film GI, the threshold voltage (Vth) becomes negative (Vth<0). When the threshold voltage (Vth) becomes negative (Vth<0), it becomes a normally-on state. On the other hand, in the gate insulating film GI, alumina (Al 2 O 3 ) was used as the first gate insulating film Gia, and hafnium oxide (HfO 2 ) was used as the gate insulating film GI. In the case of the second gate insulating film GIb of the upper layer, since the cathode electrical property of Hf is lower than that of Al, the threshold voltage (Vth) can be made positive (Vth>0) (layering effect of the gate insulating film).

其係由於藉由Al2O3與HfO2之積層將閘極絕緣膜中之氧之電子牽引至陰電性高之元素側的極化效果所達成。亦即，與該極化對應，平帶電壓Vfb變大(成為正(Vfb>0))，與該平帶電壓Vfb對應，能夠使閾值電壓(Vth)為正(Vth>0)。 This is achieved by the fact that the electrons of oxygen in the gate insulating film are pulled to the element side of the element having high electronegativity by the lamination of Al 2 O 3 and HfO 2 . In other words, in response to the polarization, the flat band voltage Vfb becomes large (becomes positive (Vfb>0)), and the threshold voltage (Vth) can be made positive (Vth>0) in accordance with the flat band voltage Vfb.

然而，根據本發明者之研究，於形成較閘極絕緣膜(Al2O3與HfO2)更上之層(例如閘極電極或配線(包括源極電極、汲極電極))時，由於成膜時所產生之電漿或荷電粒子，於閘極絕緣膜(Al2O3與HfO2)中施加損傷而可能產生陷阱(陷阱能階、缺陷)。有時將此種損傷稱為充電損傷(charge-up damage)。特別是於藉由PVD法(濺鍍法等)而形成較閘極絕緣膜(Al2O3與HfO2)更上之層之情形時，對閘極絕緣膜(Al2O3與HfO2)施加之損傷大，由於該陷阱(陷阱能階、缺陷)之影響，閾值電壓(Vth)降低(Vth<0)。 However, according to the study of the present inventors, when forming a layer higher than the gate insulating film (Al 2 O 3 and HfO 2 ) (for example, a gate electrode or a wiring (including a source electrode, a drain electrode)), The plasma or charged particles generated during film formation damage the gate insulating film (Al 2 O 3 and HfO 2 ) and may cause traps (trap levels, defects). This type of damage is sometimes referred to as charge-up damage. Particularly in by a PVD method (sputtering method) and a gate insulating film is formed more (2 O 3 Al and HfO 2) on the case of more layers, a gate insulating film of the gate (Al 2 O 3 and HfO 2 The applied damage is large, and the threshold voltage (Vth) is lowered (Vth < 0) due to the influence of the trap (trap level, defect).

因此，關於該損傷之恢復、亦即陷阱(陷阱能階、缺陷)之減低，有效的是熱處理(亦稱為退火、退火處理、後退火、恢復退火)。亦即，藉由於形成較閘極絕緣膜(Al2O3與HfO2)更上之層(例如閘極電極或配線(包括源極電極、汲極電極))後實施熱處理，能夠使閾值電壓(Vth)再次上升，從而使其為正(Vth>0)。 Therefore, regarding the recovery of the damage, that is, the reduction of the trap (trap level, defect), heat treatment (also referred to as annealing, annealing treatment, post-annealing, recovery annealing) is effective. That is, the threshold voltage can be made by performing heat treatment after forming a layer higher than the gate insulating film (Al 2 O 3 and HfO 2 ) (for example, a gate electrode or a wiring (including a source electrode, a drain electrode)) (Vth) rises again, making it positive (Vth>0).

然而，根據本發明者之實驗可判明：平帶電壓Vfb既存在恢復至Vfb>0者，亦存在停留於Vfb<0者，於恢復之程度上存在不均一。 However, according to experiments by the inventors, it can be found that the flat band voltage Vfb has both recovery to Vfb>0, and there is also a stay in Vfb<0, and there is unevenness in the degree of recovery.

本發明者關於上述平帶電壓Vfb之恢復程度之不均一，對其原因進行了銳意研究，作為用以尋求原因之實驗之一，使用上述比較例2(圖4)之半導體裝置進行了如下所述之實驗。作為器件1，製作如下者：將第1閘極絕緣膜(Al2O3)GIa與第2閘極絕緣膜(HfO2)GIb積層，其後於惰性氣體中添加有氧之氛圍下進行退火，藉由電阻加熱真空蒸鍍法形成Au而作為閘極絕緣膜GI上之閘極電極GE。並且，作為器件2，製作如下者：將第1閘極絕緣膜GIa與第2閘極絕緣膜GIb積層，於僅為 惰性氣體之氛圍下進行退火，藉由電阻加熱真空蒸鍍法形成Au而作為閘極絕緣膜GI上之閘極電極GE。再者，於Au之蒸鍍時，使用金屬遮罩(蔽蔭遮罩)形成閘極電極。藉由此種Au之蒸鍍，能夠避免充電損傷之影響，且能夠驗證退火氛圍中之氧之影響。 The inventors of the present invention conducted intensive studies on the degree of recovery of the above-mentioned flat-band voltage Vfb, and conducted research on the cause thereof. As one of the experiments for seeking the cause, the semiconductor device of Comparative Example 2 (Fig. 4) was used as follows. The experiment described. As the device 1, a first gate insulating film (Al 2 O 3 ) Gia and a second gate insulating film (HfO 2 ) GIb are laminated, and then annealed in an atmosphere in which an inert gas is added with oxygen. Au is formed as a gate electrode GE on the gate insulating film GI by resistance heating vacuum evaporation. Further, as the device 2, the first gate insulating film GIa and the second gate insulating film GIb are laminated, and annealed in an atmosphere of only an inert gas, and Au is formed by resistance heating vacuum deposition. As the gate electrode GE on the gate insulating film GI. Further, in the vapor deposition of Au, a gate electrode is formed using a metal mask (shading mask). By such vapor deposition of Au, the influence of charging damage can be avoided, and the influence of oxygen in the annealing atmosphere can be verified.

測定器件1及器件2之C-V特性，調查Vfb。其結果，於惰性氣體中添加有氧之氛圍下進行退火之器件1中，平帶電壓Vfb停留為Vfb<0。另一方面，於僅為惰性氣體之氛圍下進行退火之器件2中，平帶電壓Vfb恢復至Vfb>0。 The C-V characteristics of Device 1 and Device 2 were measured, and Vfb was investigated. As a result, in the device 1 which is annealed in an atmosphere in which an inert gas is added with oxygen, the flat band voltage Vfb stays at Vfb < 0. On the other hand, in the device 2 which is annealed in an atmosphere of only an inert gas, the flat band voltage Vfb is restored to Vfb >

根據包含以上實驗之各種研究可判明：由於退火氛圍中之氧，形成於第1閘極絕緣膜GIa與第2閘極絕緣膜GIb界面之氧之極化被破壞、或其程度減低，基於該極化效果之平帶電壓Vfb之偏移效果減低。 According to various studies including the above experiments, it is found that the polarization of oxygen formed at the interface between the first gate insulating film GIa and the second gate insulating film GIb is destroyed due to oxygen in the annealing atmosphere, or the degree is reduced. The offset effect of the flat band voltage Vfb of the polarization effect is reduced.

特別是於閘極電極GE中使用TiN之情形時，若於成膜後暫時取出至空氣中而進行退火，則進入至TiN膜之氧、或TiN膜之表面所吸附之氧擴散至膜中。又，進入至TiN膜之水分子亦擴散至膜中。於此種TiN膜中擴散之氧(氧元素)破壞閘極絕緣膜中所形成之上述極化，使該極化效果變無。 In particular, when TiN is used for the gate electrode GE, if it is temporarily taken out into the air after the film formation and annealed, the oxygen which has entered the TiN film or the oxygen adsorbed on the surface of the TiN film diffuses into the film. Further, water molecules entering the TiN film also diffuse into the film. The oxygen (oxygen element) diffused in such a TiN film destroys the above-described polarization formed in the gate insulating film, so that the polarization effect becomes unnecessary.

相對於此，根據本實施形態之半導體裝置(圖1)，由於積層使用含有第3金屬之氮化物及第4金屬作為閘極電極GE，且於上層配置第4金屬，因此能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。藉此，能夠使閾值電壓(Vth)為正(Vth>0)。又，能夠矯正閾值電壓(Vth)之不均一。特別是即使於形成閘極絕緣膜GI後實施退火處理(例如500℃以上之熱處理)之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 On the other hand, in the semiconductor device (FIG. 1) of the present embodiment, since the nitride containing the third metal and the fourth metal are used as the gate electrode GE, and the fourth metal is disposed on the upper layer, the oxygen gate can be prevented. The pole insulating film GI diffuses, maintains the polarization of oxygen (the layering effect of the gate insulating film), and maintains the offset effect of the flat band voltage Vfb. Thereby, the threshold voltage (Vth) can be made positive (Vth>0). Moreover, the unevenness of the threshold voltage (Vth) can be corrected. In particular, even when an annealing treatment (for example, heat treatment at 500 ° C or higher) is performed after the gate insulating film GI is formed, the diffusion of oxygen due to the annealing treatment can be reduced, and the effect of laminating the gate insulating film can be maintained.

其次，關於第2閘極電極GEb之氧擴散之抑制效果加以說明。作為 用以驗證該氧擴散之抑制效果之實驗之一，進行如下所述之實驗。 Next, the effect of suppressing the oxygen diffusion of the second gate electrode GEb will be described. As One of the experiments for verifying the inhibitory effect of the oxygen diffusion was carried out as described below.

作為樣品1(TiN(as))，藉由濺鍍法於Si基板上形成TiN膜。又，作為樣品2(TiN(anneal))，藉由濺鍍法於Si基板上形成TiN膜，於與上述恢復退火相當之條件下對該TiN膜進行退火。 As Sample 1 (TiN(as)), a TiN film was formed on the Si substrate by sputtering. Further, as a sample 2 (TiN (anneal)), a TiN film was formed on the Si substrate by sputtering, and the TiN film was annealed under the conditions corresponding to the above-described recovery annealing.

又，作為樣品3(W/TiN(as))，藉由濺鍍法於Si基板上形成TiN膜，連續地於TiN膜上形成W膜。又，作為樣品4(TiN(anneal))，藉由濺鍍法於Si基板上形成TiN膜，連續地於TiN膜上形成W膜，於與上述恢復退火相當之條件下對該TiN膜與W膜之積層膜進行退火。 Further, as a sample 3 (W/TiN(as)), a TiN film was formed on the Si substrate by a sputtering method, and a W film was continuously formed on the TiN film. Further, as a sample 4 (TiN (anneal)), a TiN film was formed on the Si substrate by sputtering, and a W film was continuously formed on the TiN film, and the TiN film and the W were formed under the conditions equivalent to the above-described recovery annealing. The laminated film of the film is annealed.

測定該等樣品(樣品1~樣品4)中之氧濃度分佈。於測定中使用SIMS(Secondary Ion Mass Spectrometry，次級離子質譜分析)法。 The oxygen concentration distribution in the samples (samples 1 to 4) was measured. A SIMS (Secondary Ion Mass Spectrometry) method was used for the measurement.

於圖5中表示各樣品中之氧濃度分佈。圖5(a)係一併記載4個樣品(樣品1~4)之氧濃度之曲線圖者，圖5(b)係僅僅記載樣品1、2之曲線圖者，圖5(c)係僅僅記載樣品3、4之曲線圖者。圖5之橫軸為深度(Depth、[nm])，縱軸為氧濃度(Oxygen concentration、[atoms/cm3])。例如1.0E+17表示1.0×1017。再者，於圖5之TiN膜(樣品1、2)中，錯開W膜之膜厚部分(90nm左右)而表記深度之起點。又，於深度為120nm之位置、亦即與TiN膜與Si基板之邊界對應之位置所確認之峰值係由Si基板上之自然氧化膜引起。 The oxygen concentration distribution in each sample is shown in FIG. Fig. 5(a) is a graph showing the oxygen concentration of four samples (samples 1 to 4), and Fig. 5(b) shows only the graphs of samples 1 and 2, and Fig. 5(c) is only The graphs of the samples 3 and 4 are recorded. The horizontal axis of Fig. 5 is the depth (Depth, [nm]), and the vertical axis is the oxygen concentration (Oxygen concentration, [atoms/cm 3 ]). For example, 1.0E+17 means 1.0×10 17 . Further, in the TiN film (samples 1 and 2) of Fig. 5, the film thickness portion (about 90 nm) of the W film was shifted to indicate the starting point of the depth. Further, the peak value at a position having a depth of 120 nm, that is, a position corresponding to the boundary between the TiN film and the Si substrate is caused by a natural oxide film on the Si substrate.

如圖5(a)、(b)所示，與樣品1(TiN(as))相比而言，於樣品2(TiN(anneal))中，TiN膜中之氧濃度變高(參照箭頭a部)。相對於此，如圖5(a)、(c)所示，於樣品3(W/TiN(as))及樣品4(W/TiN(anneal))中，雖然W膜中之氧濃度變高(參照箭頭b部)，但於W膜之下方之深度75nm以後(參照c部)，樣品3、4之曲線圖重疊，無法確認氧濃度上升。又，於樣品3、4中，與樣品1、2之情形相比而言，TiN膜表面之氧濃度被抑製得較低。 As shown in Fig. 5 (a) and (b), in the sample 2 (TiN (anneal)), the oxygen concentration in the TiN film becomes higher as compared with the sample 1 (TiN (as)) (refer to the arrow a). unit). On the other hand, as shown in FIGS. 5( a ) and ( c ), in sample 3 (W/TiN(as)) and sample 4 (W/TiN (anneal)), although the oxygen concentration in the W film becomes high. (Refer to the arrow b), but after the depth of the W film is 75 nm or later (see the c portion), the graphs of the samples 3 and 4 overlap, and the increase in the oxygen concentration cannot be confirmed. Further, in the samples 3 and 4, the oxygen concentration on the surface of the TiN film was suppressed to be lower than in the case of the samples 1 and 2.

根據上述結果可判明：於採用本實施形態之積層閘極電極構造 之樣品3、4中，第2閘極電極GEb表面所吸附之氧或水分子即使於退火後亦不擴散至作為第1閘極電極GEa之TiN膜。藉此，能夠維持由閘極絕緣膜GI內所形成之極化所帶來的平帶電壓Vfb之偏移效果。 According to the above results, it is found that the laminated gate electrode structure of the present embodiment is employed. In the samples 3 and 4, the oxygen or water molecules adsorbed on the surface of the second gate electrode GEb did not diffuse to the TiN film as the first gate electrode GEa even after annealing. Thereby, the effect of shifting the flat band voltage Vfb due to the polarization formed in the gate insulating film GI can be maintained.

此處，關於用以防止氧向作為第1閘極電極GEa之TiN膜擴散的第2閘極電極GEb之膜厚進行研究。例如，於圖5中確認W膜之膜厚為50nm左右，氧濃度下降1位。認為若表面之氧濃度下降1位，則相當程度地抑制氧向TiN膜之擴散，因此關於第2閘極電極GEb之膜厚，認為若為50nm左右則充分有效。 Here, the film thickness of the second gate electrode GEb for preventing oxygen from diffusing into the TiN film as the first gate electrode GEa was examined. For example, in FIG. 5, it is confirmed that the film thickness of the W film is about 50 nm, and the oxygen concentration is lowered by one place. When the oxygen concentration on the surface is lowered by one, the diffusion of oxygen into the TiN film is suppressed to a certain extent. Therefore, the film thickness of the second gate electrode GEb is considered to be sufficiently effective at about 50 nm.

又，如上所述，藉由使TiN膜富氮，亦即，使TiN膜之Ti與N之比N/Ti大於1，能夠藉由氮(N)使可於晶界產生之懸鍵鈍化。藉此，能夠抑制暴露於大氣時之氧或水分子之吸附。另一方面，於TiN膜為富Ti之情形時，作為第2閘極電極GEb之HfO2等之氧向第1閘極電極GEa移動，於第2閘極電極GEb中產生氧缺陷(氧空位)。該氧空位具有正電荷，使平帶電壓Vfb向負側偏移。因此，於使TiN膜為富氮之情形時，能夠抑制此種平帶電壓Vfb向負側之偏移。 Further, as described above, by enriching the TiN film with nitrogen, that is, the Ti/N ratio N/Ti of the TiN film is larger than 1, the dangling bond which can be generated at the grain boundary can be passivated by nitrogen (N). Thereby, the adsorption of oxygen or water molecules when exposed to the atmosphere can be suppressed. On the other hand, when the TiN film is rich in Ti, oxygen such as HfO 2 as the second gate electrode GEb moves to the first gate electrode GEa, and oxygen deficiency (oxygen vacancies) is generated in the second gate electrode GEb. ). The oxygen vacancies have a positive charge, causing the flat band voltage Vfb to shift toward the negative side. Therefore, when the TiN film is made nitrogen-rich, the shift of the flat band voltage Vfb to the negative side can be suppressed.

[製法說明] [Method Description]

其次，參照圖6~圖11對本實施形態之半導體裝置之製造方法加以說明，且使該半導體裝置之構成更明確。圖6~圖11係表示本實施形態之半導體裝置之製造步驟之剖視圖。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 6 to 11, and the configuration of the semiconductor device will be further clarified. 6 to 11 are cross-sectional views showing the steps of manufacturing the semiconductor device of the embodiment.

如圖6所示，準備形成有通道層CH之基板。通道層CH係氮化物半導體層，例如使用氮化鎵層(GaN層)。作為基板，使用GaN基板，亦可將該基板作為通道層CH而使用。又，亦可於Si基板等支持基板上形成GaN層。例如，使用有機金屬化學氣相沈積(MOCVD：Metal Organic Chemical Vapor Deposition)法等，於Si基板上異質磊晶生長i-GaN層。此時，並不刻意地進行雜質摻雜而使其生長。 As shown in FIG. 6, a substrate on which the channel layer CH is formed is prepared. The channel layer CH is a nitride semiconductor layer, and for example, a gallium nitride layer (GaN layer) is used. A GaN substrate is used as the substrate, and the substrate can also be used as the channel layer CH. Further, a GaN layer may be formed on a support substrate such as a Si substrate. For example, an i-GaN layer is heteroepitaxially grown on a Si substrate using a metal organic chemical vapor deposition (MOCVD) method or the like. At this time, impurity doping is not intentionally carried out to grow it.

首先，使用稀釋HCl溶液等對通道層(i-GaN層、GaN基板)CH之 表面進行清洗。其次，於通道層CH上形成包含第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之閘極絕緣膜GI。 First, use a diluted HCl solution or the like for the channel layer (i-GaN layer, GaN substrate) CH The surface is cleaned. Next, a gate insulating film GI including the first gate insulating film GIa and the second gate insulating film GIb is formed on the channel layer CH.

首先，如圖7所示，於通道層CH上形成第1閘極絕緣膜(第1金屬之氧化膜)GIa。例如，作為第1閘極絕緣膜GIa，使用堆積法堆積氧化鋁膜(Al2O3膜)。例如，將三甲基鋁(Al(CH3)3、TMA)及H2O(氧化劑)作為原料氣體，於400℃之氛圍中，使用ALD(Atomic Layer Deposition，原子層沈積)法堆積50nm~100nm左右之膜厚之氧化鋁膜(Al2O3膜)。藉由ALD法，能夠控制性、被覆性良好地形成膜質良好之膜。再者，作為氧化劑，除了H2O以外，亦可使用臭氧(O3)。再者，除了ALD法以外，亦可使用氧電漿CVD法形成氧化鋁膜(Al2O3膜)。 First, as shown in FIG. 7, a first gate insulating film (an oxide film of a first metal) GMa is formed on the channel layer CH. For example, as the first gate insulating film GIa, an aluminum oxide film (Al 2 O 3 film) is deposited by a deposition method. For example, trimethylaluminum (Al(CH 3 ) 3 , TMA) and H 2 O (oxidant) are used as raw material gases, and stacked in an atmosphere of 400 ° C using an ALD (Atomic Layer Deposition) method. An aluminum oxide film (Al 2 O 3 film) having a film thickness of about 100 nm. By the ALD method, it is possible to form a film having a good film quality with good controllability and coating properties. Further, as the oxidizing agent, ozone (O 3 ) may be used in addition to H 2 O. Further, in addition to the ALD method, an aluminum oxide film (Al 2 O 3 film) may be formed by an oxy-plasma CVD method.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第1閘極絕緣膜GIa(此處為氧化鋁膜)中之陷阱(陷阱能階、缺陷)。特別是於藉由堆積法於GaN上形成氧化鋁之情形時，膜中之陷阱密度變高，屢次看到電容-電壓特性(C-V特性)之遲滯。該C-V特性之遲滯係指例如一面將電壓自-10V提高至+10V一面測定之C-V波形、與一面將電壓自+10V降低至-10V一面測定之C-V波形並不相同，波形並不重疊。因此，藉由實施熱處理，能夠減低陷阱密度，改善遲滯。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the first gate insulating film GIa (here, the aluminum oxide film) can be reduced. In particular, when the aluminum oxide is formed on the GaN by the deposition method, the trap density in the film becomes high, and the hysteresis of the capacitance-voltage characteristic (CV characteristic) is repeatedly seen. The hysteresis of the CV characteristic means that, for example, the CV waveform measured while increasing the voltage from -10 V to +10 V is not the same as the CV waveform measured while reducing the voltage from +10 V to -10 V, and the waveforms do not overlap. Therefore, by performing heat treatment, the trap density can be reduced and the hysteresis can be improved.

其次，如圖8所示，於第1閘極絕緣膜GIa(此處為氧化鋁膜)上，例如形成氧化鉿膜(HfO2膜)作為第2閘極絕緣膜(第2金屬之氧化膜)GIb。例如，藉由使用Hf金屬靶、及氬(Ar)與氧(O2)之混合氣體之反應性濺鍍法，堆積氧化鉿膜。 Next, as shown in FIG. 8, on the first gate insulating film GIa (here, an aluminum oxide film), for example, a hafnium oxide film (HfO 2 film) is formed as a second gate insulating film (an oxide film of the second metal). ) GIb. For example, a ruthenium oxide film is deposited by a reactive sputtering method using a Hf metal target and a mixed gas of argon (Ar) and oxygen (O 2 ).

氧化鉿膜之膜厚例如可於1~10nm左右之範圍內調整。其中，根據本發明者之研究，即使為2~3nm之膜厚，亦能夠藉由上述氧之極化獲得充分之平帶電壓Vfb之偏移效果。反應性濺鍍法係PVD法之 一種。於形成第2閘極絕緣膜GIb時，除了PVD(Physical Vapor Deposition，物理氣相沈積)法以外，亦可使用ALD法或CVD法。 The film thickness of the ruthenium oxide film can be adjusted, for example, in the range of about 1 to 10 nm. According to the study by the inventors of the present invention, even if the film thickness is 2 to 3 nm, the effect of shifting the sufficient flat band voltage Vfb can be obtained by the polarization of the oxygen. Reactive sputtering method is PVD method One. When the second gate insulating film GIb is formed, an ALD method or a CVD method may be used in addition to the PVD (Physical Vapor Deposition) method.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，第2閘極絕緣膜GIb(此處為氧化鉿膜)中之陷阱(陷阱能階、缺陷)減少。再者，於上述步驟中，個別地進行第1閘極絕緣膜GIa(氧化鋁膜)之形成後之熱處理、第2閘極絕緣膜GIb(氧化鉿膜)之形成後之熱處理，但亦可省略第1閘極絕緣膜GIa之形成後之熱處理，於形成第1閘極絕緣膜GIa(氧化鋁膜)與第2閘極絕緣膜GIb(氧化鉿膜)之積層膜後一次性進行熱處理。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the second gate insulating film GIb (here, the hafnium oxide film) is reduced. Further, in the above step, the heat treatment after the formation of the first gate insulating film GIa (aluminum oxide film) and the heat treatment after the formation of the second gate insulating film GIb (yttrium oxide film) are performed individually, but may be performed. The heat treatment after the formation of the first gate insulating film GIa is omitted, and the laminated film of the first gate insulating film GIa (aluminum oxide film) and the second gate insulating film GIb (yttria film) is formed and heat-treated at one time.

如此般，形成包含第1閘極絕緣膜GIa(氧化鋁膜)與第2閘極絕緣膜GIb(氧化鉿膜)之積層膜之閘極絕緣膜GI。 In this manner, the gate insulating film GI including the laminated film of the first gate insulating film GIa (aluminum oxide film) and the second gate insulating film GIb (yttria film) is formed.

其次，於閘極絕緣膜GI上形成閘極電極GE。例如，如圖9及圖10所示般，形成氮化鈦膜(TiN膜)作為第1閘極電極GEa，進而於其上形成鎢膜(W膜)作為第2閘極電極GEb。例如，藉由使用Ti金屬靶、及氬(Ar)與氮(N2)之混合氣體之反應性濺鍍法，於第2閘極絕緣膜GIb上堆積20nm左右之氮化鈦膜。繼而，如圖10所示般，藉由使用W金屬靶、氬(Ar)氣體之濺鍍法，於第1閘極電極GEa上堆積100nm左右之鎢膜。較佳為於TiN膜之成膜步驟與W膜之成膜步驟之間不暴露於空氣中，而連續地進行該等步驟。藉由於TiN膜之成膜裝置與W膜之成膜裝置之間進行真空搬送，能夠在不暴露於空氣下而進行連續之成膜。作為成膜方法，除了如上述濺鍍法般之PVD法以外，亦可使用ALD法或CVD法。又，於形成第2閘極絕緣膜GIb時，亦不限定於PVD法。 Next, a gate electrode GE is formed on the gate insulating film GI. For example, as shown in FIGS. 9 and 10, a titanium nitride film (TiN film) is formed as the first gate electrode GEa, and a tungsten film (W film) is formed thereon as the second gate electrode GEb. For example, a titanium nitride film of about 20 nm is deposited on the second gate insulating film GIb by a reactive sputtering method using a Ti metal target and a mixed gas of argon (Ar) and nitrogen (N 2 ). Then, as shown in FIG. 10, a tungsten film of about 100 nm is deposited on the first gate electrode GEa by a sputtering method using a W metal target or an argon (Ar) gas. It is preferable that the steps are continuously performed without being exposed to the air between the film forming step of the TiN film and the film forming step of the W film. By performing vacuum transfer between the film forming apparatus of the TiN film and the film forming apparatus of the W film, continuous film formation can be performed without being exposed to the air. As the film formation method, in addition to the PVD method as in the above sputtering method, an ALD method or a CVD method can be used. Further, when the second gate insulating film GIb is formed, it is not limited to the PVD method.

其中，若使用多靶濺鍍裝置，則能夠容易地進行連續成膜。於該裝置中，於反應處理室內配置複數個靶，可藉由切換擋板而容易地變更膜種類。因此，裝置構成或製造步驟不會變得繁雜，能夠並不暴露於空氣中而進行連續之成膜，故適宜用於W膜/TiN膜之積層膜之形 成。 Among them, when a multi-target sputtering apparatus is used, continuous film formation can be easily performed. In this apparatus, a plurality of targets are disposed in the reaction processing chamber, and the type of film can be easily changed by switching the shutter. Therefore, the device configuration or the manufacturing steps are not complicated, and continuous film formation can be performed without being exposed to the air, so that it is suitable for the shape of the W film/TiN film. to make.

如上所述，藉由並不暴露於空氣中而進行連續之成膜，能夠減低被引入至第1閘極電極GEa之表面之氧量，而能夠抑制氧之擴散。其結果，能夠維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。 As described above, by continuously performing film formation without being exposed to the air, the amount of oxygen introduced to the surface of the first gate electrode GEa can be reduced, and diffusion of oxygen can be suppressed. As a result, the polarization of oxygen (the layering effect of the gate insulating film) can be maintained, and the effect of shifting the flat band voltage Vfb can be maintained.

又，如上所述，可確認若第2閘極電極(W膜)GEb之膜厚為50nm左右，則氧濃度下降1位，因此關於第2閘極電極(W膜)GEb之膜厚，較佳為50nm以上。又，於成膜第2閘極電極(W膜)GEb之後，將其暴露於大氣中，於以後之步驟中進行熱處理(恢復退火)之情形時，較佳為形成100nm以上之膜厚之W膜。又，第2閘極電極(W膜)GEb之膜厚之上限例如為500nm左右。 In addition, as described above, when the film thickness of the second gate electrode (W film) GEb is about 50 nm, the oxygen concentration is lowered by one bit, so that the film thickness of the second gate electrode (W film) GEb is higher. Good is 50nm or more. Further, after the second gate electrode (W film) GEb is formed and exposed to the atmosphere, and heat treatment (recovery annealing) is performed in the subsequent step, it is preferable to form a film thickness of 100 nm or more. membrane. Moreover, the upper limit of the film thickness of the second gate electrode (W film) GEb is, for example, about 500 nm.

其次，進行熱處理。該熱處理係用以減低由閘極電極GE之成膜時之電漿或荷電粒子所引起的閘極絕緣膜(Al2O3與HfO2)中之陷阱(陷阱能階、缺陷)之熱處理。作為熱處理條件，只要根據第1閘極電極GEa與第2閘極電極GEb之PVD條件(例如功率或時間)而選擇最適合之溫度、時間等即可。根據本發明者之研究，較佳為於溫度為400℃~600℃、時間為10分鐘~60分鐘之範圍內進行。又，作為熱處理氛圍，例如較佳為使用氮(N2)等惰性氣體之氛圍。 Next, heat treatment is performed. This heat treatment is for heat treatment for reducing traps (trap levels, defects) in the gate insulating film (Al 2 O 3 and HfO 2 ) caused by plasma or charged particles when the gate electrode GE is formed. As the heat treatment conditions, the most suitable temperature, time, and the like may be selected based on the PVD conditions (for example, power or time) of the first gate electrode GEa and the second gate electrode GEb. According to the study by the present inventors, it is preferably carried out at a temperature of from 400 ° C to 600 ° C for a period of from 10 minutes to 60 minutes. Further, as the heat treatment atmosphere, for example, an atmosphere of an inert gas such as nitrogen (N 2 ) is preferably used.

其次，如圖11所示，使用光微影技術及蝕刻技術，對氮化鈦膜與鎢膜之積層膜進行圖案化(加工)，藉此形成所期望之形狀之閘極電極GE(第1閘極電極GEa與第2閘極電極GEb)。第2閘極電極GEb覆蓋第1閘極電極GEa之整個上表面。再者，於該閘極電極GE之蝕刻時，亦可對下層之閘極絕緣膜GI進行蝕刻。又，上述熱處理亦可於該圖案化步驟之後進行。 Next, as shown in FIG. 11, a laminated film of a titanium nitride film and a tungsten film is patterned (processed) by using a photolithography technique and an etching technique, thereby forming a gate electrode GE having a desired shape (first Gate electrode GEa and second gate electrode GEb). The second gate electrode GEb covers the entire upper surface of the first gate electrode GEa. Further, in the etching of the gate electrode GE, the gate insulating film GI of the lower layer may be etched. Further, the above heat treatment may be performed after the patterning step.

如此般，形成包含第1閘極電極GEa與第2閘極電極GEb之積層膜之閘極電極GE。又，作為第1閘極電極GEa之材料，亦可使用容易閘 極蝕刻之例如TaN、WN等，作為第2閘極電極GEb，亦可使用例如Ru或Ir等。 In this manner, the gate electrode GE including the laminated film of the first gate electrode GEa and the second gate electrode GEb is formed. Moreover, as a material of the first gate electrode GEa, an easy gate can also be used. For the electrode etching, for example, TaN, WN, or the like, as the second gate electrode GEb, for example, Ru or Ir may be used.

如上所述，根據本實施形態，藉由將第1金屬之氧化膜與陰電性低於第1金屬之第2金屬之氧化膜積層而用作閘極絕緣膜，能夠使閾值電壓(Vth)向正方向偏移。 As described above, according to the present embodiment, the threshold voltage (Vth) can be obtained by using an oxide film of the first metal and an oxide film having a lower electrical property than the second metal of the first metal as a gate insulating film. Offset in the positive direction.

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬，因此能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，從而維持平帶電壓Vfb之偏移效果。藉此，能夠使閾值電壓(Vth)為正(Vth>0)。又，能夠矯正閾值電壓(Vth)之不均一。特別是即使於形成閘極絕緣膜GI之後實施退火處理之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is placed on the upper layer. Therefore, it is possible to prevent oxygen from diffusing into the gate insulating film GI and maintain polarization of oxygen (gate) The lamination effect of the insulating film) maintains the offset effect of the flat band voltage Vfb. Thereby, the threshold voltage (Vth) can be made positive (Vth>0). Moreover, the unevenness of the threshold voltage (Vth) can be corrected. In particular, even in the case where the annealing treatment is performed after the formation of the gate insulating film GI, the diffusion of oxygen due to the annealing treatment can be reduced, and the layering effect of the gate insulating film can be maintained.

又，於本實施形態中，對可將閘極絕緣膜及閘極電極應用為圖2中所示之半導體裝置之一部分之例進行了說明，但亦可將本實施形態之閘極絕緣膜及閘極應用於其他類型之半導體裝置中。於後述之實施形態2或實施形態6中說明此種應用例之一部分。 Further, in the present embodiment, an example in which the gate insulating film and the gate electrode can be applied to one portion of the semiconductor device shown in FIG. 2 has been described. However, the gate insulating film of the present embodiment and the gate insulating film of the present embodiment may be used. The gate is used in other types of semiconductor devices. A part of such an application example will be described in the second embodiment or the sixth embodiment to be described later.

(總結) (to sum up)

一面參照圖12，一面於以下總結說明本實施形態之半導體裝置之特徵性構成。圖12係表示本實施形態之半導體裝置之特徵性構成之剖視圖。 The characteristic configuration of the semiconductor device of the present embodiment will be briefly described below with reference to FIG. Fig. 12 is a cross-sectional view showing a characteristic configuration of the semiconductor device of the embodiment.

本實施形態之半導體裝置如圖12所示般包含介隔閘極絕緣膜GI形成於通道層(氮化物半導體)CH上之閘極電極GE。 As shown in FIG. 12, the semiconductor device of the present embodiment includes a gate electrode GE which is formed on a channel layer (nitride semiconductor) CH via a gate insulating film GI.

<關於閘極絕緣膜> <About gate insulating film>

閘極絕緣膜GI包含形成於通道層(氮化物半導體)CH上之第1金屬M1之氧化膜M1O、形成於氧化膜M1O上之第2金屬M2之氧化膜M2O。M1與O之組成比、M2與O之組成比自然根據所選擇之元素而變 化。 The gate insulating film GI includes an oxide film M1O of the first metal M1 formed on the channel layer (nitride semiconductor) CH, and an oxide film M2O of the second metal M2 formed on the oxide film M1O. The composition ratio of M1 to O, and the composition ratio of M2 to O are naturally changed according to the selected element. Chemical.

並且，第2金屬M2之陰電性小於第1金屬M1之陰電性。第1金屬M1及第2金屬M2選自以下之表1(極化之陰電性)中所示之第2族、第3族、第4族、第5族及第13族。作為第1金屬M1及第2金屬M2，特佳為其氧化物於器件動作範圍溫度(例如<200℃)下以固體形式存在，且為薄膜而具有良好之絕緣性。該等金屬中，只要根據陰電性之關係而選擇下層之氧化膜及上層之氧化膜之組合即可。 Further, the cathode electrical property of the second metal M2 is smaller than the cathode electrical property of the first metal M1. The first metal M1 and the second metal M2 are selected from the group consisting of Group 2, Group 3, Group 4, Group 5, and Group 13 shown in Table 1 below (polarity of polarization). As the first metal M1 and the second metal M2, it is particularly preferable that the oxide is present in a solid form at a device operating range temperature (for example, <200 ° C), and is a film and has good insulating properties. Among these metals, a combination of the oxide film of the lower layer and the oxide film of the upper layer may be selected in accordance with the relationship between the electrical properties.

作為第1金屬M1、亦即構成下層之氧化膜之金屬(元素)，較佳為Al。再者，亦可如後述之實施形態3等中所說明般使用Si(第14族)。若於形成第1金屬之氧化物時氮化物半導體表面被氧化，則形成絕緣性低之界面氧化物層，有損閘極絕緣膜之特性。上述Al之氧化物、亦即氧化鋁即使形成於氮化物半導體(特別是GaN)上，亦難以形成該界面反應層，於此方面而言適宜用於下層。 The metal (element) which is the first metal M1, that is, the oxide film constituting the lower layer, is preferably Al. Further, Si (Group 14) can be used as described in the third embodiment or the like described later. When the surface of the nitride semiconductor is oxidized when the oxide of the first metal is formed, an interface oxide layer having low insulating properties is formed, which detracts from the characteristics of the gate insulating film. Even if the oxide of Al, that is, aluminum oxide is formed on a nitride semiconductor (particularly GaN), it is difficult to form the interface reaction layer, and in this respect, it is suitably used for the lower layer.

<關於閘極電極> <About gate electrode>

閘極電極GE包含形成於閘極絕緣膜GI上之第3金屬M3之氮化物M3N、形成於第3金屬M3之氮化物M3N上之第4金屬M4。 The gate electrode GE includes a nitride M3N of the third metal M3 formed on the gate insulating film GI, and a fourth metal M4 formed on the nitride M3N of the third metal M3.

將於上述本實施形態中適宜使用之金屬(M3、M3N、M4)總結表示於以下之表2。 The metals (M3, M3N, M4) which are suitably used in the above-described embodiment are summarized in Table 2 below.

又，如上所述，較佳為N與M3之組成比N/M3大於1。又，M4之膜厚較佳為50nm以上。 Further, as described above, it is preferable that the composition ratio N/M3 of N and M3 is more than 1. Further, the film thickness of M4 is preferably 50 nm or more.

(實施形態2) (Embodiment 2)

以下，一面參照圖式，一面對本實施形態之半導體裝置加以詳細說明。 Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

[構造說明] [structural description]

圖13係表示本實施形態之半導體裝置之構成之剖視圖。圖13中所示之半導體裝置係使用氮化物半導體之MISFET。該半導體裝置亦稱為高電子遷移率電晶體(HEMT：High Electron Mobility Transistor)或功率電晶體。本實施形態之半導體裝置係所謂之凹槽閘極型半導體裝置。 Fig. 13 is a cross-sectional view showing the configuration of a semiconductor device of the embodiment. The semiconductor device shown in Fig. 13 uses a MISFET of a nitride semiconductor. The semiconductor device is also referred to as a High Electron Mobility Transistor (HEMT) or a power transistor. The semiconductor device of this embodiment is a so-called recess gate type semiconductor device.

於本實施形態之半導體裝置中，包含形成於基板S上之複數個氮化物半導體層。具體而言，於基板S上依序形成有核生成層NUC、應變緩和層STR、緩衝層BU、通道層(亦稱為電子移行層)CH及障壁層BA。閘極電極GE係貫通絕緣膜IF及障壁層BA，介隔閘極絕緣膜GI而形成於挖掘至通道層CH之中途之溝(亦稱為溝槽、凹槽)T之內部。 The semiconductor device of this embodiment includes a plurality of nitride semiconductor layers formed on the substrate S. Specifically, a nucleation layer NUC, a strain relaxation layer STR, a buffer layer BU, a channel layer (also referred to as an electron transition layer) CH, and a barrier layer BA are sequentially formed on the substrate S. The gate electrode GE penetrates through the insulating film IF and the barrier layer BA, and is formed inside the trench (also referred to as a trench or groove) T excavated to the channel layer CH via the gate insulating film GI.

此處，閘極絕緣膜GI包含形成於通道層CH上之第1閘極絕緣膜GIa、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb，包含與實施形態1中所說明之閘極絕緣膜(第1閘極絕緣膜GIa、第2閘極絕緣膜GIb)同樣之材料。亦即，第1閘極絕緣膜GIa包含第1金屬之氧化物。第2閘極絕緣膜GIb包含第2金屬之氧化物。並且，第2金屬之陰電性低於第1金屬之陰電性。第1閘極絕緣膜GIa並非對通道層(氮化物半導 體)CH進行熱氧化而形成之膜，而是藉由所謂堆積法(沈積法)而形成之膜。亦即，下層之第1金屬之氧化膜並非構成氮化物半導體層之元素之氧化物。如上所述，第1金屬之氧化膜並非藉由通道層(氮化物半導體)之直接氧化而形成者，因此第1金屬與構成通道層(氮化物半導體)之元素不同。 Here, the gate insulating film GI includes the first gate insulating film GIa formed on the channel layer CH and the second gate insulating film GIb formed on the first gate insulating film GIa, and is included in the first embodiment. The same material as the gate insulating film (the first gate insulating film GIa and the second gate insulating film GIb) will be described. That is, the first gate insulating film GIa includes the oxide of the first metal. The second gate insulating film GIb includes an oxide of the second metal. Further, the cathode of the second metal is lower than the cathode of the first metal. The first gate insulating film GIa is not the channel layer (nitride semiconductor The film formed by thermal oxidation of CH is a film formed by a so-called deposition method (deposition method). That is, the oxide film of the first metal of the lower layer is not an oxide of an element constituting the nitride semiconductor layer. As described above, since the oxide film of the first metal is not formed by direct oxidation of the channel layer (nitride semiconductor), the first metal is different from the element constituting the channel layer (nitride semiconductor).

又，閘極電極GE包含形成於通道層CH上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb，包含與實施形態1中所說明之閘極電極(第1閘極電極GEa、第2閘極電極GEb)同樣之材料。亦即，第1閘極電極GEa包含第3金屬之氮化物(含有第3金屬之氮化物、第3金屬之氮化膜)。第2閘極電極GEb包含第4金屬。並且，較佳為第3金屬之氮化物之氮(N)與第3金屬(M3)之組成比N/M3大於1。又，第4金屬之膜厚較佳為50nm以上。 Further, the gate electrode GE includes a first gate electrode GEa formed on the channel layer CH and a second gate electrode GEb formed on the first gate electrode GEa, and includes the gate electrode described in the first embodiment. (The first gate electrode GEa and the second gate electrode GEb) are made of the same material. In other words, the first gate electrode GEa includes a nitride of a third metal (a nitride containing a third metal and a nitride film of a third metal). The second gate electrode GEb includes a fourth metal. Further, it is preferable that the composition ratio N/M3 of the nitrogen (N) to the third metal (M3) of the nitride of the third metal is larger than 1. Further, the film thickness of the fourth metal is preferably 50 nm or more.

又，源極電極SE及汲極電極DE形成於閘極電極GE之兩側之障壁層BA上。 Further, the source electrode SE and the drain electrode DE are formed on the barrier layer BA on both sides of the gate electrode GE.

如圖13所示，於基板S上形成有核生成層NUC，於核生成層NUC上形成有應變緩和層STR。核生成層NUC係為了生成於應變緩和層STR等之上部所形成之層生長時之晶核而形成。又，核生成層NUC係為了防止如下現象而形成：形成於上部之層之構成元素(例如Ga等)自上部所形成之層擴散至基板S，從而造成基板S變質。又，應變緩和層STR係為了緩和對基板S之應力，抑制於基板S產生翹曲或裂痕而形成。 As shown in FIG. 13, a nucleation layer NUC is formed on the substrate S, and a strain relaxation layer STR is formed on the nucleation layer NUC. The nucleation layer NUC is formed in order to form a crystal nucleus at the time of layer growth of the upper portion formed by the strain relaxation layer STR or the like. Further, the nucleation layer NUC is formed to prevent the formation of a constituent element (for example, Ga or the like) formed in the upper layer from the layer formed on the upper portion to the substrate S, thereby deteriorating the substrate S. Further, the strain relief layer STR is formed to suppress warpage or cracking of the substrate S in order to alleviate the stress on the substrate S.

於該應變緩和層STR上形成有緩衝層BU，於緩衝層BU上形成有包含氮化物半導體之通道層(亦稱為電子移行層)CH，於通道層CH上形成有包含氮化物半導體之障壁層BA。於閘極電極GE之兩側之障壁層BA上形成有源極電極SE及汲極電極DE。該源極電極SE及汲極電極DE與障壁層BA分別進行歐姆連接。又，於閘極電極GE上形成有絕緣 層IL1，該絕緣層IL1中，將源極電極SE之形成區域及汲極電極DE之形成區域之絕緣層IL1除去而形成接觸孔。於該接觸孔之內部埋入導電性膜，藉由該導電性膜構成上述源極電極SE及汲極電極DE。於源極電極SE及汲極電極DE上形成有絕緣層IL2。 A buffer layer BU is formed on the strain relaxation layer STR, and a channel layer (also referred to as an electron transition layer) CH including a nitride semiconductor is formed on the buffer layer BU, and a barrier layer containing a nitride semiconductor is formed on the channel layer CH. Layer BA. A source electrode SE and a drain electrode DE are formed on the barrier layer BA on both sides of the gate electrode GE. The source electrode SE and the drain electrode DE are ohmically connected to the barrier layer BA, respectively. Also, an insulation is formed on the gate electrode GE In the layer IL1, in the insulating layer IL1, the insulating layer IL1 which forms the region where the source electrode SE is formed and the region where the gate electrode DE is formed is removed to form a contact hole. A conductive film is buried in the contact hole, and the source electrode SE and the drain electrode DE are formed by the conductive film. An insulating layer IL2 is formed on the source electrode SE and the drain electrode DE.

此處，於本實施形態之半導體裝置中，於通道層CH與障壁層BA之界面附近之通道層側生成二維電子氣2DEG。又，於對閘極電極GE施加正電壓(閾值電壓)之情形時，於閘極電極GE與通道層CH之界面附近形成通道。 Here, in the semiconductor device of the present embodiment, the two-dimensional electron gas 2DEG is generated on the channel layer side near the interface between the channel layer CH and the barrier layer BA. Further, when a positive voltage (threshold voltage) is applied to the gate electrode GE, a channel is formed in the vicinity of the interface between the gate electrode GE and the channel layer CH.

上述二維電子氣2DEG係由於如下機制而形成。構成通道層CH或障壁層BA之氮化物半導體(此處為氮化鎵系半導體)分別禁帶寬度(帶隙)或電子親和力不同。因此，於該等半導體之接合面生成井型電位。於該井型電位內儲存電子，因此於通道層CH與障壁層BA之界面附近生成二維電子氣2DEG。 The above two-dimensional electron gas 2DEG system is formed by the following mechanism. The nitride semiconductor (here, a gallium nitride-based semiconductor) constituting the channel layer CH or the barrier layer BA has a different band gap (band gap) or electron affinity. Therefore, a well type potential is generated at the junction surface of the semiconductors. The electrons are stored in the well type potential, so that a two-dimensional electron gas 2DEG is generated in the vicinity of the interface between the channel layer CH and the barrier layer BA.

並且，於通道層CH與障壁層BA之界面附近所形成之二維電子氣2DEG藉由形成有閘極電極GE之溝T而分斷。因此，於本實施形態之半導體裝置中，可根據通道之形成之有無而切換接通/斷開。 Further, the two-dimensional electron gas 2DEG formed in the vicinity of the interface between the channel layer CH and the barrier layer BA is separated by the groove T in which the gate electrode GE is formed. Therefore, in the semiconductor device of the present embodiment, the on/off can be switched in accordance with the presence or absence of the formation of the channel.

並且，於本實施形態中，將第1金屬之氧化物與配置於其上之陰電性低於第1金屬之第2金屬之氧化物的積層膜用作閘極絕緣膜GI，因此能夠與實施形態1之情形同樣地使平帶電壓(Vfb)向正方向偏移。藉此，能夠使閾值電壓(Vth)向正方向偏移。並且，藉由調整偏移量，能夠使閾值電壓(Vth)為正(Vth>0)，能夠使常斷開特性提高。 Further, in the present embodiment, the laminated film in which the oxide of the first metal and the oxide of the second metal which is disposed on the second metal are less than the gate insulating film GI is used as the gate insulating film GI. In the case of the first embodiment, the flat band voltage (Vfb) is shifted in the positive direction in the same manner. Thereby, the threshold voltage (Vth) can be shifted in the positive direction. Further, by adjusting the offset amount, the threshold voltage (Vth) can be made positive (Vth>0), and the normally-off characteristic can be improved.

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬，因此能夠與實施形態1之情形同樣地防止氧向閘極絕緣膜GI擴散，減低閾值電壓(Vth)之不均一。特別是即使經過後述之退火處理，亦能夠減低氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is disposed in the upper layer. Therefore, in the same manner as in the first embodiment, oxygen can be prevented from diffusing into the gate insulating film GI. Reduce the non-uniformity of the threshold voltage (Vth). In particular, even after the annealing treatment described later, it is possible to reduce the diffusion of oxygen and maintain the layering effect of the gate insulating film.

進而，藉由使第3金屬之氮化物之氮(N)與第3金屬(M3)之組成比N/M3大於1，能夠起到與實施形態1同樣之效果。又，藉由使第4金屬之膜厚為50nm以上，能夠起到與實施形態1同樣之效果。 Further, by setting the composition ratio N/M3 of nitrogen (N) to the third metal (M3) of the nitride of the third metal to be larger than 1, the same effect as in the first embodiment can be obtained. Moreover, by making the film thickness of the fourth metal 50 nm or more, the same effects as those of the first embodiment can be obtained.

[製法說明] [Method Description]

其次，一面參照圖14~圖25一面說明本實施形態之半導體裝置之製造方法，且使該半導體裝置之構成更明確。圖14~圖25係表示本實施形態之半導體裝置之製造步驟之剖視圖。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 14 to 25, and the configuration of the semiconductor device will be further clarified. 14 to 25 are cross-sectional views showing the steps of manufacturing the semiconductor device of the embodiment.

如圖14所示，作為基板S，例如使用包含露出(111)面之矽(Si)之半導體基板，於其上部，例如使用有機金屬化學氣相沈積法等異質磊晶生長氮化鋁(AlN)層作為核生成層NUC。其次，於核生成層NUC上，形成反覆積層有氮化鎵(GaN)層與氮化鋁(AlN)層之積層膜(AlN/GaN膜)之超晶格構造體作為應變緩和層STR。例如，使用有機金屬氣相沈積法等，分別以2~3nm左右之膜厚，分別反覆異質磊晶生長100層(合計200層)左右之氮化鎵(GaN)層及氮化鋁(AlN)層。再者，作為基板S，除了上述矽以外，亦可使用包含SiC或藍寶石等之基板。 As shown in FIG. 14, as the substrate S, for example, a semiconductor substrate including a (Si) surface (Si) is exposed, and in the upper portion thereof, aluminum nitride (AlN) is grown by, for example, an organic metal chemical vapor deposition method. The layer acts as a nuclear generation layer NUC. Next, on the nucleation layer NUC, a superlattice structure in which a laminated film (AlN/GaN film) of a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer is laminated is formed as a strain relaxation layer STR. For example, an organic metal vapor phase deposition method or the like, respectively, a film thickness of about 2 to 3 nm, respectively, and a heterogeneous epitaxial growth of 100 layers (total of 200 layers) of a gallium nitride (GaN) layer and aluminum nitride (AlN) Floor. Further, as the substrate S, a substrate including SiC or sapphire may be used in addition to the above-described crucible.

其次，於應變緩和層STR上形成緩衝層BU。於應變緩和層STR上，例如使用有機金屬氣相沈積法等使AlGaN層異質磊晶生長而作為緩衝層BU。 Next, a buffer layer BU is formed on the strain relaxation layer STR. The AlGaN layer is heteroepitaxially grown on the strain relaxation layer STR by, for example, an organic metal vapor deposition method to serve as the buffer layer BU.

其次，如圖15所示般，於緩衝層BU上形成通道層CH。例如，於緩衝層BU上，使氮化鎵層(i-GaN層)異質磊晶生長。此時，並不刻意地進行雜質之摻雜而使其生長。該通道層CH之電子親和力大於緩衝層BU之電子親和力。又，該通道層CH係帶隙比緩衝層BU窄之氮化物半導體。 Next, as shown in FIG. 15, a channel layer CH is formed on the buffer layer BU. For example, on the buffer layer BU, a gallium nitride layer (i-GaN layer) is heteroepitaxially grown. At this time, doping of impurities is not intentionally carried out to grow them. The electron affinity of the channel layer CH is greater than the electron affinity of the buffer layer BU. Further, the channel layer CH is a nitride semiconductor having a narrower band gap than the buffer layer BU.

其次，於通道層CH上，例如使用有機金屬氣相沈積法等使AlGaN層異質磊晶生長而作為障壁層BA。該障壁層BA之電子親和力 小於通道層CH之電子親和力。又，該障壁層BA係帶隙比通道層CH寬之氮化物半導體。 Next, the AlGaN layer is heteroepitaxially grown on the channel layer CH by, for example, an organic metal vapor deposition method or the like as the barrier layer BA. Electronic affinity of the barrier layer BA Less than the electron affinity of the channel layer CH. Further, the barrier layer BA is a nitride semiconductor having a band gap wider than that of the channel layer CH.

如此般，形成緩衝層BU、通道層CH及障壁層BA之積層體。該積層體係藉由上述異質磊晶生長、亦即[0001]晶軸(C軸)方向所積層之III族面生長而形成。換而言之，藉由(0001)Ga面生長而形成上述積層體。該積層體中，於通道層CH與障壁層BA之界面附近生成二維電子氣2DEG。 In this manner, a laminate of the buffer layer BU, the channel layer CH, and the barrier layer BA is formed. The layered system is formed by the above-described heterogeneous epitaxial growth, that is, the growth of the group III surface of the layer in the [0001] crystal axis (C-axis) direction. In other words, the above laminated body is formed by (0001) Ga surface growth. In the laminate, a two-dimensional electron gas 2DEG is generated in the vicinity of the interface between the channel layer CH and the barrier layer BA.

其次，如圖16所示般，於障壁層BA上形成具有開口部之絕緣膜IF。例如，使用熱CVD法等，於障壁層BA上堆積氮化矽膜作為絕緣膜IF。其次，藉由使用光微影技術及蝕刻技術而於絕緣膜IF上形成開口部。 Next, as shown in FIG. 16, an insulating film IF having an opening is formed on the barrier layer BA. For example, a tantalum nitride film is deposited on the barrier layer BA as the insulating film IF by a thermal CVD method or the like. Next, an opening is formed in the insulating film IF by using a photolithography technique and an etching technique.

其次，將絕緣膜IF作為遮罩，對障壁層BA及通道層CH進行蝕刻，藉此形成貫通絕緣膜IF及障壁層BA而到達通道層CH之中途之溝T(圖17)。於該蝕刻後，為了恢復蝕刻損傷，亦可進行熱處理。 Next, the insulating film IF is used as a mask, and the barrier layer BA and the channel layer CH are etched to form a trench T that penetrates the insulating film IF and the barrier layer BA and reaches the channel layer CH (FIG. 17). After the etching, heat treatment may be performed in order to restore the etching damage.

其次，如圖18及圖19所示般，於溝T內及絕緣膜IF上形成包含第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之閘極絕緣膜GI。例如，於通道層CH露出於其底部之溝T內及絕緣膜IF上形成第1閘極絕緣膜GIa。例如，於溝T之底面、側壁及絕緣膜IF上堆積氧化鋁膜(Al2O3膜)作為第1閘極絕緣膜GIa(圖18)。具體而言，藉由稀釋HCl溶液對基板S之表面進行清洗後，例如將三甲基鋁(Al(CH3)3、TMA)及H2O(氧化劑)作為原料氣體，於400℃之氛圍中，使用ALD法於溝T內及絕緣膜IF上堆積50nm~100nm左右之膜厚之氧化鋁膜(Al2O3膜)。藉由ALD法，能夠膜厚之控制性良好、且即使於凹凸面亦被覆性良好地形成膜。再者，作為氧化劑，除了H2O以外，亦可使用臭氧(O3)。 Next, as shown in FIGS. 18 and 19, a gate insulating film GI including a first gate insulating film GIa and a second gate insulating film GIb is formed in the trench T and on the insulating film IF. For example, the first gate insulating film GIa is formed in the trench T in which the channel layer CH is exposed at the bottom and on the insulating film IF. For example, an aluminum oxide film (Al 2 O 3 film) is deposited on the bottom surface of the trench T, the sidewall, and the insulating film IF as the first gate insulating film GMa (Fig. 18). Specifically, after the surface of the substrate S is washed by diluting the HCl solution, for example, trimethylaluminum (Al(CH 3 ) 3 , TMA) and H 2 O (oxidant) are used as a material gas at an atmosphere of 400 ° C. In the ALD method, an aluminum oxide film (Al 2 O 3 film) having a film thickness of about 50 nm to 100 nm is deposited in the trench T and on the insulating film IF. According to the ALD method, the film thickness can be controlled with good controllability, and the film can be formed with excellent coating properties even on the uneven surface. Further, as the oxidizing agent, ozone (O 3 ) may be used in addition to H 2 O.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，第1閘極絕緣膜GIa(此處為氧化鋁膜) 中之陷阱(陷阱能階、缺陷)減少。特別是於藉由堆積法於GaN上形成氧化鋁之情形時，膜中之陷阱密度變高，C-V特性之遲滯變大。因此，藉由實施熱處理，能夠減低陷阱密度。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the first gate insulating film GIa (here, the aluminum oxide film) is reduced. In particular, when aluminum oxide is formed on the GaN by the deposition method, the trap density in the film becomes high, and the hysteresis of the CV characteristic becomes large. Therefore, by performing heat treatment, the trap density can be reduced.

其次，如圖19所示般，於第1閘極絕緣膜GIa(此處為氧化鋁膜)上，例如形成氧化鉿膜(HfO2膜)作為第2閘極絕緣膜GIb。例如，藉由使用Hf金屬靶、及氬(Ar)與氧(O2)之混合氣體之反應性濺鍍法堆積氧化鉿膜。氧化鉿膜之膜厚亦因閾值電壓(Vth)而異，較佳為1~10nm左右。反應性濺鍍法係PVD法之一種。於形成第2閘極絕緣膜GIb時，除了PVD法以外，亦可使用ALD法或CVD法。 Next, as shown in FIG. 19, for example, a hafnium oxide film (HfO 2 film) is formed as the second gate insulating film GIb on the first gate insulating film GIa (here, an aluminum oxide film). For example, a ruthenium oxide film is deposited by a reactive sputtering method using a Hf metal target and a mixed gas of argon (Ar) and oxygen (O 2 ). The film thickness of the ruthenium oxide film also varies depending on the threshold voltage (Vth), and is preferably about 1 to 10 nm. The reactive sputtering method is one of the PVD methods. When the second gate insulating film GIb is formed, an ALD method or a CVD method may be used in addition to the PVD method.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第2閘極絕緣膜GIb(此處為氧化鉿膜)中之陷阱(陷阱能階、缺陷)。再者，於上述步驟中，個別地進行第1閘極絕緣膜GIa(氧化鋁膜)之形成後之熱處理、第2閘極絕緣膜GIb(氧化鉿膜)之形成後之熱處理，但亦可省略第1閘極絕緣膜GIa之形成後之熱處理，於第1閘極絕緣膜GIa(氧化鋁膜)與第2閘極絕緣膜GIb(氧化鉿膜)之積層膜之形成後一次性進行熱處理。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the second gate insulating film GIb (here, the hafnium oxide film) can be reduced. Further, in the above step, the heat treatment after the formation of the first gate insulating film GIa (aluminum oxide film) and the heat treatment after the formation of the second gate insulating film GIb (yttrium oxide film) are performed individually, but may be performed. The heat treatment after the formation of the first gate insulating film GIa is omitted, and the heat treatment is performed once after the formation of the laminated film of the first gate insulating film GIa (aluminum oxide film) and the second gate insulating film GIb (yttria film). .

如此般，形成包含第1閘極絕緣膜GIa(氧化鋁膜)與第2閘極絕緣膜GIb(氧化鉿膜)之積層膜之閘極絕緣膜GI。 In this manner, the gate insulating film GI including the laminated film of the first gate insulating film GIa (aluminum oxide film) and the second gate insulating film GIb (yttria film) is formed.

其次，如圖20及圖21所示般，於閘極絕緣膜GI上形成閘極電極GE。例如，形成氮化鈦膜(TiN膜)作為第1閘極電極GEa，進而於其上形成鎢膜(W膜)作為第2閘極電極GEb。該等之積層膜可使用多靶濺鍍裝置連續地形成。例如，藉由使用Ti金屬靶、及氬(Ar)與氮(N2)之混合氣體之反應性濺鍍法，於第2閘極絕緣膜GIb上堆積20nm左右之氮化鈦膜。此時，使所形成之TiN膜之N與Ti之比N/Ti大於1。TiN膜中之N之比例可藉由調整氬(Ar)與氮(N2)之混合氣體中之氮量而控制。 Next, as shown in FIGS. 20 and 21, a gate electrode GE is formed on the gate insulating film GI. For example, a titanium nitride film (TiN film) is formed as the first gate electrode GEa, and a tungsten film (W film) is formed thereon as the second gate electrode GEb. These laminated films can be formed continuously using a multi-target sputtering apparatus. For example, a titanium nitride film of about 20 nm is deposited on the second gate insulating film GIb by a reactive sputtering method using a Ti metal target and a mixed gas of argon (Ar) and nitrogen (N 2 ). At this time, the ratio N/Ti of N to Ti of the formed TiN film is made larger than 1. The ratio of N in the TiN film can be controlled by adjusting the amount of nitrogen in the mixed gas of argon (Ar) and nitrogen (N 2 ).

繼而，如圖21所示般，藉由使用W金屬靶、氬(Ar)氣體之濺鍍法 於第1閘極電極GEa上堆積100nm左右之膜厚之鎢膜。 Then, as shown in FIG. 21, by using a W metal target, argon (Ar) gas sputtering method A tungsten film having a film thickness of about 100 nm is deposited on the first gate electrode GEa.

其次，進行熱處理。該熱處理係用以減低由閘極電極GE之成膜時之電漿或荷電粒子所引起的閘極絕緣膜(Al2O3與HfO2)中之陷阱(陷阱能階、缺陷)之熱處理。作為熱處理條件，只要根據第1閘極電極GEa與第2閘極電極GEb之PVD條件(例如功率或時間)而選擇最合適之溫度、時間等即可。根據本發明者之研究，較佳為於溫度為400℃~600℃、時間為10分鐘~60分鐘之範圍進行。又，作為熱處理氛圍，例如較佳為使用氮(N2)等惰性氣體之氛圍。 Next, heat treatment is performed. This heat treatment is for heat treatment for reducing traps (trap levels, defects) in the gate insulating film (Al 2 O 3 and HfO 2 ) caused by plasma or charged particles when the gate electrode GE is formed. As the heat treatment conditions, the most suitable temperature, time, and the like may be selected based on the PVD conditions (for example, power or time) of the first gate electrode GEa and the second gate electrode GEb. According to the study by the inventors, it is preferably carried out at a temperature of from 400 ° C to 600 ° C for a period of from 10 minutes to 60 minutes. Further, as the heat treatment atmosphere, for example, an atmosphere of an inert gas such as nitrogen (N 2 ) is preferably used.

其次，如圖22所示般，使用光微影技術及蝕刻技術，對氮化鈦膜與鎢膜之積層膜進行圖案化，藉此形成閘極電極GE。於閘極電極GE之蝕刻時，亦對下層之閘極絕緣膜GI進行蝕刻。再者，上述熱處理亦可於該圖案化步驟之後進行。 Next, as shown in FIG. 22, a laminated film of a titanium nitride film and a tungsten film is patterned using a photolithography technique and an etching technique, thereby forming a gate electrode GE. When the gate electrode GE is etched, the lower gate insulating film GI is also etched. Furthermore, the above heat treatment may also be performed after the patterning step.

如此般，形成包含第1閘極電極GEa與第2閘極電極GEb之積層膜之閘極電極GE。又，作為第1閘極電極GEa之材料，亦可使用容易閘極蝕刻之例如TaN、WN等，作為第2閘極電極GEb，亦可使用例如Ru或Ir等。 In this manner, the gate electrode GE including the laminated film of the first gate electrode GEa and the second gate electrode GEb is formed. Further, as the material of the first gate electrode GEa, for example, TaN or WN which is easily gate-etched may be used, and as the second gate electrode GEb, for example, Ru or Ir may be used.

其次，如圖23所示般，使用CVD法等，於閘極電極GE及絕緣膜IF上形成例如氧化矽膜作為絕緣層IL1。其次，如圖24所示般，藉由使用光微影技術及蝕刻技術，將源極電極SE之形成區域及汲極電極DE之形成區域上之絕緣層IL1及絕緣膜IF利用蝕刻除去，形成接觸孔。其次，於閘極電極GE之兩側之障壁層BA上形成源極電極SE及汲極電極DE。例如，於包含接觸孔內之絕緣層IL1上形成導電性膜。例如，使用濺鍍法等形成包含氮化鈦(TiN)膜與其上部之鋁(Al)膜之積層膜(Al/TiN)作為導電性膜。其次，藉由使用光微影技術及蝕刻技術，對上述積層膜(Al/TiN)進行圖案化，並例如於550℃下進行30分鐘左右之熱處理。藉由該熱處理，源極電極SE及汲極電極DE與障壁層 BA(氮化物半導體膜)之界面之接觸成為歐姆接觸。又，能夠消除成膜導電性膜時對閘極絕緣膜GI之充電損傷。 Next, as shown in FIG. 23, for example, a ruthenium oxide film is formed as the insulating layer IL1 on the gate electrode GE and the insulating film IF by a CVD method or the like. Next, as shown in FIG. 24, the insulating layer IL1 and the insulating film IF on the formation region of the source electrode SE and the formation region of the drain electrode DE are removed by etching using a photolithography technique and an etching technique. Contact hole. Next, a source electrode SE and a drain electrode DE are formed on the barrier layer BA on both sides of the gate electrode GE. For example, a conductive film is formed on the insulating layer IL1 including the contact holes. For example, a laminated film (Al/TiN) including a titanium nitride (TiN) film and an aluminum (Al) film on the upper portion thereof is formed as a conductive film by a sputtering method or the like. Next, the laminated film (Al/TiN) is patterned by using a photolithography technique and an etching technique, and heat-treated at 550 ° C for about 30 minutes, for example. By the heat treatment, the source electrode SE and the drain electrode DE and the barrier layer The contact of the interface of BA (nitride semiconductor film) becomes an ohmic contact. Further, it is possible to eliminate the charging damage to the gate insulating film GI when the conductive film is formed.

其後，於包括源極電極SE及汲極電極DE上之絕緣層IL1上形成絕緣層(亦稱為覆蓋膜、表面保護膜)IL2。作為絕緣層IL2，例如使用CVD法等堆積氮氧化矽(SiON)膜(圖25)。 Thereafter, an insulating layer (also referred to as a cover film, surface protective film) IL2 is formed on the insulating layer IL1 including the source electrode SE and the drain electrode DE. As the insulating layer IL2, for example, a ruthenium oxynitride (SiON) film is deposited by a CVD method or the like (Fig. 25).

藉由以上步驟，能夠形成本實施形態之半導體裝置。 Through the above steps, the semiconductor device of the present embodiment can be formed.

如上所述，根據本實施形態，與實施形態1之情形同樣地將第1金屬之氧化膜與陰電性低於第1金屬之第2金屬之氧化膜積層而用作閘極絕緣膜，藉此能夠使閾值電壓(Vth)向正方向偏移。並且，藉由調整偏移量，能夠實現使閾值電壓(Vth)為正(Vth>0)之常斷開化。 As described above, in the same manner as in the first embodiment, the oxide film of the first metal and the oxide film of the second metal having a lower electrical property than the first metal are laminated as the gate insulating film. This can shift the threshold voltage (Vth) in the positive direction. Further, by adjusting the offset amount, the threshold voltage (Vth) is always turned off (Vth>0).

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬，因此能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。藉此，能夠使閾值電壓(Vth)為正(Vth>0)。又，能夠矯正閾值電壓(Vth)之不均一。特別是即使於形成閘極絕緣膜GI之後實施退火處理之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is placed on the upper layer. Therefore, it is possible to prevent oxygen from diffusing into the gate insulating film GI and maintain polarization of oxygen (gate) The layering effect of the insulating film) maintains the offset effect of the flat band voltage Vfb. Thereby, the threshold voltage (Vth) can be made positive (Vth>0). Moreover, the unevenness of the threshold voltage (Vth) can be corrected. In particular, even in the case where the annealing treatment is performed after the formation of the gate insulating film GI, the diffusion of oxygen due to the annealing treatment can be reduced, and the layering effect of the gate insulating film can be maintained.

上述閘極電極GE、源極電極SE及汲極電極DE之佈局並無限制，該等電極例如如圖26般配置。圖26係表示本實施形態之半導體裝置之構成之俯視圖之一例。例如，圖13與圖26之A-A剖面部對應。源極電極SE與汲極電極DE例如為於Y方向上延伸之線狀。換而言之，為於Y方向上具有長邊之矩形狀(四邊形狀)。源極電極SE與汲極電極DE係交替排列於X方向而配置。並且，於源極電極SE與汲極電極DE之間配置閘極電極GE。例如，於Y方向上延伸之線狀之複數個閘極電極(GE)之其中一個端部(圖中上側)與在X方向上延伸之線(亦稱為閘極線)連接。又，於Y方向上延伸之線狀之複數個閘極電極(GE)之另一個端 部(圖中下側)與在X方向上延伸之線(亦稱為閘極線)連接。再者，於2根在X方向上延伸之線(亦稱為閘極線)中，亦可省略任一者，將閘極電極GE設為梳齒狀。又，複數個源極電極SE經由插塞(連接部)PG而與在X方向上延伸之源極線SL連接。又，複數個汲極電極DE經由插塞(連接部)PG而與在X方向上延伸之汲極線DL連接。再者，亦可於同層配置源極電極SE與源極線SL。例如，亦可設為將在X方向上延伸之線(與源極線部對應)、與在Y方向上延伸之線狀源極電極連接的形狀(梳齒狀)。同樣，亦可於同層配置汲極電極DE與汲極線DL。例如，亦可設為將在X方向上延伸之線(與汲極線部對應)、與在Y方向上延伸之線狀汲極電極連接的形狀(梳齒狀)。如上所述，閘極電極GE、源極電極SE、汲極電極DE及其他配線之佈局可適當變更，配線層數亦無限制。 The layout of the gate electrode GE, the source electrode SE, and the drain electrode DE is not limited, and the electrodes are disposed as shown in FIG. 26, for example. Fig. 26 is a view showing an example of a plan view of the configuration of the semiconductor device of the embodiment. For example, FIG. 13 corresponds to the A-A section of FIG. The source electrode SE and the drain electrode DE are, for example, in a line shape extending in the Y direction. In other words, it has a rectangular shape (a quadrangular shape) having a long side in the Y direction. The source electrode SE and the drain electrode DE are arranged alternately in the X direction. Further, a gate electrode GE is disposed between the source electrode SE and the drain electrode DE. For example, one end portion (upper side in the figure) of a plurality of linear gate electrodes (GE) extending in the Y direction is connected to a line (also referred to as a gate line) extending in the X direction. Further, the other end of the plurality of gate electrodes (GE) extending in the Y direction The portion (the lower side in the figure) is connected to a line (also referred to as a gate line) extending in the X direction. Further, in the two lines (also referred to as gate lines) extending in the X direction, either one of them may be omitted, and the gate electrode GE may be formed in a comb shape. Further, a plurality of source electrodes SE are connected to the source line SL extending in the X direction via a plug (connecting portion) PG. Further, a plurality of gate electrodes DE are connected to the drain line DL extending in the X direction via a plug (connecting portion) PG. Furthermore, the source electrode SE and the source line SL may be disposed in the same layer. For example, a shape (comb-like shape) in which a line extending in the X direction (corresponding to the source line portion) and a linear source electrode extending in the Y direction are connected may be used. Similarly, the drain electrode DE and the drain line DL may be disposed in the same layer. For example, a shape (comb-like shape) in which a line extending in the X direction (corresponding to the drain line portion) and a linear drain electrode extending in the Y direction are connected may be used. As described above, the layout of the gate electrode GE, the source electrode SE, the drain electrode DE, and other wirings can be appropriately changed, and the number of wiring layers is not limited.

又，閘極電極GE例如可引出至活性區域之外側之元件分離區域ISO上(於圖26中為右側之B-B部)。並且，該引出部例如可經由插塞PG而與其他配線層之配線連接。再者，圖27係表示本實施形態之半導體裝置之構成之剖視圖。圖27例如與圖26之B-B剖面部對應。插塞PG例如包含Al/TiN膜。 Further, the gate electrode GE can be drawn, for example, to the element isolation region ISO on the outer side of the active region (the B-B portion on the right side in Fig. 26). Further, the lead portion can be connected to the wiring of another wiring layer via the plug PG, for example. Fig. 27 is a cross-sectional view showing the configuration of the semiconductor device of the embodiment. Fig. 27 corresponds to, for example, the section B-B of Fig. 26. The plug PG includes, for example, an Al/TiN film.

(實施形態3) (Embodiment 3)

於實施形態1(圖1)中，將閘極絕緣膜GI之下層之氧化膜(GIa)設為第1金屬之氧化膜，但亦可將該下層之氧化膜設為氧化矽膜。亦即，作為構成下層之氧化膜之元素，使用Si(半導體)。 In the first embodiment (FIG. 1), the oxide film (GIa) under the gate insulating film GI is an oxide film of the first metal. However, the oxide film of the lower layer may be a hafnium oxide film. That is, Si (semiconductor) is used as an element constituting the oxide film of the lower layer.

[構造說明] [structural description]

圖28係表示本實施形態之半導體裝置之構成之剖視圖。本實施形態之半導體裝置除了第1閘極絕緣膜GIa為氧化矽膜以外，其他與實施形態1之情形相同。 Fig. 28 is a cross-sectional view showing the configuration of a semiconductor device of the embodiment. The semiconductor device of the present embodiment is the same as the first embodiment except that the first gate insulating film GIa is a hafnium oxide film.

如圖28所示，於本實施形態之半導體裝置中，與實施形態1之情 形同樣地包含介隔閘極絕緣膜GI配置於包含氮化物半導體之通道層CH上之閘極電極GE(GEa、GEb)。 As shown in FIG. 28, in the semiconductor device of the present embodiment, the situation of the first embodiment is the same as that of the first embodiment. Similarly, the barrier gate insulating film GI is disposed on the gate electrode GE (GEa, GEb) including the channel layer CH of the nitride semiconductor.

此處，閘極絕緣膜GI包含形成於通道層CH上之作為第1閘極絕緣膜GIa之氧化矽膜(SiO2)、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。又，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb。 Here, the gate insulating film GI includes a hafnium oxide film (SiO 2 ) as the first gate insulating film GIa formed on the channel layer CH, and a second gate insulating film formed on the first gate insulating film GIa. GIb. Further, the gate electrode GE includes a first gate electrode GEa formed on the second gate insulating film GIb and a second gate electrode GEb formed on the first gate electrode GEa.

如上所述，設置氧化矽膜(SiO2)作為第1閘極絕緣膜GIa。又，設置第2金屬(M2)之氧化膜作為第2閘極絕緣膜GIb。第2金屬係選自Al、Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素。於此情形時，第2金屬之氧化物例如成為氧化鋁(Al2O3)、氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鉭(Ta2O5)、氧化鈦(TiO2)、氧化鈮(Nb2O5)、氧化鑭(La2O3)、氧化釔(Y2O3)、氧化鎂(MgO)。 As described above, the ruthenium oxide film (SiO 2 ) is provided as the first gate insulating film GIa. Further, an oxide film of the second metal (M2) is provided as the second gate insulating film GIb. The second metal is one or more elements selected from the group consisting of Al, Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. In this case, the oxide of the second metal is, for example, alumina (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), or titanium oxide (TiO 2 ). ), cerium oxide (Nb 2 O 5 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO).

於此情形時，分別構成2層閘極絕緣膜(GIa、GIb)之元素(Si、M2)之陰電性係Si>M2。於此情形時，亦產生實施形態1中所說明之氧之極化效果，平帶電壓Vfb向正方向偏移。 In this case, the elements (Si, M2) of the two-layer gate insulating film (GIa, GIb) are respectively composed of an electroconductive system Si>M2. In this case as well, the polarization effect of oxygen described in the first embodiment is also generated, and the flat band voltage Vfb is shifted in the positive direction.

又，與實施形態1之情形同樣地將閘極電極GE設為積層構造，亦即，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬之構成，能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。特別是即使於形成閘極絕緣膜GI之後實施退火處理之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 In the same manner as in the first embodiment, the gate electrode GE has a laminated structure, that is, a nitride containing a third metal and a fourth metal are laminated, and a fourth metal is disposed in the upper layer, thereby preventing oxygen. The gate insulating film GI is diffused to maintain the polarization of oxygen (the layering effect of the gate insulating film), and the effect of shifting the flat band voltage Vfb is maintained. In particular, even in the case where the annealing treatment is performed after the formation of the gate insulating film GI, the diffusion of oxygen due to the annealing treatment can be reduced, and the layering effect of the gate insulating film can be maintained.

[製法說明] [Method Description]

其次，對本實施形態之半導體裝置之製造方法加以說明。於本實施形態之半導體裝置之製造方法中，除了閘極絕緣膜GI之形成步驟以外，其他與實施形態1之情形相同。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described. The method of manufacturing the semiconductor device of the present embodiment is the same as the case of the first embodiment except for the step of forming the gate insulating film GI.

亦即，以與實施形態1同樣之方式對通道層(i-GaN層、GaN基 板)CH之表面進行清洗後，使用堆積法於通道層CH上堆積氧化矽膜(SiO2膜)作為第1閘極絕緣膜GIa。 In other words, after the surface of the channel layer (i-GaN layer, GaN substrate) CH is cleaned in the same manner as in the first embodiment, a yttrium oxide film (SiO 2 film) is deposited on the channel layer CH by the deposition method as the first. Gate insulating film GIA.

例如，將三-二甲基胺基矽烷(SiH(N(CH3)2)3、TDMAS)及臭氧(O3、氧化劑)作為原料氣體，於480℃之氛圍中，使用ALD法堆積3nm左右之膜厚之氧化矽膜(SiO2膜)。氧化矽膜之膜厚例如可於3nm~20nm之範圍內調整。除了ALD法以外，亦可使用CVD法(熱CVD或電漿CVD法等)堆積氧化矽膜。再者，根據本發明者之研究，即使是3~5nm左右之膜厚，亦能夠藉由上述氧之極化而獲得充分之平帶電壓Vfb之偏移效果。 For example, tris-dimethylamino decane (SiH(N(CH 3 ) 2 ) 3 , TDMAS) and ozone (O 3 , oxidizing agent) are used as raw material gases, and are stacked in an atmosphere of 480 ° C using an ALD method of about 3 nm. A cerium oxide film (SiO 2 film) having a film thickness. The film thickness of the ruthenium oxide film can be adjusted, for example, in the range of 3 nm to 20 nm. In addition to the ALD method, a ruthenium oxide film may be deposited by a CVD method (thermal CVD, plasma CVD, or the like). Further, according to the study by the inventors of the present invention, even if the film thickness is about 3 to 5 nm, the effect of shifting the sufficient flat band voltage Vfb can be obtained by the polarization of the oxygen.

其次，進行熱處理。例如，於氮(N2)氛圍中實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第1閘極絕緣膜GIa(此處為氧化矽膜)中之陷阱(陷阱能階、缺陷)。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the first gate insulating film GMa (here, the hafnium oxide film) can be reduced.

其次，於第1閘極絕緣膜GIa上形成第2閘極絕緣膜(第2金屬之氧化膜)GIb。例如，以與實施形態1同樣之方式堆積50nm~100nm左右之膜厚之氧化鋁膜(Al2O3膜)作為第2閘極絕緣膜GIb。 Next, a second gate insulating film (an oxide film of the second metal) GIb is formed on the first gate insulating film GIa. For example, an aluminum oxide film (Al 2 O 3 film) having a film thickness of about 50 nm to 100 nm is deposited as the second gate insulating film GIb in the same manner as in the first embodiment.

其次，進行熱處理。例如，於氮(N2)氛圍中實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第2閘極絕緣膜GIb(此處為氧化鋁膜)中之陷阱(陷阱能階、缺陷)。再者，於上述步驟中，於形成各閘極絕緣膜(GIa、GIb)之後個別地進行熱處理，但亦可於形成第2閘極絕緣膜GIb之後一次性進行熱處理。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the second gate insulating film GIb (here, the aluminum oxide film) can be reduced. Further, in the above step, after each of the gate insulating films (GIa, GIb) is formed, the heat treatment is performed individually, but the heat treatment may be performed once after the formation of the second gate insulating film GIb.

如此般，能夠形成自下方起依序積層有第1閘極絕緣膜GIa(氧化矽膜)及第2閘極絕緣膜GIb(氧化鋁膜)之閘極絕緣膜GI。 In this manner, the gate insulating film GI in which the first gate insulating film GIa (yttrium oxide film) and the second gate insulating film GIb (aluminum oxide film) are sequentially laminated is formed.

其次，以與實施形態1同樣之方式於閘極絕緣膜GI上形成閘極電極GE(GEa、GEb)。 Then, gate electrodes GE (GEa, GEb) are formed on the gate insulating film GI in the same manner as in the first embodiment.

再者，亦可將本實施形態之閘極絕緣膜GI用作實施形態2之閘極絕緣膜GI。 Further, the gate insulating film GI of the present embodiment can also be used as the gate insulating film GI of the second embodiment.

圖29係表示閘極絕緣膜之積層效果之曲線圖。橫軸表示閘極電壓(Gate Voltage[V])，縱軸表示電流(Jg[A/cm2])。例如，使用圖28中所示之半導體裝置，調查其I-V特性。其中，閘極電極為單層。作為Ref、No.1、No.2、No.3，分別使用Al2O3/SiO2之積層膜，將SiO2之膜厚設為0nm、3nm、5nm、10nm。No.1、No.2、No.3，亦即將SiO2之膜厚設為3nm~10nm之情形時，電流之上升電壓變高。認為其係由於平帶電壓Vfb之偏移效果及耐電壓提高效果所達成。 Fig. 29 is a graph showing the effect of lamination of a gate insulating film. The horizontal axis represents the gate voltage (Gate Voltage [V]), and the vertical axis represents the current (Jg [A/cm 2 ]). For example, the IV characteristics of the semiconductor device shown in Fig. 28 were investigated. Among them, the gate electrode is a single layer. As Ref, No. 1, No. 2, and No. 3, a laminated film of Al 2 O 3 /SiO 2 was used, and the film thickness of SiO 2 was set to 0 nm, 3 nm, 5 nm, and 10 nm. In the case of No. 1, No. 2, and No. 3, when the film thickness of SiO 2 is set to 3 nm to 10 nm, the rising voltage of the current becomes high. It is considered that this is achieved by the offset effect of the flat band voltage Vfb and the effect of increasing the withstand voltage.

並且，若於上述閘極絕緣膜之積層構造上加上閘極電極之積層構造，則能夠維持平帶電壓Vfb之偏移效果，因此能夠維持上述電流之上升電壓。 In addition, when the laminated structure of the gate electrode is added to the laminated structure of the gate insulating film, the effect of shifting the flat band voltage Vfb can be maintained, and thus the rising voltage of the current can be maintained.

(實施形態4) (Embodiment 4)

於實施形態1(圖1)中，將閘極絕緣膜GI設為2層(GIa、GIb)，但亦可將閘極絕緣膜GI設為3層，於第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之積層膜之下層(基板或通道層側)設置第3閘極絕緣膜(最下層閘極絕緣膜)GIu。並且，作為構成該第3閘極絕緣膜(最下層閘極絕緣膜)GIu之元素，可使用Si(半導體)。 In the first embodiment (FIG. 1), the gate insulating film GI is made of two layers (GIa, GIb), but the gate insulating film GI may be three layers, and the first gate insulating film GIa and the first The third gate insulating film (the lowermost gate insulating film) GIu is provided on the lower layer (the substrate or the channel layer side) of the laminated film of the gate insulating film GIb. Further, as an element constituting the third gate insulating film (the lowermost gate insulating film) GIu, Si (semiconductor) can be used.

[構造說明] [structural description]

圖30係表示本實施形態之半導體裝置之構成之剖視圖。本實施形態之半導體裝置除了以3層構成閘極絕緣膜GI以外，其他與實施形態1之情形相同。 Fig. 30 is a cross-sectional view showing the configuration of the semiconductor device of the embodiment. The semiconductor device of the present embodiment is the same as the case of the first embodiment except that the gate insulating film GI is formed of three layers.

如圖30所示，於本實施形態之半導體裝置中，與實施形態1之情形同樣地包含介隔閘極絕緣膜GI配置於包含氮化物半導體之通道層CH上之閘極電極GE(GEa、GEb)。 As shown in FIG. 30, in the semiconductor device of the present embodiment, as in the case of the first embodiment, the gate electrode GE (GEa, which is disposed on the channel layer CH including the nitride semiconductor, is provided with the barrier gate insulating film GI. GEb).

此處，閘極絕緣膜GI包含形成於通道層CH上之作為第3閘極絕緣膜GIu之氧化矽膜(SiO2)、形成於第3閘極絕緣膜GIu上之第1閘極絕緣膜GIa、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。第1閘極絕 緣膜GIa包含第1金屬之氧化物。第2閘極絕緣膜GIb包含第2金屬之氧化物。並且，第2金屬之陰電性低於第1金屬之陰電性。又，第1金屬之陰電性低於Si之陰電性。 Here, the gate insulating film GI includes a tantalum oxide film (SiO 2 ) as a third gate insulating film GUI formed on the channel layer CH, and a first gate insulating film formed on the third gate insulating film GIU. GIa, the second gate insulating film GIb formed on the first gate insulating film GIa. The first gate insulating film GIa includes an oxide of the first metal. The second gate insulating film GIb includes an oxide of the second metal. Further, the cathode of the second metal is lower than the cathode of the first metal. Moreover, the cathode electrical property of the first metal is lower than the cathode electrical property of Si.

又，閘極電極GE包含形成於通道層CH上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb，包含與實施形態1中所說明之閘極電極(第1閘極電極GEa、第2閘極電極GEb)同樣之材料。亦即，第1閘極電極GEa包含第3金屬之氮化物(含有第3金屬之氮化物、第3金屬之氮化膜)。第2閘極電極GEb包含第4金屬。並且，較佳為第3金屬之氮化物之氮(N)與第3金屬(M3)之組成比N/M3大於1。又，第4金屬之膜厚較佳為50nm以上。 Further, the gate electrode GE includes a first gate electrode GEa formed on the channel layer CH and a second gate electrode GEb formed on the first gate electrode GEa, and includes the gate electrode described in the first embodiment. (The first gate electrode GEa and the second gate electrode GEb) are made of the same material. In other words, the first gate electrode GEa includes a nitride of a third metal (a nitride containing a third metal and a nitride film of a third metal). The second gate electrode GEb includes a fourth metal. Further, it is preferable that the composition ratio N/M3 of the nitrogen (N) to the third metal (M3) of the nitride of the third metal is larger than 1. Further, the film thickness of the fourth metal is preferably 50 nm or more.

如上所述，設置氧化矽膜(SiO2)作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu。於此情形時，可使分別構成3層閘極絕緣膜(GIu、GIa、GIb)之元素(Si、M1、M2)之陰電性自下層側起依序變小。藉此，能夠使實施形態1中所說明之氧之極化效果變大，平帶電壓Vfb之偏移量變大。 As described above, a ruthenium oxide film (SiO 2 ) is provided as the third gate insulating film (the lowermost gate insulating film) GIu. In this case, the anion properties of the elements (Si, M1, M2) constituting the three-layer gate insulating film (GIu, Gia, GIb) can be sequentially reduced from the lower layer side. Thereby, the polarization effect of oxygen described in the first embodiment can be increased, and the amount of shift of the flat band voltage Vfb can be increased.

又，與實施形態1之情形同樣地將閘極電極GE設為積層構造、亦即積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬之構成，藉此能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。特別是即使於形成閘極絕緣膜GI之後實施退火處理之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 In the same manner as in the first embodiment, the gate electrode GE has a laminated structure, that is, a nitride containing a third metal and a fourth metal are laminated, and a fourth metal is disposed on the upper layer, thereby preventing the gate electrode GE from being laminated. Oxygen diffuses to the gate insulating film GI, maintains the polarization of oxygen (the layering effect of the gate insulating film), and maintains the offset effect of the flat band voltage Vfb. In particular, even in the case where the annealing treatment is performed after the formation of the gate insulating film GI, the diffusion of oxygen due to the annealing treatment can be reduced, and the layering effect of the gate insulating film can be maintained.

[製法說明] [Method Description]

其次，對本實施形態之半導體裝置之製造方法加以說明。於本實施形態之半導體裝置之製造方法中，除了閘極絕緣膜GI之形成步驟以外，其他與實施形態1之情形相同。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described. The method of manufacturing the semiconductor device of the present embodiment is the same as the case of the first embodiment except for the step of forming the gate insulating film GI.

亦即，以與實施形態1同樣之方式對通道層(i-GaN層、GaN基 板)CH之表面進行清洗後，使用堆積法於通道層CH上堆積氧化矽膜(SiO2膜)作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu。 In other words, the surface of the channel layer (i-GaN layer, GaN substrate) CH is cleaned in the same manner as in the first embodiment, and then a tantalum oxide film (SiO 2 film) is deposited on the channel layer CH by the deposition method as the third. Gate insulating film (lowest gate insulating film) GIu.

例如，將三-二甲基胺基矽烷(SiH(N(CH3)2)3、TDMAS)及臭氧(O3、氧化劑)作為原料氣體，於480℃之氛圍中，使用ALD法堆積3nm左右之膜厚之氧化矽膜(SiO2膜)。氧化矽膜之膜厚例如可於3nm~20nm之範圍內調整。除了ALD法以外，亦可使用CVD法(熱CVD或電漿CVD法等)堆積氧化矽膜。再者，根據本發明者之研究，即使是3~5nm左右之膜厚，亦能夠藉由上述氧之極化而獲得充分之平帶電壓Vfb之偏移效果。 For example, tris-dimethylamino decane (SiH(N(CH 3 ) 2 ) 3 , TDMAS) and ozone (O 3 , oxidizing agent) are used as raw material gases, and are stacked in an atmosphere of 480 ° C using an ALD method of about 3 nm. A cerium oxide film (SiO 2 film) having a film thickness. The film thickness of the ruthenium oxide film can be adjusted, for example, in the range of 3 nm to 20 nm. In addition to the ALD method, a ruthenium oxide film may be deposited by a CVD method (thermal CVD, plasma CVD, or the like). Further, according to the study by the inventors of the present invention, even if the film thickness is about 3 to 5 nm, the effect of shifting the sufficient flat band voltage Vfb can be obtained by the polarization of the oxygen.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第3閘極絕緣膜GIu(此處為氧化矽膜)中之陷阱(陷阱能階、缺陷)。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the third gate insulating film GUI (here, the hafnium oxide film) can be reduced.

其次，於第3閘極絕緣膜GIu上形成第1閘極絕緣膜(第1金屬之氧化膜)GIa。例如，以與實施形態1同樣之方式，以50nm~100nm左右之膜厚堆積氧化鋁膜(Al2O3膜)作為第1閘極絕緣膜GIa。 Next, a first gate insulating film (an oxide film of the first metal) GGa is formed on the third gate insulating film GIu. For example, in the same manner as in the first embodiment, an aluminum oxide film (Al 2 O 3 film) is deposited as a first gate insulating film GIa with a film thickness of about 50 nm to 100 nm.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、I分鐘左右之熱處理。藉由該熱處理，能夠減低第1閘極絕緣膜GIa(此處為氧化鋁膜)中之陷阱(陷阱能階、缺陷)。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the first gate insulating film GIa (here, the aluminum oxide film) can be reduced.

其次，於第1閘極絕緣膜GIa上形成第2閘極絕緣膜(第2金屬之氧化膜)GIb。例如，以與實施形態1同樣之方式，以2nm左右之膜厚堆積氧化鉿膜(HfO2膜)作為第2閘極絕緣膜GIb。 Next, a second gate insulating film (an oxide film of the second metal) GIb is formed on the first gate insulating film GIa. For example, in the same manner as in the first embodiment, a ruthenium oxide film (HfO 2 film) is deposited as a second gate insulating film GIb at a film thickness of about 2 nm.

其次，進行熱處理。例如，於氮(N2)氛圍中，實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第2閘極絕緣膜GIb(此處為氧化鉿膜)中之陷阱(陷阱能階、缺陷)。再者，於上述步驟中，於形成各閘極絕緣膜(GIu、GIa、GIb)之後個別地進行熱處理，但亦可於形成第2閘極絕緣膜GIb之後一次性進行熱處理。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the second gate insulating film GIb (here, the hafnium oxide film) can be reduced. Further, in the above step, after each of the gate insulating films (GIu, GIa, GIb) is formed, the heat treatment is performed individually, but the heat treatment may be performed once after the formation of the second gate insulating film GIb.

如此般，能夠形成自下方起依序積層有第3閘極絕緣膜GIu(氧化矽膜)、第1閘極絕緣膜GIa(氧化鋁膜)及第2閘極絕緣膜GIb(氧化鉿膜)之閘極絕緣膜GI。 In this manner, the third gate insulating film GIu (yttria film), the first gate insulating film GIa (aluminum oxide film), and the second gate insulating film GIb (yttria film) can be sequentially formed from the bottom. The gate insulating film GI.

其次，以與實施形態1同樣之方式於閘極絕緣膜GI上形成閘極電極GE(GEa、GEb)。 Then, gate electrodes GE (GEa, GEb) are formed on the gate insulating film GI in the same manner as in the first embodiment.

再者，亦可將本實施形態之3層之閘極絕緣膜GI用作實施形態2之閘極絕緣膜GI。 Further, the gate insulating film GI of the third layer of the present embodiment can be used as the gate insulating film GI of the second embodiment.

(實施形態5) (Embodiment 5)

於實施形態4(圖30)中，使用氧化矽膜作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu，但亦可設置氮化矽膜。 In the fourth embodiment (Fig. 30), a hafnium oxide film is used as the third gate insulating film (lowest gate insulating film) GIU, but a tantalum nitride film may be provided.

[構造說明] [structural description]

圖31係表示本實施形態之半導體裝置之構成之剖視圖。本實施形態之半導體裝置除了閘極絕緣膜GI之第3閘極絕緣膜(最下層閘極絕緣膜)GIu以外，其他與實施形態4之情形相同。 Figure 31 is a cross-sectional view showing the configuration of a semiconductor device of the present embodiment. The semiconductor device of the present embodiment is the same as the case of the fourth embodiment except for the third gate insulating film (the lowermost gate insulating film) GIu of the gate insulating film GI.

如圖31所示般，於本實施形態之半導體裝置中，與實施形態1之情形同樣地包含介隔閘極絕緣膜GI配置於包含氮化物半導體之通道層CH上之閘極電極GE(GEa、GEb)。 As in the case of the first embodiment, the semiconductor device of the present embodiment includes a gate electrode GE (GEa) in which the gate insulating film GI is disposed on the channel layer CH including the nitride semiconductor, as in the case of the first embodiment. , GEb).

此處，閘極絕緣膜GI包含形成於通道層CH上之作為第3閘極絕緣膜GIu之氮化矽膜(SiNX)、形成於第3閘極絕緣膜GIu上之第1閘極絕緣膜GIa、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。又，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb。 Here, the gate insulating film GI includes a tantalum nitride film (SiN X ) as a third gate insulating film GUI formed on the channel layer CH, and a first gate insulating formed on the third gate insulating film GIU The film GIa and the second gate insulating film GIb formed on the first gate insulating film GIa. Further, the gate electrode GE includes a first gate electrode GEa formed on the second gate insulating film GIb and a second gate electrode GEb formed on the first gate electrode GEa.

如上所述，設置氮化矽膜(SiNX)作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu。於此情形時，氮化矽膜(GIu)不含氧，因此於與第1閘極絕緣膜GIa之界面並不產生氧之極化，藉由第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之界面所產生之極化而使平帶電壓Vfb向正方向偏移。 As described above, a tantalum nitride film (SiN X ) is provided as the third gate insulating film (lowest gate insulating film) GIU. In this case, the tantalum nitride film (GIu) does not contain oxygen, so that no polarization of oxygen is generated at the interface with the first gate insulating film GIa, and the first gate insulating film GMa and the second gate are formed. The polarization generated by the interface of the insulating film GIb shifts the flat band voltage Vfb in the positive direction.

又，藉由使用氮化矽膜(SiNX)作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu，能夠抑制通道層CH(此處為i-GaN層)之氧化。特別是若GaN層等氮化物半導體被氧化，則於與閘極絕緣膜GI之界面產生大量界面能階。於此情形時，MISFET之遷移率降低。由此，造成MISFET之性能降低。 Further, by using a tantalum nitride film (SiN X ) as the third gate insulating film (lowest gate insulating film) GIU, oxidation of the channel layer CH (here, the i-GaN layer) can be suppressed. In particular, when a nitride semiconductor such as a GaN layer is oxidized, a large amount of interface energy level is generated at the interface with the gate insulating film GI. In this case, the mobility of the MISFET is lowered. As a result, the performance of the MISFET is degraded.

又，為了使閘極絕緣膜GI之膜質提高，有效的是成膜後之氧化退火。然而，若GaN層等氮化物半導體與氧化膜相接，則存在如下之虞：由於氧化退火，氮化物半導體之氧化進一步進行。 Moreover, in order to improve the film quality of the gate insulating film GI, it is effective to oxidize and anneal after film formation. However, when a nitride semiconductor such as a GaN layer is in contact with an oxide film, there is a possibility that oxidation of the nitride semiconductor proceeds further by oxidation annealing.

對此，如本實施形態所示般設置氮化膜作為最下層閘極絕緣膜(第3閘極絕緣膜)GIu之情形時，上述氧化得到抑制。藉此，使處理風險(process risk)之裕度變大。換而言之，能夠抑制由與閘極絕緣膜GI之接觸引起之氮化物半導體之氧化。又，於實施氧化退火之情形時，亦能夠抑制氮化物半導體之氧化。 On the other hand, when the nitride film is provided as the lowermost gate insulating film (third gate insulating film) GIU as in the present embodiment, the above oxidation is suppressed. Thereby, the margin of process risk is increased. In other words, oxidation of the nitride semiconductor caused by contact with the gate insulating film GI can be suppressed. Further, in the case of performing oxidation annealing, oxidation of the nitride semiconductor can also be suppressed.

又，與實施形態1之情形同樣地將閘極電極GE設為積層構造、亦即積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬之構成，藉此能夠防止氧向閘極絕緣膜GI擴散，維持氧之極化(閘極絕緣膜之積層效果)，維持平帶電壓Vfb之偏移效果。特別是即使於形成閘極絕緣膜GI之後實施退火處理之情形時，亦能夠減低由退火處理引起之氧之擴散，維持閘極絕緣膜之積層效果。 In the same manner as in the first embodiment, the gate electrode GE has a laminated structure, that is, a nitride containing a third metal and a fourth metal are laminated, and a fourth metal is disposed on the upper layer, thereby preventing the gate electrode GE from being laminated. Oxygen diffuses to the gate insulating film GI, maintains the polarization of oxygen (the layering effect of the gate insulating film), and maintains the offset effect of the flat band voltage Vfb. In particular, even in the case where the annealing treatment is performed after the formation of the gate insulating film GI, the diffusion of oxygen due to the annealing treatment can be reduced, and the layering effect of the gate insulating film can be maintained.

[製法說明] [Method Description]

其次，對本實施形態之半導體裝置之製造方法加以說明。於本實施形態之半導體裝置之製造方法中，除了第3閘極絕緣膜(最下層閘極絕緣膜)GIu之形成步驟以外，其他與實施形態4之情形相同。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described. The method of manufacturing the semiconductor device of the present embodiment is the same as the case of the fourth embodiment except for the step of forming the third gate insulating film (lowest gate insulating film) GIu.

亦即，以與實施形態1或4同樣之方式對通道層(i-GaN層、GaN基板)CH之表面進行清洗後，使用堆積法於通道層CH上堆積氮化矽膜(SiNX膜)作為第3閘極絕緣膜(最下層閘極絕緣膜)GIu。 That is, after the surface of the channel layer (i-GaN layer, GaN substrate) CH is cleaned in the same manner as in the first or fourth embodiment, a tantalum nitride film (SiN X film) is deposited on the channel layer CH by a deposition method. It is the third gate insulating film (the lowermost gate insulating film) GIU.

例如，將三-二甲基胺基矽烷(SiH(N(CH3)2)3、TDMAS)及氨(NH3)作為原料氣體，於480℃之氛圍中，使用ALD法堆積4nm左右之膜厚之氮化矽膜(SiNX膜)。氮化矽膜之膜厚例如可於1nm~15nm之範圍內調整。除了ALD法以外，亦可使用CVD法(熱CVD或電漿CVD法等)堆積氮化矽膜。 For example, tris-dimethylamino decane (SiH(N(CH 3 ) 2 ) 3 , TDMAS) and ammonia (NH 3 ) are used as raw material gases, and a film of about 4 nm is deposited by an ALD method in an atmosphere of 480 ° C. Thick tantalum nitride film (SiN X film). The film thickness of the tantalum nitride film can be adjusted, for example, in the range of 1 nm to 15 nm. In addition to the ALD method, a tantalum nitride film may be deposited by a CVD method (thermal CVD, plasma CVD, or the like).

其次，進行熱處理。例如，於氮(N2)氛圍中實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第3閘極絕緣膜GIu(此處為氮化矽膜)中之陷阱(陷阱能階、缺陷)。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the third gate insulating film GIu (here, the tantalum nitride film) can be reduced.

其次，於第3閘極絕緣膜GIu上形成第1閘極絕緣膜(第1金屬之氧化膜)GIa。例如，以與實施形態1同樣之方式，以50nm~100nm左右之膜厚堆積氧化鋁膜(Al2O3膜)作為第1閘極絕緣膜GIa。 Next, a first gate insulating film (an oxide film of the first metal) GGa is formed on the third gate insulating film GIu. For example, in the same manner as in the first embodiment, an aluminum oxide film (Al 2 O 3 film) is deposited as a first gate insulating film GIa with a film thickness of about 50 nm to 100 nm.

其次，進行熱處理。例如，於氮(N2)氛圍中實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第1閘極絕緣膜GIa(此處為氧化鋁膜)中之陷阱(陷阱能階、缺陷)。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the first gate insulating film GIa (here, the aluminum oxide film) can be reduced.

其次，於第1閘極絕緣膜GIa上形成第2閘極絕緣膜(第2金屬之氧化膜)GIb。例如，以與實施形態1同樣之方式，以2nm左右之膜厚堆積氧化鉿膜(HfO2膜)作為第2閘極絕緣膜GIb。 Next, a second gate insulating film (an oxide film of the second metal) GIb is formed on the first gate insulating film GIa. For example, in the same manner as in the first embodiment, a ruthenium oxide film (HfO 2 film) is deposited as a second gate insulating film GIb at a film thickness of about 2 nm.

其次，進行熱處理。例如，於氮(N2)氛圍中實施750℃、1分鐘左右之熱處理。藉由該熱處理，能夠減低第2閘極絕緣膜GIb(此處為氧化鉿膜)中之陷阱(陷阱能階、缺陷)。再者，於上述步驟中，於形成各閘極絕緣膜(GIu、GIa、GIb)之後個別地進行熱處理，但亦可於形成第2閘極絕緣膜GIb之後一次性進行熱處理。 Next, heat treatment is performed. For example, heat treatment at 750 ° C for about 1 minute is carried out in a nitrogen (N 2 ) atmosphere. By this heat treatment, the trap (trap level, defect) in the second gate insulating film GIb (here, the hafnium oxide film) can be reduced. Further, in the above step, after each of the gate insulating films (GIu, GIa, GIb) is formed, the heat treatment is performed individually, but the heat treatment may be performed once after the formation of the second gate insulating film GIb.

如此般，能夠形成自下方起依序積層有第3閘極絕緣膜GIu(氮化矽膜)、第1閘極絕緣膜GIa(氧化鋁膜)及第2閘極絕緣膜GIb(氧化鉿膜)之閘極絕緣膜GI。 In this manner, the third gate insulating film GIu (tantalum nitride film), the first gate insulating film GIa (aluminum oxide film), and the second gate insulating film GIb (yttria film) can be formed in this order from the bottom. ) The gate insulating film GI.

其次，以與實施形態1同樣之方式於閘極絕緣膜GI上形成閘極電 極GE(GEa、GEb)。 Next, a gate electrode is formed on the gate insulating film GI in the same manner as in the first embodiment. Extreme GE (GEa, GEb).

再者，亦可將本實施形態之3層之閘極絕緣膜GI用作實施形態2之閘極絕緣膜GI。 Further, the gate insulating film GI of the third layer of the present embodiment can be used as the gate insulating film GI of the second embodiment.

(實施形態6) (Embodiment 6)

於上述實施形態1~5中，使用氮化物半導體(GaN層)作為通道層CH，但亦可使用其他半導體層。於本實施形態中，使用SiC層(SiC基板)。 In the above-described first to fifth embodiments, a nitride semiconductor (GaN layer) is used as the channel layer CH, but other semiconductor layers may be used. In the present embodiment, a SiC layer (SiC substrate) is used.

[構造說明] [structural description]

圖32係表示本實施形態之半導體裝置之構成之剖視圖。 Fig. 32 is a cross-sectional view showing the configuration of the semiconductor device of the embodiment.

如圖32所示般，於本實施形態之半導體裝置中，包含介隔閘極絕緣膜GI配置於包含SiC之通道層CH上之閘極電極GE。 As shown in FIG. 32, in the semiconductor device of the present embodiment, the gate electrode GE is disposed on the channel layer CH including the SiC via the gate insulating film GI.

並且，閘極絕緣膜GI包含形成於通道層CH上之第1閘極絕緣膜GIa、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。又，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb。可於Si等基板上設置SiC層作為通道層CH，又，亦可使用SiC基板作為基板，將該基板用作通道層CH。再者，於閘極電極GE之兩側之通道層CH中，配置有作為n型或p型之雜質注入區域之源極區域SR及汲極區域DR。並且，進而於源極區域SR及汲極區域DR上配置有源極電極SE及汲極電極DE。 Further, the gate insulating film GI includes a first gate insulating film GIa formed on the channel layer CH and a second gate insulating film GIb formed on the first gate insulating film GIa. Further, the gate electrode GE includes a first gate electrode GEa formed on the second gate insulating film GIb and a second gate electrode GEb formed on the first gate electrode GEa. A SiC layer may be provided as a channel layer CH on a substrate such as Si, or a SiC substrate may be used as a substrate, and the substrate may be used as a channel layer CH. Further, in the channel layer CH on both sides of the gate electrode GE, a source region SR and a drain region DR which are n-type or p-type impurity implantation regions are disposed. Further, the source electrode SE and the drain electrode DE are further disposed on the source region SR and the drain region DR.

此處，閘極絕緣膜GI包含形成於通道層CH上之第1閘極絕緣膜GIa、形成於第1閘極絕緣膜GIa上之第2閘極絕緣膜GIb。第1閘極絕緣膜GIa包含氧化矽膜(SiO2)。又，第2閘極絕緣膜GIb包含第2金屬之氧化物。並且，第2金屬之陰電性低於Si之陰電性。換而言之，該閘極絕緣膜GI係將實施形態1之閘極絕緣膜GI之第1金屬之氧化物設為氧化矽膜(SiO2)者。 Here, the gate insulating film GI includes the first gate insulating film GIa formed on the channel layer CH and the second gate insulating film GIb formed on the first gate insulating film GIa. The first gate insulating film GIa contains a hafnium oxide film (SiO 2 ). Further, the second gate insulating film GIb includes an oxide of the second metal. Further, the cathode of the second metal is lower than the cathode of Si. In other words, in the gate insulating film GI, the oxide of the first metal of the gate insulating film GI of the first embodiment is a hafnium oxide film (SiO 2 ).

又，第1閘極絕緣膜(SiO2)GIa可為通道層(SiC層)CH之熱氧化 膜，又，亦可為堆積膜。作為熱氧化法，可使用乾式氧化或濕式氧化。又，亦可使用臭氧進行氧化。作為堆積法，可使用ALD法、CVD法或PVD法。氧化矽膜之膜厚可於1nm~10nm之範圍內調整。 Further, the first gate insulating film (SiO 2 ) Gia may be a thermal oxide film of the channel layer (SiC layer) CH, or may be a deposited film. As the thermal oxidation method, dry oxidation or wet oxidation can be used. Further, it is also possible to oxidize using ozone. As the deposition method, an ALD method, a CVD method, or a PVD method can be used. The film thickness of the ruthenium oxide film can be adjusted within the range of 1 nm to 10 nm.

第2金屬係陰電性低於Si之金屬，例如為鋁(Al)。於此情形時，第1金屬之氧化物成為氧化鋁(Al2O3)。該第1金屬之氧化物之膜厚例如為60nm左右。 The second metal is a metal having a lower anisoelectricity than Si, and is, for example, aluminum (Al). In this case, the oxide of the first metal becomes alumina (Al 2 O 3 ). The film thickness of the oxide of the first metal is, for example, about 60 nm.

作為第2金屬，除了Al以外，可使用Hf、Zr、Ta、Ti、Nb、La、Y、Mg等。此情形時之氧化膜例如成為氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鉭(Ta2O5)、氧化鈦(TiO2)、氧化鈮(Nb2O5)、氧化鑭(La2O3)、氧化釔(Y2O3)、氧化鎂(MgO)。第2金屬與氧之組成比並不限定於上述者。又，作為第2金屬，亦可含有2種以上元素。於此情形時，成為2種金屬與氧之化合物。其中，於此情形時，2種以上元素之陰電性均必須低於Si。其中，含有雜質程度之金屬(例如0.01%濃度以下之金屬)於製造上不可避免，因此有無關陰電性之大小而含有雜質程度之金屬之情況。又，第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之各自之膜厚可根據作為閘極絕緣膜GI而要求之特性或由堆積方法所引起之膜質(介電常數或漏電特性等電氣特性)而選擇適宜之組合。 As the second metal, in addition to Al, Hf, Zr, Ta, Ti, Nb, La, Y, Mg, or the like can be used. In this case, the oxide film is, for example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), niobium oxide (Nb 2 O 5 ), or antimony oxide ( La 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO). The composition ratio of the second metal to oxygen is not limited to the above. Further, the second metal may contain two or more elements. In this case, it is a compound of two kinds of metals and oxygen. In this case, the cathode electrical properties of the two or more elements must be lower than Si. Among them, a metal containing a degree of impurities (for example, a metal having a concentration of 0.01% or less) is unavoidable in production, and therefore, there is a case where a metal having a degree of impurities is contained irrespective of the size of the electrical property. In addition, the film thickness of each of the first gate insulating film GIa and the second gate insulating film GIb can be determined according to the characteristics required as the gate insulating film GI or the film quality (dielectric constant, leakage characteristics, etc.) caused by the deposition method. Select the appropriate combination for electrical characteristics).

又，閘極電極GE包含形成於第2閘極絕緣膜GIb上之第1閘極電極GEa、形成於第1閘極電極GEa上之第2閘極電極GEb。 Further, the gate electrode GE includes a first gate electrode GEa formed on the second gate insulating film GIb and a second gate electrode GEb formed on the first gate electrode GEa.

第1閘極電極GEa係含有第3金屬之氮化膜。作為第3金屬，可使用Ti、Ta、W等。於此情形時，含有第3金屬之氮化膜成為TiN、TaN、WN。作為第3金屬，較佳為具有導電性、加工性高、氧之吸收性或供給性低之金屬。於此方面而言，作為第3金屬，適宜使用Ti。 The first gate electrode GEa contains a nitride film of a third metal. As the third metal, Ti, Ta, W, or the like can be used. In this case, the nitride film containing the third metal is TiN, TaN, and WN. As the third metal, a metal having high conductivity, high workability, and low oxygen absorption or supply property is preferable. In this regard, Ti is preferably used as the third metal.

第2閘極電極GEb包含第4金屬。作為第4金屬，可使用W、Ru、Ir。作為第4金屬，較佳為即使於氧化後亦具有導電性、加工性高、能夠阻擋氧向下層之第1閘極電極GEa滲入者。於此方面而言，作為 第4金屬，適宜使用W。 The second gate electrode GEb includes a fourth metal. As the fourth metal, W, Ru, and Ir can be used. The fourth metal is preferably one which has conductivity and high workability even after oxidation, and can penetrate the first gate electrode GEa of the lower layer of oxygen. In this respect, as For the fourth metal, W is suitably used.

如上所述，於本實施形態中，作為閘極絕緣膜GI，積層使用Si及第2金屬之各自之氧化物，且於上層配置陰電性低於Si之第2金屬之氧化膜，因此能夠使閾值電壓(Vth)為正(Vth>0)(閘極絕緣膜之積層效果)。 As described above, in the present embodiment, as the gate insulating film GI, an oxide of each of Si and the second metal is laminated, and an oxide film of the second metal having a lower electrical property than Si is disposed in the upper layer. The threshold voltage (Vth) is made positive (Vth>0) (layering effect of the gate insulating film).

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬，因此能夠防止氧向閘極絕緣膜GI擴散，減低閾值電壓(Vth)之不均一。特別是即使經過後述之退火處理，亦能夠減低氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is disposed on the upper layer. Therefore, it is possible to prevent oxygen from diffusing into the gate insulating film GI and to reduce the threshold voltage (Vth). Uniform. In particular, even after the annealing treatment described later, it is possible to reduce the diffusion of oxygen and maintain the layering effect of the gate insulating film.

[製法說明] [Method Description]

其次，對本實施形態之半導體裝置之製造方法加以說明，且使該半導體裝置之構成更明確。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described, and the configuration of the semiconductor device will be further clarified.

首先，準備形成有通道層CH之基板(未圖示)。通道層CH係SiC層。SiC層例如可使用CVD法等形成。亦可使用SiC基板作為基板，將該基板用作通道層CH。 First, a substrate (not shown) in which the channel layer CH is formed is prepared. The channel layer CH is a SiC layer. The SiC layer can be formed, for example, by a CVD method or the like. A SiC substrate can also be used as the substrate, and the substrate can be used as the channel layer CH.

其次，使用硫酸過氧化氫混合物或氨水過氧化氫混合物系溶液等對通道層(SiC層)CH之表面進行清洗。其次，於通道層CH上形成包含第1閘極絕緣膜GIa與第2閘極絕緣膜GIb之閘極絕緣膜GI。 Next, the surface of the channel layer (SiC layer) CH is washed using a sulfuric acid hydrogen peroxide mixture or an aqueous ammonia hydrogen peroxide mixture solution or the like. Next, a gate insulating film GI including the first gate insulating film GIa and the second gate insulating film GIb is formed on the channel layer CH.

首先，於通道層CH上形成第1閘極絕緣膜GIa。例如，藉由乾式氧化形成氧化矽膜(SiO2膜)作為第1閘極絕緣膜GIa。例如，於O2與N2之混合氣體中，進行氧化溫度為1300℃之乾式氧化，例如形成10nm左右之膜厚之氧化矽膜。再者，氧化法並不限定於乾式氧化，亦可為利用其他氧化劑之熱氧化。又，亦可使用CVD法、ALD法、PVD法等堆積法形成氧化矽膜。 First, the first gate insulating film GIa is formed on the channel layer CH. For example, a hafnium oxide film (SiO 2 film) is formed by dry oxidation as the first gate insulating film GIa. For example, in a mixed gas of O 2 and N 2 , dry oxidation at an oxidation temperature of 1300 ° C is performed, for example, a ruthenium oxide film having a film thickness of about 10 nm is formed. Further, the oxidation method is not limited to dry oxidation, and may be thermal oxidation using other oxidizing agents. Further, a hafnium oxide film can also be formed by a deposition method such as a CVD method, an ALD method, or a PVD method.

其次，對第1閘極絕緣膜GIa與通道層CH之界面(SiO2/SiC界面)進行氮化。作為氮化處理，例如於含有一氧化氮(NO)之氛圍下，進行 1000℃、1小時之熱處理。藉由該氮化處理，能夠使上述界面所產生之界面能階(懸鍵等)減低。作為該氮化處理中所使用之氣體，除了上述一氧化氮(NO)以外，亦可使用N2O、NH3等。又，亦可使用該等氣體之混合氣體。又，亦可根據時間切換使用複數種氣體。又，藉由該氮化處理，不僅僅產生氮化反應，亦產生氧化反應(氮氧化處理)。如上所述，較佳為根據氧化矽膜之成膜方法、膜質、界面之界面狀態而進行適宜之膜質改善處理。此處，作為膜質改善處理，例示了對界面能階進行氮化處理之方法，除此以外，亦可進行氫化處理或氮以外之V族化處理(例如磷化)等。於該等處理中，亦能夠實現界面能階之減低。 Next, the interface (SiO 2 /SiC interface) of the first gate insulating film GIa and the channel layer CH is nitrided. As the nitriding treatment, for example, heat treatment at 1000 ° C for 1 hour is performed in an atmosphere containing nitrogen monoxide (NO). By this nitriding treatment, the interface energy level (dwelling key, etc.) generated by the above interface can be reduced. As the gas used in the nitriding treatment, in addition to the above-mentioned nitrogen monoxide (NO), N 2 O, NH 3 or the like can be used. Further, a mixed gas of these gases can also be used. Further, a plurality of gases can be switched depending on the time. Further, by the nitriding treatment, an oxidation reaction (nitrogen oxidation treatment) is generated not only by the nitridation reaction but also by the nitridation reaction. As described above, it is preferred to carry out a suitable film quality improvement treatment depending on the film formation method of the ruthenium oxide film, the interface state of the film quality and the interface. Here, as the film quality improvement treatment, a method of nitriding the interface energy level is exemplified, and other than the above, a hydrogenation treatment or a V group treatment (for example, phosphating) other than nitrogen may be performed. In these processes, the reduction of the interface energy level can also be achieved.

其次，於第1閘極絕緣膜(氧化矽膜)GIa上形成第2閘極絕緣膜(第2金屬之氧化膜)GIb。例如，作為第2閘極絕緣膜GIb，使用堆積法堆積氧化鋁膜(Al2O3膜)。例如，將三甲基鋁(Al(CH3)3、TMA)及H2O(氧化劑)作為原料氣體，於400℃之氛圍中，使用ALD法堆積60nm左右之膜厚之氧化鋁膜(Al2O3膜)。藉由ALD法，能夠控制性、被覆性良好地形成膜質良好之膜。再者，作為氧化劑，除了H2O以外，亦可使用臭氧(O3)。再者，除了ALD法以外，亦可使用氧電漿CVD法形成氧化鋁膜(Al2O3膜)。其次，進行熱處理。例如，於氮(N2)氛圍中實施600℃、30分鐘左右之熱處理。再者，此處，作為第2閘極絕緣膜GIb用金屬，使用Al，但第2金屬亦可使用例如選自Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素之氧化物。 Next, a second gate insulating film (an oxide film of the second metal) GIb is formed on the first gate insulating film (yttria film) GGa. For example, as the second gate insulating film GIb, an aluminum oxide film (Al 2 O 3 film) is deposited by a deposition method. For example, trimethylaluminum (Al(CH 3 ) 3 , TMA) and H 2 O (oxidant) are used as raw material gases, and an aluminum oxide film (Al is deposited by a ALD method with a film thickness of about 60 nm in an atmosphere of 400 ° C. 2 O 3 film). By the ALD method, it is possible to form a film having a good film quality with good controllability and coating properties. Further, as the oxidizing agent, ozone (O 3 ) may be used in addition to H 2 O. Further, in addition to the ALD method, an aluminum oxide film (Al 2 O 3 film) may be formed by an oxy-plasma CVD method. Next, heat treatment is performed. For example, heat treatment at 600 ° C for about 30 minutes is carried out in a nitrogen (N 2 ) atmosphere. In addition, although Al is used as the metal for the second gate insulating film GIb, the second metal may be, for example, one or more selected from the group consisting of Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. The oxide of the element.

如上所述，形成包含第1閘極絕緣膜GIa(氧化矽膜)與第2閘極絕緣膜GIb(氧化鋁膜)之積層膜之閘極絕緣膜GI。 As described above, the gate insulating film GI including the laminated film of the first gate insulating film GIa (yttrium oxide film) and the second gate insulating film GIb (aluminum oxide film) is formed.

其次，以與實施形態1之情形同樣之方式，於閘極絕緣膜GI上形成閘極電極GE。例如，形成氮化鈦膜(TiN膜)作為第1閘極電極GEa，進而於其上形成鎢膜(W膜)作為第2閘極電極GEb。該等之積層膜可使 用多靶濺鍍裝置連續地形成。例如，於第2閘極絕緣膜GIb上，藉由使用Ti金屬靶、及氬(Ar)與氮(N2)之混合氣體之反應性濺鍍法堆積20nm左右之氮化鈦膜。此時，所形成之TiN膜之N與Ti比N/Ti大於1。TiN中之N之比例可藉由調整氬(Ar)與氮(N2)之混合氣體中之氮量而控制。 Next, in the same manner as in the first embodiment, the gate electrode GE is formed on the gate insulating film GI. For example, a titanium nitride film (TiN film) is formed as the first gate electrode GEa, and a tungsten film (W film) is formed thereon as the second gate electrode GEb. These laminated films can be formed continuously using a multi-target sputtering apparatus. For example, a titanium nitride film of about 20 nm is deposited on the second gate insulating film GIb by a reactive sputtering method using a Ti metal target and a mixed gas of argon (Ar) and nitrogen (N 2 ). At this time, the ratio of N to Ti of the formed TiN film is greater than 1 by N/Ti. The ratio of N in the TiN can be controlled by adjusting the amount of nitrogen in the mixed gas of argon (Ar) and nitrogen (N 2 ).

繼而，於第1閘極電極GEa上，藉由使用W金屬靶、氬(Ar)氣體之濺鍍法堆積100nm左右之鎢膜作為第2閘極電極GEb。如實施形態1中所說明般，確認若第2閘極電極(W膜)GEb之膜厚為50nm左右，則氧濃度下降1位，因此關於第2閘極電極(W膜)GEb之膜厚，較佳為50nm以上。又，於成膜第2閘極電極(W膜)GEb之後，將其暴露於大氣中，於以後之步驟中進行熱處理(恢復退火)之情形時，較佳為形成100nm以上之膜厚之W膜。又，第2閘極電極(W膜)GEb之膜厚之上限例如為500nm左右。 Then, on the first gate electrode GEa, a tungsten film of about 100 nm is deposited as a second gate electrode GEb by sputtering using a W metal target or an argon (Ar) gas. As described in the first embodiment, when the film thickness of the second gate electrode (W film) GEb is about 50 nm, the oxygen concentration is lowered by one bit. Therefore, the film thickness of the second gate electrode (W film) GEb is determined. Preferably, it is 50 nm or more. Further, after the second gate electrode (W film) GEb is formed and exposed to the atmosphere, and heat treatment (recovery annealing) is performed in the subsequent step, it is preferable to form a film thickness of 100 nm or more. membrane. Moreover, the upper limit of the film thickness of the second gate electrode (W film) GEb is, for example, about 500 nm.

其次，進行熱處理。該熱處理係用以減低由閘極電極GE之成膜時之電漿或荷電粒子所引起的閘極絕緣膜(Al2O3與HfO2)中之陷阱(陷阱能階、缺陷)之熱處理。作為熱處理條件，只要根據第1閘極電極GEa與第2閘極電極GEb之PVD條件(例如功率或時間)而選擇最合適之溫度、時間等即可。根據本發明者之研究，較佳為於溫度為400℃~600℃、時間為10分鐘~60分鐘之範圍內進行。又，作為熱處理氛圍，例如較佳為使用氮(N2)等惰性氣體之氛圍。 Next, heat treatment is performed. This heat treatment is for heat treatment for reducing traps (trap levels, defects) in the gate insulating film (Al 2 O 3 and HfO 2 ) caused by plasma or charged particles when the gate electrode GE is formed. As the heat treatment conditions, the most suitable temperature, time, and the like may be selected based on the PVD conditions (for example, power or time) of the first gate electrode GEa and the second gate electrode GEb. According to the study by the present inventors, it is preferably carried out at a temperature of from 400 ° C to 600 ° C for a period of from 10 minutes to 60 minutes. Further, as the heat treatment atmosphere, for example, an atmosphere of an inert gas such as nitrogen (N 2 ) is preferably used.

其次，使用光微影技術及蝕刻技術，對第1閘極電極GEa與第2閘極電極GEb進行圖案化(加工)，藉此形成所期望之形狀之閘極電極GE。第2閘極電極GEb覆蓋第1閘極電極GEa之整個上表面。再者，於該閘極電極GE之蝕刻時，亦可對下層之閘極絕緣膜GI進行蝕刻。又，上述熱處理亦可於該圖案化步驟之後進行。作為第1閘極電極GEa之材料，亦可使用容易閘極蝕刻之例如TaN、WN等，作為第2閘極電極GEb，亦可使用例如Ru或Ir等。 Next, the first gate electrode GEa and the second gate electrode GEb are patterned (processed) using a photolithography technique and an etching technique to form a gate electrode GE having a desired shape. The second gate electrode GEb covers the entire upper surface of the first gate electrode GEa. Further, in the etching of the gate electrode GE, the gate insulating film GI of the lower layer may be etched. Further, the above heat treatment may be performed after the patterning step. As the material of the first gate electrode GEa, for example, TaN or WN which is easy to be gate-etched can be used, and as the second gate electrode GEb, for example, Ru or Ir can be used.

其後，於閘極電極GE之兩側之通道層CH中注入n型或p型之雜質，藉此形成源極區域SR及汲極區域DR。其次，於閘極電極GE、源極區域SR及汲極區域DR上，例如使用CVD法等形成氧化矽膜作為絕緣層IL1。其次，藉由使用光微影技術及蝕刻技術，將源極區域SR上及汲極區域DR上之絕緣層IL1利用蝕刻除去，形成接觸孔。其次，於閘極電極GE之兩側之源極區域SR及汲極區域DR上分別形成源極電極SE及汲極電極DE。例如，於包括接觸孔內之絕緣層IL1上形成導電性膜。其次，藉由使用光微影技術及蝕刻技術，對上述導電性膜進行圖案化。再者，亦可使用所謂金屬鑲嵌法形成源極電極SE及汲極電極DE。又，其後亦可於絕緣層IL1上形成複數個配線。 Thereafter, n-type or p-type impurities are implanted into the channel layer CH on both sides of the gate electrode GE, thereby forming the source region SR and the drain region DR. Next, on the gate electrode GE, the source region SR, and the drain region DR, a hafnium oxide film is formed as the insulating layer IL1 by, for example, a CVD method. Next, the insulating layer IL1 on the source region SR and the drain region DR is removed by etching using a photolithography technique and an etching technique to form a contact hole. Next, a source electrode SE and a drain electrode DE are formed on the source region SR and the drain region DR on both sides of the gate electrode GE, respectively. For example, a conductive film is formed on the insulating layer IL1 including the contact hole. Next, the conductive film is patterned by using a photolithography technique and an etching technique. Further, the source electrode SE and the drain electrode DE may be formed by a so-called damascene method. Further, a plurality of wirings may be formed on the insulating layer IL1 thereafter.

藉由以上之步驟，能夠形成本實施形態之半導體裝置。 The semiconductor device of this embodiment can be formed by the above steps.

如上所述，於本實施形態中，將Si之氧化物與其上所配置之陰電性低於Si之第2金屬之氧化物的積層膜用作閘極絕緣膜GI，因此能夠與實施形態1之情形同樣地使平帶電壓(Vfb)向正方向偏移。藉此，能夠使閾值電壓(Vth)向正方向偏移。並且，藉由調整偏移量，能夠使閾值電壓(Vth)為正(Vth>0)，能夠使常斷開特性提高。 As described above, in the present embodiment, the laminated film of the oxide of Si and the oxide of the second metal having a lower electrical property than that of Si is used as the gate insulating film GI, and therefore, the first embodiment can be used. In the same situation, the flat band voltage (Vfb) is shifted in the positive direction. Thereby, the threshold voltage (Vth) can be shifted in the positive direction. Further, by adjusting the offset amount, the threshold voltage (Vth) can be made positive (Vth>0), and the normally-off characteristic can be improved.

又，作為閘極電極GE，積層使用含有第3金屬之氮化物及第4金屬，且於上層配置第4金屬，因此能夠與實施形態1之情形同樣地防止氧向閘極絕緣膜GI擴散，減低閾值電壓(Vth)之不均一。特別是即使經過後述之退火處理，亦能夠減低氧之擴散，維持閘極絕緣膜之積層效果。 In addition, as the gate electrode GE, the nitride containing the third metal and the fourth metal are laminated, and the fourth metal is disposed in the upper layer. Therefore, in the same manner as in the first embodiment, oxygen can be prevented from diffusing into the gate insulating film GI. Reduce the non-uniformity of the threshold voltage (Vth). In particular, even after the annealing treatment described later, it is possible to reduce the diffusion of oxygen and maintain the layering effect of the gate insulating film.

進而，藉由使第3金屬之氮化物的氮(N)與第3金屬(M3)之組成比N/M3大於1，能夠起到與實施形態1同樣之效果。 Further, by making the composition ratio N/M3 of nitrogen (N) of the nitride of the third metal to the third metal (M3) larger than 1, the same effect as in the first embodiment can be obtained.

進而，藉由將SiC層作為通道層CH，使平帶電壓Vfb向正方向偏移，使閾值電壓(Vth)向正方向偏移，能夠使通道層CH之Vth控制用雜質濃度降低。雜質使在通道層CH內移行之載子(電子或電洞)之遷移率 降低(雜質散射)。因此，藉由使通道層之雜質濃度降低，能夠使載子之遷移率提高，其結果使MISFET之接通電流增加。遷移率依存於形成MISFET之結晶面，SiC層之遷移率小於Si層之遷移率，因此遷移率之提高效果有用。 Further, by using the SiC layer as the channel layer CH, the flat band voltage Vfb is shifted in the positive direction, and the threshold voltage (Vth) is shifted in the positive direction, whereby the Vth control impurity concentration of the channel layer CH can be lowered. The mobility of carriers (electrons or holes) that move impurities in the channel layer CH Reduce (impurity scattering). Therefore, by lowering the impurity concentration of the channel layer, the mobility of the carrier can be increased, and as a result, the on-current of the MISFET is increased. The mobility is dependent on the crystal plane on which the MISFET is formed, and the mobility of the SiC layer is smaller than the mobility of the Si layer, so that the effect of improving the mobility is useful.

再者，於本實施形態中，作為閘極絕緣膜GI，使用氧化矽膜與氧化鋁膜之積層膜(例如與實施形態3對應)，亦可應用其他實施形態1、4、5中所說明之閘極絕緣膜GI。 In the present embodiment, as the gate insulating film GI, a laminated film of a hafnium oxide film and an aluminum oxide film (for example, corresponding to the third embodiment) may be used, and the other embodiments 1, 4, and 5 may be applied. The gate insulating film GI.

以上，基於實施形態對由本發明者完成之發明加以具體之說明，但本發明並不限定於上述實施形態，可於不脫離其主旨之範圍進行各種變更。 The invention made by the inventors of the present invention has been specifically described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[附註1] [Note 1]

一種半導體裝置，其包含：SiC層、設於上述SiC層上之第1閘極絕緣膜、設於上述第1閘極絕緣膜上之第2閘極絕緣膜、設於上述第2閘極絕緣膜上之第1閘極電極、設於上述第1閘極電極上之第2閘極電極；且上述第1閘極絕緣膜係含有第1金屬之氧化膜或含有矽之氧化膜，上述第2閘極絕緣膜係含有第2金屬之氧化膜，上述第2金屬之陰電性小於上述第1金屬或矽之陰電性，上述第1閘極電極係含有第3金屬之氮化膜，上述第2閘極電極包含第4金屬。 A semiconductor device comprising: a SiC layer; a first gate insulating film provided on the SiC layer; a second gate insulating film provided on the first gate insulating film; and the second gate insulating film a first gate electrode on the film, and a second gate electrode provided on the first gate electrode; and the first gate insulating film includes an oxide film of the first metal or an oxide film containing germanium, the first The gate insulating film includes an oxide film of the second metal, wherein the second metal has a lower electrical property than the first metal or the negative electrode, and the first gate electrode includes a nitride film of the third metal. The second gate electrode includes a fourth metal.

[附註2] [Note 2]

如附註1之半導體裝置，其中上述第1金屬係Al。 A semiconductor device according to claim 1, wherein said first metal is Al.

[附註3] [Note 3]

如附註2之半導體裝置，其中上述第2金屬係選自Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素。 The semiconductor device according to the second aspect, wherein the second metal is one or more elements selected from the group consisting of Hf, Zr, Ta, Ti, Nb, La, Y, and Mg.

[附註4] [Note 4]

如附註3之半導體裝置，其中上述第3金屬係Ti。 A semiconductor device according to the third aspect, wherein the third metal is Ti.

[附註5] [Note 5]

如附註4之半導體裝置，其中上述含有第3金屬之氮化膜係氮化鈦，鈦(Ti)與氮(N)之比(N/Ti)大於1。 A semiconductor device according to the fourth aspect, wherein the nitride film containing the third metal is titanium nitride, and a ratio (N/Ti) of titanium (Ti) to nitrogen (N) is more than 1.

[附註6] [Note 6]

如附註4之半導體裝置，其中上述第4金屬係W。 A semiconductor device according to the fourth aspect, wherein the fourth metal system W is the same.

[附註7] [Note 7]

如附註6之半導體裝置，其中上述第2閘極電極之膜厚為50nm以上。 A semiconductor device according to the sixth aspect, wherein the film thickness of the second gate electrode is 50 nm or more.

[附註8] [Note 8]

如附註6之半導體裝置，其中上述第1閘極電極覆蓋上述第2閘極電極之整個上表面。 A semiconductor device according to the sixth aspect, wherein the first gate electrode covers the entire upper surface of the second gate electrode.

[附註9] [Note 9]

一種半導體裝置之製造方法，其包含：(a)準備氮化物半導層之步驟，(b)於上述氮化物半導體層上形成包含含有第1金屬之氧化膜或含有矽之氧化膜的第1閘極絕緣膜之步驟，(c)於上述第1閘極絕緣膜上形成包含第2金屬之氧化膜的第2閘極 絕緣膜之步驟，(d)於上述第2閘極絕緣膜上形成包含含有第3金屬之氮化膜的第1閘極電極之步驟，(e)於上述第1閘極電極上形成包含第4金屬之第2閘極電極之步驟；且上述第2金屬之陰電性小於上述第1金屬或矽之陰電性。 A method of manufacturing a semiconductor device, comprising: (a) preparing a nitride semiconductor layer, and (b) forming a first oxide film containing a first metal or an oxide film containing germanium on the nitride semiconductor layer a step of forming a gate insulating film, (c) forming a second gate including an oxide film of the second metal on the first gate insulating film a step of insulating the film, (d) forming a first gate electrode including a nitride film containing a third metal on the second gate insulating film, and (e) forming the first gate electrode a step of the second gate electrode of the metal; and the cathode electrical property of the second metal is less than the cathode electrical property of the first metal or tantalum.

[附註10] [Note 10]

如附註8之半導體裝置之製造方法，其中於上述(d)步驟至上述(e)步驟中，於形成上述第1閘極電極之後，並不暴露於空氣中而形成上述第2閘極電極。 A method of manufacturing a semiconductor device according to the eighth aspect, wherein in the step (d) to the step (e), after the first gate electrode is formed, the second gate electrode is formed without being exposed to the air.

[附註11] [Note 11]

如附註9之半導體裝置之製造方法，其中上述第1閘極絕緣膜包含含有矽之氧化膜，上述第2金屬係選自Al、Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素，上述第3金屬係Ti，上述第4金屬係W。 The method of manufacturing a semiconductor device according to the ninth aspect, wherein the first gate insulating film includes an oxide film containing germanium, and the second metal is selected from the group consisting of Al, Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. One or more elements of the group, the third metal system Ti, and the fourth metal system W.

[附註12] [Note 12]

如附註1之半導體裝置，其中上述第1閘極絕緣膜包含含有矽之氧化膜，上述第2金屬係選自Al、Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素，上述第3金屬係Ti，上述第4金屬係W。 The semiconductor device according to the first aspect, wherein the first gate insulating film includes an oxide film containing germanium, and the second metal is selected from the group consisting of Al, Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. The above elements are the third metal-based Ti and the fourth metal-based W.

CH‧‧‧通道層 CH‧‧‧ channel layer

GE‧‧‧閘極電極 GE‧‧‧gate electrode

GEa‧‧‧第1閘極電極 GEa‧‧1st gate electrode

GEb‧‧‧第2閘極電極 GEb‧‧‧2nd gate electrode

GI‧‧‧閘極絕緣膜 GI‧‧‧gate insulating film

GIa‧‧‧第1閘極絕緣膜 GIa‧‧1 first gate insulating film

GIb‧‧‧第2閘極絕緣膜 GIb‧‧‧2nd gate insulating film

Claims (21)

一種半導體裝置，其包含：氮化物半導體層、設於上述氮化物半導體層上之第1閘極絕緣膜、設於上述第1閘極絕緣膜上之第2閘極絕緣膜、設於上述第2閘極絕緣膜上之第1閘極電極、設於上述第1閘極電極上之第2閘極電極；且上述第1閘極絕緣膜係含有第1金屬之氧化膜或含有矽之氧化膜，上述第2閘極絕緣膜係含有第2金屬之氧化膜，上述第2金屬之陰電性小於上述第1金屬或矽之陰電性，上述第1閘極電極係含有第3金屬之氮化膜，上述第2閘極電極包含第4金屬。 A semiconductor device comprising: a nitride semiconductor layer; a first gate insulating film provided on the nitride semiconductor layer; and a second gate insulating film provided on the first gate insulating film; a first gate electrode on the gate insulating film and a second gate electrode provided on the first gate electrode; and the first gate insulating film contains an oxide film of the first metal or an oxide containing germanium In the film, the second gate insulating film contains an oxide film of a second metal, wherein the second metal has a lower electrical property than the first metal or tantalum, and the first gate electrode contains a third metal. In the nitride film, the second gate electrode includes a fourth metal. 如請求項1之半導體裝置，其中上述第1金屬係Al。 The semiconductor device of claim 1, wherein the first metal is Al. 如請求項2之半導體裝置，其中上述第2金屬係選自Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素。 The semiconductor device according to claim 2, wherein the second metal is one or more elements selected from the group consisting of Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. 如請求項3之半導體裝置，其中上述第3金屬係Ti。 The semiconductor device of claim 3, wherein the third metal is Ti. 如請求項4之半導體裝置，其中上述含有第3金屬之氮化膜係氮化鈦，鈦(Ti)與氮(N)之比(N/Ti)大於1。 The semiconductor device according to claim 4, wherein the nitride film containing the third metal is titanium nitride, and a ratio (N/Ti) of titanium (Ti) to nitrogen (N) is more than 1. 如請求項4之半導體裝置，其中上述第4金屬係W。 A semiconductor device according to claim 4, wherein said fourth metal system W is. 如請求項6之半導體裝置，其中上述第2閘極電極之膜厚為50nm以上。 The semiconductor device according to claim 6, wherein the film thickness of the second gate electrode is 50 nm or more. 如請求項6之半導體裝置，其中上述第1閘極電極覆蓋上述第2閘極電極之整個上表面。 The semiconductor device of claim 6, wherein the first gate electrode covers the entire upper surface of the second gate electrode. 如請求項6之半導體裝置，其中上述氮化物半導體層係GaN。 The semiconductor device of claim 6, wherein the nitride semiconductor layer is GaN. 如請求項6之半導體裝置，其中於上述氮化物半導體層與上述第1閘極絕緣膜之間包含第3閘極絕緣膜，上述第3閘極絕緣膜係氧化矽膜或氮化矽膜。 The semiconductor device according to claim 6, wherein the third gate insulating film is included between the nitride semiconductor layer and the first gate insulating film, and the third gate insulating film is a hafnium oxide film or a tantalum nitride film. 一種半導體裝置，其包含：形成於基板上方之第1氮化物半導體層、形成於上述第1氮化物半導體層上之第2氮化物半導體層、貫通上述第2氮化物半導體層，到達至上述第1氮化物半導體層之溝、介隔閘極絕緣膜而配置於上述溝內之閘極電極；且上述閘極絕緣膜包含設於上述第1氮化物半導體層上之第1閘極絕緣膜、與設於上述第1閘極絕緣膜上之第2閘極絕緣膜，上述閘極電極包含設於上述第2閘極絕緣膜上之第1閘極電極、與設於上述第1閘極電極上之第2閘極電極，上述第1閘極絕緣膜係含有第1金屬之氧化膜或含有矽之氧化膜，上述第2閘極絕緣膜係含有第2金屬之氧化膜，上述第2金屬之陰電性小於上述第1金屬或矽之陰電性，上述第1閘極電極係含有第3金屬之氮化膜，上述第2閘極電極包含第4金屬。 A semiconductor device comprising: a first nitride semiconductor layer formed on a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and a second nitride semiconductor layer extending through the second nitride semiconductor layer a trench of a nitride semiconductor layer, a gate electrode disposed in the trench via a gate insulating film, and the gate insulating film includes a first gate insulating film provided on the first nitride semiconductor layer, And a second gate insulating film provided on the first gate insulating film, wherein the gate electrode includes a first gate electrode provided on the second gate insulating film, and a first gate electrode provided on the first gate electrode In the second gate electrode, the first gate insulating film includes an oxide film of a first metal or an oxide film containing germanium, and the second gate insulating film contains an oxide film of a second metal, and the second metal The cathode electrical property is less than the cathode electrical property of the first metal or tantalum, the first gate electrode includes a nitride film of a third metal, and the second gate electrode includes a fourth metal. 一種半導體裝置之製造方法，其包含：(a)準備氮化物半導層之步驟、(b)於上述氮化物半導體層上形成包含含有第1金屬之氧化膜或含有矽之氧化膜的第1閘極絕緣膜之步驟、(c)於上述第1閘極絕緣膜上形成包含第2金屬之氧化膜的第2閘極絕緣膜之步驟、(d)於上述第2閘極絕緣膜上形成包含含有第3金屬之氮化膜的第1閘極電極之步驟、(e)於上述第1閘極電極上形成包含第4金屬之第2閘極電極之步驟；且上述第2金屬之陰電性小於上述第1金屬或矽之陰電性。 A method of manufacturing a semiconductor device, comprising: (a) a step of preparing a nitride semiconductor layer; and (b) forming a first layer including an oxide film containing a first metal or an oxide film containing germanium on the nitride semiconductor layer a step of forming a gate insulating film, (c) forming a second gate insulating film including an oxide film of the second metal on the first gate insulating film, and (d) forming the second gate insulating film a step of including a first gate electrode including a nitride film of a third metal, (e) a step of forming a second gate electrode including a fourth metal on the first gate electrode; and a cathode of the second metal The electrical property is less than the electrical conductivity of the first metal or tantalum. 如請求項12之半導體裝置之製造方法，其中於上述(d)步驟至上述(e)步驟中，於上述第1閘極電極之形成後，並不暴露於空氣中而形成上述第2閘極電極。 The method of manufacturing a semiconductor device according to claim 12, wherein in the steps (d) to (e), after the forming of the first gate electrode, the second gate is formed without being exposed to air. electrode. 如請求項13之半導體裝置之製造方法，其中於上述(e)步驟後，包含：(f)於惰性氣體氛圍下進行熱處理之步驟。 The method of manufacturing a semiconductor device according to claim 13, wherein after the step (e), the method comprises: (f) performing a heat treatment in an inert gas atmosphere. 如請求項13之半導體裝置之製造方法，其中於上述(e)步驟後，包含：(g)將上述第1閘極電極及上述第2閘極電極之積層膜加工為第1形狀之步驟。 The method of manufacturing a semiconductor device according to claim 13, wherein the step (e) includes: (g) processing the laminated film of the first gate electrode and the second gate electrode into a first shape. 如請求項12之半導體裝置之製造方法，其中上述第1金屬係Al。 The method of manufacturing a semiconductor device according to claim 12, wherein the first metal is Al. 如請求項16之半導體裝置之製造方法，其中上述第2金屬係選自Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之 一種以上元素。 The method of manufacturing a semiconductor device according to claim 16, wherein the second metal is selected from the group consisting of Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. More than one element. 如請求項17之半導體裝置之製造方法，其中上述第3金屬係Ti。 The method of manufacturing a semiconductor device according to claim 17, wherein the third metal is Ti. 如請求項18之半導體裝置之製造方法，其中上述第4金屬係W。 The method of manufacturing a semiconductor device according to claim 18, wherein the fourth metal system W is. 如請求項19之半導體裝置之製造方法，其中上述氮化物半導體層係GaN。 The method of manufacturing a semiconductor device according to claim 19, wherein the nitride semiconductor layer is GaN. 如請求項12之半導體裝置之製造方法，其中上述第1閘極絕緣膜包含含有矽之氧化膜，上述第2金屬係選自Al、Hf、Zr、Ta、Ti、Nb、La、Y、Mg之群之一種以上元素，上述第3金屬係Ti，上述第4金屬係W。 The method of manufacturing a semiconductor device according to claim 12, wherein the first gate insulating film includes an oxide film containing germanium, and the second metal is selected from the group consisting of Al, Hf, Zr, Ta, Ti, Nb, La, Y, and Mg. One or more elements of the group, the third metal system Ti, and the fourth metal system W.
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