TW201705321A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer.

Description

Semiconductor device manufacturing method

The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a manufacturing technique of a semiconductor device that performs flip chip connection.

In a semiconductor device in which a semiconductor wafer is mounted on a substrate by flip chip connection, a resin (underfill) is disposed in a gap between the semiconductor wafer and the substrate, and a connection portion for protecting the flip chip is protected by the resin.

The above-mentioned underfill is formed by a method of pre-installing a resin on a substrate before mounting a semiconductor wafer, and a post-mounting method of flowing a resin into the gap after mounting the semiconductor wafer. An example of the above-described pre-installation method is NCF. The method of (non-conductive insulating film; Non-Conductive Film) is known. NCF is a film-shaped insulating adhesive material, and has a property of flowing once heated.

In recent years, the number of bumps in semiconductor wafers has increased with the increase in the number of functions of semiconductor devices, and as a result, bumps have been used. There are many cases where the pitch is fine pitch (narrow pitch). Further, when the pitch between the bumps is a fine pitch, since the bump size is also small, the gap between the semiconductor wafer and the substrate is also narrowed. For example, even when the substrate is formed with a bend of an allowable range, the resin is hard to flow into the above. Clearance, so the post-installation method is not suitable for fine pitch.

Therefore, when the pitch between the bumps is set to a fine pitch, it is preferable to adopt a pre-installation method.

In addition, a method of manufacturing an electronic component in which a wiring board is attached via an adhesive film is disclosed in Japanese Laid-Open Patent Publication No. 2012-231039 (Patent Document 1).

[prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2012-231039

In the assembly of a semiconductor device in which flip chip connection is performed, when the NCF first mounting method is employed, the adhesion between the substrate and the NCF is important. That is, when the NCF sticker on the substrate is contaminated, the adhesion between the substrate and the NCF is deteriorated, and the NCF is easily peeled off from the substrate. As a result, the quality of the semiconductor device is lowered, and the reliability is also lowered.

Also. Contamination occurs, for example, in baking works. That is, once the organic material such as a substrate or a resin is heat-treated, various chemicals are used. The substance is released, and the substrate or the like attached to the semiconductor device being manufactured is contaminated.

Other problems and novel features will be apparent from the description and the drawings of the specification.

A method of manufacturing a semiconductor device according to the embodiment includes: (a) a step of plasma-cleaning the upper surface of the upper and lower wafer support substrates on which a plurality of electrodes are formed; (b) the above (a) After the project, the insulating adhesive is placed on the upper surface of the wafer supporting substrate; and (c) after the above (b), the semiconductor wafer is mounted on the upper surface of the wafer supporting substrate via the insulating adhesive. engineering.

Further, after the (c) project, the wafer supporting substrate on which the semiconductor wafer is mounted and the insulating adhesive are heated by reflow, and the wafer supporting substrate is electrically connected to the wafer supporting substrate via a plurality of protruding electrodes. The engineering of each of the plurality of electrodes and the plurality of electrode pads of the semiconductor wafer.

Further, in the above (d), in a state in which the insulating adhesive is placed around each of the plurality of protruding electrodes, each of the plurality of electrodes is electrically connected to the plurality of electrodes via the plurality of protruding electrodes. Each of the electrode pads.

Further, according to another semiconductor device of one embodiment The manufacturing method includes: (a) a process of mounting a second substrate on a first substrate, wherein the second substrate includes an upper surface and a lower surface on which a plurality of electrodes are formed; (b) after the (a) project, baking the above After the first substrate is processed, and (c) after the above (b), the plasma is washed by the above-mentioned upper substrate.

Further, (d) after the (c) project, the insulating adhesive is placed on the upper surface of the second substrate; and (e) after the above (d), the upper surface of the second substrate is passed through The above-mentioned insulating adhesive material is used to mount a semiconductor wafer.

Further, after the (e) project, the second substrate on which the semiconductor wafer is mounted and the insulating adhesive are heated by reflow, and the second substrate is electrically connected via a plurality of bump electrodes. The engineering of each of the plurality of electrodes and the plurality of electrode pads of the semiconductor wafer.

In the above-mentioned (f), in a state in which the insulating adhesive is placed around each of the plurality of protruding electrodes, each of the plurality of electrodes is electrically connected to the plurality of electrodes via the plurality of protruding electrodes. Each of the electrode pads.

According to the above embodiment, the reliability of the semiconductor device can be improved.

1‧‧‧Si interposer (wafer support substrate, second substrate)

1a‧‧‧above

1b‧‧‧ below

1c‧‧‧through guide hole

1d‧‧‧ wiring layer

1e‧‧‧ alignment mark

1f‧‧‧ wafer loading field

1g‧‧‧electroplated Ni

1h‧‧‧terminal part (electrode)

2‧‧‧Logical Wafers (Semiconductor Wafers)

2a‧‧‧Main face

2b‧‧‧back

2c‧‧‧electrode pads

3‧‧‧ memory chip (semiconductor wafer)

3a‧‧‧Main face

3b‧‧‧back

3c‧‧‧through guide hole

4‧‧‧Cu pillars (protrusion electrodes, columnar electrodes)

5‧‧‧BGA (Ball Grid Array, semiconductor device)

6a, 6b‧‧‧ underfill

7‧‧‧ Cover

7a‧‧‧Edge

7b‧‧‧ top

8‧‧‧BGA ball (external connection terminal, external electrode terminal)

9‧‧‧Printed wiring board (first board)

9a‧‧‧above

9b‧‧‧ below

9c‧‧‧ Guide hole

9d‧‧‧Internal wiring

10‧‧‧NCF (Insulating Adhesive)

10a‧‧‧Basic film

10b‧‧‧ cover film

11‧‧‧Adhesive

12‧‧‧ solder balls

13‧‧‧Solder

14‧‧‧Electroplating Au

15‧‧‧Solder

16‧‧‧Flag transfer board

17‧‧‧ wafer tray

18‧‧‧ chuck

19‧‧‧Jointing tool (head)

19a‧‧‧Adsorption surface

20‧‧‧ platform

21‧‧‧Flip chip adapter

22‧‧‧ Wafer

23‧‧‧Liquid resin

24‧‧‧Many removal of substrates

25‧‧‧Scraper

26‧‧‧ mask

27‧‧‧ platform

28‧‧‧ cream resin

29‧‧‧Printed wiring substrate (wafer supporting substrate)

29a‧‧‧Electrode

30‧‧‧矽 wafer (semiconductor wafer)

31‧‧‧Many removal substrates

32‧‧‧BGA (semiconductor device)

FIG. 1 is a cross-sectional view showing an example of a structure of a semiconductor device according to an embodiment.

FIG. 2 is a flowchart showing an example of an assembly procedure of the semiconductor device shown in FIG. 1.

Fig. 3 is a cross-sectional view showing a structure of a part of the assembly procedure shown in Fig. 2;

Fig. 4 is a cross-sectional view showing a structure of a part of the assembly procedure shown in Fig. 2;

Fig. 5 is a cross-sectional view showing a structure of a part of the assembly procedure shown in Fig. 2;

Fig. 6 is a cross-sectional view showing a structure of a part of the assembly procedure shown in Fig. 2;

Fig. 7 is a cross-sectional view showing a structure of a part of the assembly procedure shown in Fig. 2;

8 is a plan view showing an example of a method of identifying an alignment mark at the time of wafer mounting in the assembly program shown in FIG. 2 .

FIG. 9 is a perspective view showing an example of a mounting method at the time of wafer mounting in the assembly program shown in FIG. 2 .

FIG. 10 is a perspective view showing an example of a mounting method at the time of wafer mounting in the assembly program shown in FIG. 2 .

FIG. 11 is a cross-sectional view showing an example of a state of adsorption of a wafer during wafer mounting of the assembly program shown in FIG. 2 .

FIG. 12 is an enlarged cross-sectional view showing an example of a structure before and after connection in a flip chip connection of the assembly program shown in FIG. 2 .

Fig. 13 is a graph showing an example of a temperature distribution at the time of reflow of the assembly program shown in Fig. 2 .

FIG. 14 is a cross-sectional view and a perspective view showing a first modification of the NCF supply method according to the embodiment.

Fig. 15 is a perspective view showing a second modification of the NCF supply method according to the embodiment.

Fig. 16 is a perspective view showing a third modification of the NCF supply method according to the embodiment.

FIG. 17 is a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the embodiment.

FIG. 18 is a cross-sectional view showing an NCF supply state of the assembly of the semiconductor device shown in FIG. 17.

19 is a cross-sectional view showing a flip-chip connection state of the assembly of the semiconductor device shown in FIG. 17.

Fig. 20 is a cross-sectional view showing an enlarged portion of a structure before and after connection in the flip chip connection shown in Fig. 19;

In the following embodiments, the description of the same or similar parts will not be repeated in principle unless otherwise specified.

Further, in the following embodiments, a part or an embodiment divided into plural numbers will be described as necessary for convenience, but Unless otherwise specified, these are not mutually exclusive, and one of them is a modification of some or all of the other, detailed, supplementary, and the like.

In the following embodiments, the number of elements (including the number, the numerical value, the quantity, the range, and the like) is not limited to the specific number except when it is specifically indicated and the principle is clearly limited to a specific number. The number can also be a specific number or more.

Further, in the following embodiments, the constituent elements (including the element steps and the like) are not necessarily essential unless otherwise specified and essential in principle.

In addition, in the following embodiments, when the components are formed, such as "made by A", "made by A", "having A", and "including A", except when only the elements are specifically indicated, Of course, the other elements are not excluded. Similarly, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are included, the shape is substantially similar or similar to the shape, unless otherwise specified. The same is true for the above values and ranges.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the entire drawings for explaining the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. In addition, in order to easily understand the drawing, even a plan view may be attached with a hatching.

(embodiment)

Fig. 1 is a cross-sectional view showing an example of a structure of a semiconductor device according to an embodiment; Surface map.

The semiconductor device of the present embodiment shown in FIG. 1 is a semiconductor package in which a logic chip 2 and a memory chip 3 are mounted on an interposer electrically connecting a main substrate and a semiconductor wafer, and the logic chip 2 is interposed on the interposer. The memory chips 3 are respectively connected by flip chip bonding. Further, the memory chip 3 may be mounted in one stage (one piece) or stacked in multiple stages. The configuration shown in FIG. 1 is a case where the memory wafer 3 is stacked in three stages.

In the present embodiment, a case where the external connection terminal of the semiconductor device is provided on a plurality of ball electrodes provided on the lower surface of the main substrate will be described as an example of the semiconductor device. Therefore, the semiconductor device described in the present embodiment is also a BGA (Ball Grid Array) type semiconductor package (hereinafter abbreviated as BGA5).

Further, the BGA 5 of the present embodiment is provided with a heat release plate called a lid 7 on the logic chip 2 and the memory chip 3 so as to cover the semiconductor wafers.

Further, the interposer is a wafer supporting substrate between the semiconductor wafer and the main substrate (first substrate) having different terminal pitches, and the interposer of the present embodiment is a substrate made of Si. Hereinafter, in the present embodiment, the wafer supporting substrate is referred to as a Si interposer (second substrate) 1.

Here, since the wiring connecting the logic chip 2 and the memory chip 3 is completed in the Si interposer 1, the Si interposer 1 also has a function of reducing the number of terminals connected to the main substrate and increasing the terminal pitch.

Also, in BGA5, it is set on logic chip 2 and The plurality of protruding electrodes of the memory wafer 3 are disposed at a fine pitch (narrow pitch). Therefore, each of the plurality of bump electrodes is a Cu pillar (columnar electrode) 4 made of an alloy containing Cu (copper) as a main component in accordance with the fine pitch. The Cu pillar 4 is, for example, also referred to as a microbump.

The detailed description of the detailed structure of the BGA 5 shown in FIG. 1 includes a printed wiring board (first substrate) 9 having a main substrate and a plurality of solder balls 12 mounted on the upper surface 9a of the printed wiring board 9. The Si interposer (wafer support substrate, second substrate) 1 of the substrate and the logic wafer 2 and the memory chip 3 which are respectively bonded to the upper surface 1a of the Si interposer 1 are respectively covered.

Therefore, the upper surface 9a of the printed wiring board 9 and the lower surface 1b of the Si interposer 1 are opposed to each other with a plurality of solder balls 12 interposed therebetween, and the upper surface 1a of the Si interposer 1 and the main surface 2a of the logic wafer 2 and the memory wafer are The main faces 3a of the three faces are arranged opposite each other with a plurality of Cu pillars 4 interposed therebetween.

As described above, the logic chip 2 is flip-chip bonded to the upper surface 1a of the Si interposer 1 via a plurality of Cu pillars 4 provided at fine pitches, and the memory wafer 3 is also provided via fine pitches. A plurality of Cu pillars 4 are flip-chip bonded to the upper surface 1a of the Si interposer 1.

Further, the memory wafer 3 is stacked in three stages, and is electrically connected to a plurality of Cu pillars 4 via the through-vias 3c. In other words, the memory chip 3 of the second stage is stacked on the back surface 3b of the memory chip 3 of the first stage, and the memory chip 3 of the third stage is stacked on the back surface 3b of the memory chip 3 of the second stage.

Further, the surface layer on the upper surface 1a side of the Si interposer 1 is shaped The wiring layer 1d is formed, and a plurality of through via holes 1c are provided inside from the upper surface 1a side to the lower surface 1b side. Thereby, each of the plurality of Cu pillars 4 and the plurality of solder balls 12 provided on the lower surface 1b side are electrically connected to each other via the wiring formed in the wiring layer 1d and the through via 1c. Similarly, the plurality of Cu pillars 4 of the memory wafer 3 are also electrically connected to each of the plurality of solder balls 12 provided on the lower surface 1b side via the wiring formed in the wiring layer 1d and the through via 1c.

Further, the printed wiring board 9 includes a plurality of internal wirings 9d and a plurality of via holes 9c, and a plurality of BGA balls 8 are provided on the lower surface 9b. These BGA balls 8 are external connection terminals or external electrode terminals of the BGA 5.

As described above, the electrode pad 2c of the main surface 2a of the logic chip 2 is electrically connected to the through via 1c of the Si pillar 4, the Si interposer 1, the solder ball 12, the internal wiring 9d of the printed wiring board 9, and the via 9c. The BGA ball 8 on the lower surface 9b side of the printed wiring board 9 is printed. On the other hand, the through via 3c of the memory chip 3 is similarly electrically connected to the through via 1c of the Si pillar 4, the Si interposer 1, the solder ball 12, the internal wiring 9d of the printed wiring board 9, and the via 9c. The BGA ball 8 on the lower surface 9b side of the printed wiring board 9 is printed.

Further, an underfill (resin) 6a is filled between the printed wiring board 9 and the Si interposer 1. The underfill 6a of the Si interposer 1 is placed on the printed wiring substrate 9 by a plurality of solder balls 12 to be flip-chip bonded to the Si interposer 1 and then implanted.

On the other hand, each of the logic chip 2 and the memory chip 3 The underfill (resin) 6b is an NCF (Insulating Adhesive) 10, and the NCF 10 is placed on the upper surface 1a of the Si interposer 1 before the flip-chip connection of the logic wafer 2 or the memory wafer 3, and is disposed from the upper surface of the NCF 10. The logic chip 2 and the memory chip 3 are mounted. That is, the NCF 10 of the underfill 6b of each of the logic chip 2 and the memory chip 3 is disposed on the Si interposer 1 by a preload (also referred to as a first coating) method.

However, the gap between the memory chip 3 of the first stage of the memory chip 3 stacked in three stages and the memory chip 3 of the second stage, and the memory chip 3 and the third stage of the second stage The gap between the memory chips 3 is an underfill rubber 6a in which a resin injected into each of the gaps is placed. These underfills 6a are gaps which are injected between the wafers after lamination of all the memory chips 3.

Further, a cover 7 is provided as a heat release plate in the BGA 5. The cover 7 is a memory chip 3 and a Si interposer 1 which are provided so as to cover the logic chips 2 and 3. The cover 7 is a top portion 7b having a rim portion 7a and a position higher than the edge portion 7a, and the edge portion 7a is joined to the peripheral edge portion of the upper surface 9a of the printed wiring board 9 by the adhesive member 11. Thereby, the logic chip 2, the memory chip 3, and the Si interposer 1 are covered by the cover 7, and are protected.

Further, the top portion 7b of the cover 7 is bonded to the back surface 2b of the logic chip 2 and the back surface 3b of the third stage memory chip 3 via the adhesive 11, and the heat emitted from the logic chip 2 or the memory chip 3 is transferred to The cover 7 is then placed outside. That is, the cover 7 also has the function of a heat release plate.

Therefore, if heat dissipation is considered, the adhesive 11 is used. An electric adhesive (conductive resin) is preferable, for example, a silver paste or an aluminum paste.

Further, the memory chip 3 mounted on the BGA 5 is, for example, a DRAM (Dynamic Random Access Memory) controlled by the logic chip 2, but is not limited to the DRAM.

Next, the assembly of the semiconductor device (BGA 5) of the present embodiment will be described.

2 is a flow chart showing an example of an assembly procedure of the semiconductor device shown in FIG. 1, and FIGS. 3 to 7 are cross-sectional views showing a structure of a part of the assembly program shown in FIG. 2, respectively.

First, the "flux supply" shown in step S1 of Fig. 2 is performed. In the flux supply of the step S1, as shown in FIG. 3, the flux 15 is supplied to the plurality of solder balls 12 provided on the lower surface 1b of the Si interposer 1 by the flux transfer plate 16.

After the flux is supplied, the "Si interposer mounting" shown in step S2 of Fig. 2 is performed. Here, as shown in step S2 of FIG. 3, the electrodes 13 are applied to the respective electrodes of the upper surface 9a of the printed wiring board (first substrate) 9, and the solder 13 is provided on the Si interposer ( The plurality of solder balls 12 on the lower surface 1b of the second substrate) 1 are in contact with each other, and the Si interposer 1 is mounted. That is, the Si interposer 1 is mounted on the printed wiring board 9.

After the Si interposer is mounted, "reflow" shown in step S3 of Fig. 2 is performed. In other words, the assembly formed of the printed wiring board 9 and the Si interposer 1 is placed in a reflow furnace and heated, and the solder balls 12 and the solder 13 are melted to form a new plurality of solder balls 12. At this time, in the newly formed complex A flux 15 is formed on the surface of each of the plurality of solder balls 12.

After the reflow, "flux cleaning" shown in step S4 of Fig. 2 is performed. That is, the flux 15 formed on the surface of each of the plurality of solder balls 12 is removed. At this time, the flux is washed with a solvent or water (see FIG. 4).

After the flux is washed, "baking" shown in step S5 of Fig. 2 is performed. The baking in step S5 is a heat treatment for drying the printed wiring substrate 9. Specifically, the dehumidifying baking of the printed wiring board 9 is performed for the purpose of reducing the voids in the underfill (the underfill 6a shown in FIG. 5 described later) due to the moisture contained in the printed wiring board 9. grilled. The conditions for dehumidifying baking at this time depend on the material or size of the printed wiring board 9 and the wiring layout. For example, the temperature is 120 ° C to 180 ° C, and the time is 0.5 hours to 6 hours.

Further, if the temperature is too low, the baking effect cannot be obtained, and if it is too high, the substrate is deteriorated. Therefore, it is preferable that the temperature is about 150 ° C and the time is about 4.5 hours in the case of a substrate having a thickness of 0.5 μm.

Further, the environment of the baking furnace is an inert gas such as a flowing atmosphere or a nitrogen gas, and the oxygen concentration in the baking furnace is preferably 10% or less.

After baking, "O ₂ plasma cleaning" shown in step S6 of Fig. 2 is performed. Here, the contamination of the upper surface 9a of the printed wiring board 9 is removed by plasma cleaning using oxygen (O ₂ ), whereby the underfill resin (the underfill 6a shown in FIG. 5) which will be described later can be used. The adhesion is improved.

After the O ₂ plasma is washed, "underfill resin coating + cure bake" shown in step S7 of Fig. 2 is performed. As shown in step S7 of Fig. 5, an underfill (resin) 6a is injected (coated) in a gap between the printed wiring substrate 9 and the Si interposer 1. At this time, the underfill rubber 6a is also injected to the side of the Si interposer 1 to the extent that the underfill 6a is climbed.

In addition, since the upper surface 9a of the printed wiring board 9 is cleaned by the plasma before the application of the underfill rubber 6a as described above, the adhesion between the printed wiring board 9 and the underfill rubber 6a is good.

After the underfill resin coating + curing baking, "Ar plasma cleaning" shown in step S8 of Fig. 2 is performed. That is, the plasma washes the upper surface 1a of the Si interposer 1. Specifically, the Si interposer 1 is plasma-washed for the purpose of improving the adhesion of the Si interposer 1 to the NCF 10 to be described later (prevention of the separation of the Si interposer 1 and the NCF 10) and the reduction of the voids in the NCF. Net processing. At this time, the gas generating the plasma may be argon (Ar) or oxygen (O ₂ ) or a mixed gas thereof.

For example, when Ar gas is used as the gas for generating plasma, the Ar plasma is washed so that Ar atoms collide with the surface of the Si interposer 1, and impurities such as organic substances can be removed. Further, by causing the Ar atoms to collide with the surface of the Si interposer 1, fine irregularities are formed on the surface of the Si interposer 1, whereby the adhesion to the NCF 10 to be described later can be improved.

After the Ar plasma is washed, "NCF is attached to the Si interposer" shown in step S9 of Fig. 2 is performed. That is, the NCF (Insulating Adhesive) 10 is placed on the upper surface 1a of the Si interposer 1.

Here, NCF10 is a lightly peeled film (material: PET) The three-layer structure sandwiched between the heavy release film (material: PET) or the two-layer structure in which the heavy release film is attached to one side of the NCF 10 is wound on the reel in a state of three or two layers. Moreover, the light release film of the three-layer structure is designed. It is easy to peel from the NCF body by manufacturing a specific gravity peeling film.

Next, a procedure for supplying the NCF 10 (see step S9 of FIG. 5) to the Si interposer 1 after dehumidifying baking (step S5 in FIG. 2) and plasma cleaning processing (step S8 in FIG. 2) is described.

First, the heavy release film and the NCF 10 are cut into a predetermined size, and the NCF 10 is placed on the upper surface 1a of the Si interposer 1 in a direction in contact with the Si interposer 1 (when the three-layer structure is peeled off, the light release film is peeled off) wear). When the NCF 10 is worn through the punching machine, it is also possible to prevent the burrs of the NCF 10 from being punctured while the NCF 10 is being heated. When the temperature of the NCF 10 at this time is too low, the burrs are prevented from being ineffective. If the temperature of the NCF 10 is too high, the thermal hardening of the NCF 10 is excessively advanced. Therefore, the temperature is preferably 40 to 80 ° C.

Next, the adhesion work of the NCF 10 to the Si interposer 1 is carried out. The operation is performed by applying a vacuum laminating apparatus to a pressure of 0.05 MPa to 0.5 MPa on a side of the heavy release film while heating to 60 ° C to 100 ° C under a reduced pressure of 0.05 kPa to 0.5 kPa. ~20 seconds, sticking to it.

Finally, the heavy release film was removed to form a state in which only the NCF 10 was adhered to the upper surface 1a of the Si interposer 1.

After the NCF is attached to the Si interposer, "NCF prebaking" shown in step S10 of Fig. 2 is performed. That is, after the NCF is attached, and halfway Before the conductor wafer is mounted, the NCF 10 is baked (prebaking: heat treatment).

Specifically, for the purpose of removing excess solvent and moisture contained in the NCF which is a cause of pores in the NCF, the Si interposer 1 of the NCF 10 is preliminarily attached to the baking furnace (pre-baking the NCF 10). The temperature of the heat-treated Si interposer 1 is 60 ° C to 100 ° C, and the time is about 0.5 to 3 hours. Preferably, the temperature is about 80 ° C and the time is about 1.5 hours.

This is a temperature lower than the temperature (for example, 150 ° C) at the time of baking the printed wiring substrate 9 (baking in step S5 of FIG. 2 ), and the time is also longer than the baking process of the printed wiring substrate 9 (for example, 4.5). Hours) Short time.

If the temperature is too high or the time is too long, the NCF 10 is hardened. On the other hand, if the temperature is too low or the time is too short, the curing is insufficient (the solvent and moisture are not sufficiently removed). .

Therefore, it is important that the pre-baking of the NCF 10 is carried out at an appropriate temperature and time.

Further, in the environment of the pre-baked baking oven of the NCF 10, an inert gas such as air or nitrogen gas may be used. When an inert gas is used, it is preferable that the oxygen concentration in the furnace is 10% or less.

After the NCF is pre-baked, the "logic chip/memory chip mounting (temporary connection)" shown in step S11 of Fig. 2 is performed. That is, as shown in S11 of FIG. 6, the upper surface 1a of the Si interposer 1 passes through the NCF 10 Each semiconductor wafer (logic wafer 2 and memory chip 3) is mounted (temporarily connected).

Here, FIG. 8 is a plan view showing an example of a method of identifying an alignment mark at the time of wafer mounting in the assembly program shown in FIG. 2 , and FIG. 9 is a view showing an example of a method of mounting the wafer in the assembly process shown in FIG. 2 . FIG. 10 is a perspective view showing an example of a mounting method at the time of wafer mounting of the assembly program shown in FIG. 2 . In addition, FIG. 11 is a cross-sectional view showing an example of a state in which the wafer is loaded during wafer mounting of the assembly program shown in FIG. 2, and FIG. 12 is a view showing the connection before and after the connection of the flip-chip connection of the assembly program shown in FIG. An enlarged partial cross-sectional view of an example of a structure.

In the wafer mounting process, specifically, the semiconductor wafer (logic wafer 2, memory chip 3) is mounted on the Si interposer 1 to which the NCF is adhered by using the flip chip bonder 21 as shown in FIG. That is, the Si interposer 1 to which the NCF is adhered is fixed by means of adsorption or the like on the stage 20 of the flip chip bonder 21. In addition, when the temperature of the Si interposer 1 is fixed to the stage 20 of the flip chip bonder 21, if the temperature of the Si interposer 1 is too high, the time required for the mounting of the NCF 10 to the semiconductor wafer becomes unsatisfactory. When the viscosity of the NCF 10 is high, the mounting of the semiconductor wafer is difficult, and the influence of the occurrence of voids when the semiconductor wafer is mounted is adversely affected.

For this reason, the temperature at which the heat hardening reaction of the NCF 10 is fast is generally about 100 ° C. Therefore, the temperature of the stage 20 of the flip chip bonder 21 can be set so that the temperature of the Si interposer 1 can be formed at 60 ° C to 100 ° C.

In the wafer mounting project, first, as shown in FIG. The logic chip 2 (which is also the same for the memory chip 3) accommodated in the wafer tray 17 by the chuck (wafer adsorption tool) 18 is sucked and picked up, and the logic chip 2 to be picked up is then picked up by the flip chip bonder. The reversing mechanism of 21 reverses the front and back of the logic chip 2 in a state in which the chuck 18 is adsorbed. Then, as shown in FIG. 10, the back surface 2b of the logic wafer 2 is adsorbed and held by the bonding tool 19 of the flip chip bonder 21, and in this state, the logic wafer 2 is transferred to the Si medium held by the stage 20. On layer 1.

Then, the alignment mark (mark) 1e of the Si interposer 1 shown in FIG. 8 is recognized from above by a camera (not shown), and the alignment of the logic chip 2 is recognized from below by a camera (not shown). Marking, positioning of the logic chip 2 and the Si interposer 1 is performed based on the identification result of each.

Further, as shown in FIG. 8, the alignment mark 1e for identifying the position of the Si interposer 1 is formed on the upper surface 1a of the Si interposer 1 at a position outside the NCF 10 disposed in the wafer mounting region 1f. Since the alignment mark 1e is formed at the outer position of the NCF 10 as described above, the alignment mark 1e of the Si interposer 1 can be recognized immediately after the NCF 10 is attached and immediately before the logic wafer 2 is mounted.

Thereby, the alignment of the logic chip 2 and the Si interposer 1 can be performed with high precision.

As described above, in the state where the logic wafer 2 is sucked and held by the bonding tool 19 of the flip chip bonder 21, and the logic wafer 2 and the Si interposer 1 are aligned, the logic crystal is mounted on the Si interposer 1. Slice 2.

At this time, when the bonding tool 19 of the flip chip bonder 21 detects the contact of the logic chip 2 with the Si interposer 1 after the NCF 10 is adhered, as shown in FIG. 12, a load is applied to the logic chip 2, and the logic chip 2 is placed. Pushed into the Si interposer 1 side. Then, the columnar Cu pillars 4 formed on the wafer side are brought into contact with the terminal portion (electrode) 1h (the terminal portion (electrode) 1h is an electrode terminal on the Si interposer 1 side, and is connected to the through via 1c). The solder 13 formed at the tip end of the columnar Cu pillar 4 on the wafer side is deformed (see the mounting of FIG. 12).

Further, since the shape after the deformation is connected and the shape of the connection portion after the reflow processing, since the distance between the logic wafer 2 and the gap portion of the Si interposer 1 is almost the same, even if the logic wafer 2 is slightly inclined to the Si interposer 1 Further, the logic chip 2 can be mounted, and all of the columnar Cu pillars 4 can be brought into full contact with the electrode terminal (terminal portion 1h) of the Si interposer 1.

Specifically, the load applied to the logic wafer 2, the temperature, and the application time are adjusted to deform the solder 13 at the tip end of the columnar Cu pillar 4, and the height thereof is 5 μm to 15 μm lower than that before the deformation.

The temperature of the electrode terminal (terminal portion 1h) at this time is preferably as high as possible in the range of the temperature below the solder melting temperature (melting temperature of the solder 13). That is, after the logic wafer 2 is aligned with the Si interposer 1, as shown in FIG. 12, the temperature is lower than the melting temperature of the solder 13 applied to the tip end of each of the plurality of Cu pillars 4, and Heat as high as possible and heat separately. Pressurize to deform, Thereby, the plurality of terminal portions 1h are respectively caught in the respective solders 13. That is, the Cu pillar 4 is pushed into the terminal portion 1h at a temperature to the extent that the solder 13 is insolubilized.

Specifically, in the tin-silver-based lead-free solder, since the melting point of the solder is about 230 ° C, the temperature of the connection portion during the mounting operation is preferably about 200 ° C to 220 ° C. The temperature of the bonding tool 19 of the flip chip bonder 21 is likely to cause deterioration of the takt time as it rises and falls, and therefore it is preferable to keep it constant.

In addition, the structure of the terminal portion (electrode) 1h connected to the through-via 1c of the Si interposer 1 is such that, as shown in the pre-installation of FIG. 12, a metal in which the solder 13 is solid-phase-diffused is formed on the surface of the Ni1g plating. For example, in the case of Au14 plating, the connection between the Cu pillar 4 on the wafer side and the terminal portion (electrode) 1h on the Si interposer 1 side is performed by solder 13 and Au14 plating.

Above, the logic chip 2 is temporarily connected to the Si interposer 1. In the same manner, the memory wafer 3 is also temporarily connected. However, the stacking of the three segments of the memory chip 3 is performed in advance, and the gap portions between the first segment and the second segment and between the second segment and the third segment are respectively post-loaded (post-injection). The underfill 6b is injected.

Further, in the wafer mounting process of the present embodiment, as shown in FIG. 11, the logic wafer 2 is sucked and held by the adsorption surface 19a of the bonding tool (head) 19 of the flip chip bonder 21, as shown in FIG. The logic chip 2 is mounted on the upper surface 1a of the Si interposer 1.

At this time, as shown in FIG. 11, the adsorption of the bonding tool 19 The plane size of the face 19a is smaller than the plane size of the back surface 2b of the logic chip 2. However, the plane size of the adsorption surface 19a of the bonding tool 19 may be the same as the plane size of the back surface 2b of the logic wafer 2.

After the logic chip/memory chip is mounted, "reflow (official connection)" shown in step S12 (step S12 of Fig. 6) of Fig. 2 is performed. Here, the Si interposer 1 and the NCF 10 on which the logic chip 2 and the memory chip 3 are mounted are heated by reflow, and the plurality of terminal portions 1h of the Si interposer 1 are electrically connected via a plurality of Cu pillars 4 and solder 13 Each of the plurality of electrode pads 2c (see FIG. 1) of the logic chip 2 is used.

In this case, as shown in FIG. 12, the NCF 10 is placed in the upper surface 1a of the Si interposer 1 in advance by the pre-installation method. Therefore, in a state where the NCF 10 is placed around each of the plurality of Cu pillars 4, The Cu pillars 4 are electrically connected (formally connected) to each of the plurality of terminal portions 1h and each of the plurality of electrode pads 2c.

Specifically, in the reflow furnace of the conveyor type, the Si interposer 1 of the logic chip 2 and the memory chip 3 and the printed wiring board 9 supporting the Si interposer 1 are mounted by wafer mounting. In addition, each of the logic chip 2 and the memory chip 3 is a columnar Cu pillar 4 on the surface of each wafer and a terminal portion 1h on the Si interposer 1 side. The connection force by the NCF 10 and the columnar Cu are obtained. The state in which the pillar 4 is connected to the terminal portion 1h of the Si interposer 1 is maintained.

Thereby, soldering is performed on the terminal portion 1h of the Si interposer 1, and the formation of the alloy layer is promoted, and the logic wafer is more physically connected. 2 (the same applies to the memory chip 3) and the Si interposer 1.

Here, FIG. 13 is a graph showing an example of a temperature distribution at the time of reflow of the assembly program shown in FIG. 2 .

As shown in Fig. 13, the temperature distribution is preferably a temperature distribution in which the Si interposer 1 on which the semiconductor wafer is mounted enters the reflow furnace and the temperature reaches the peak temperature as soon as possible after the temperature rises. This is because the solder is melted at a faster timing, so that the solder can be melted at a time when the curing rate of the NCF 10 is as low as possible, and the shape of the solder of the connection portion between the semiconductor wafer and the Si interposer 1 can be expected. The smoothness is maintained by the surface tension of the molten solder. Further, in Fig. 13, the line portion A indicates the distribution of the portion which first enters the reflow furnace, and on the other hand, the line portion B is the distribution of the portion which enters the reflow furnace.

Since the shape of the connecting portion is a smooth shape, the concentration of stress such as general thermal stress can be alleviated, and thus the reliability of the connecting portion can be expected to be improved. Specifically, it is preferable that the temperature rise starts and the peak temperature reaches within 100 seconds. The peak temperature is required to be equal to or higher than the solder melting temperature. However, if it is too high, an excessive heat load is applied, so it is set in the range of 230 ° C to 260 ° C. The reflow method can be carried out in a general hot air method or an infrared method in the assembly of the semiconductor. An inert gas such as a nitrogen gas can also be used.

An example of the use of an actual reflow project is described. When the Si interposer 1 on which the semiconductor wafer is mounted is placed in a reflow furnace, the Si interposer 1 is disposed in a direction in which the predetermined direction of the Si interposer 1 coincides with the traveling direction of the conveyor. At this time, the Si interposer 1 may be disposed adjacent to each other. Moreover, the Si interposer 1 is capable of being transported immediately before the Si interposer 1 is transported. Order input. The conveyor speed of the reflow furnace is in accordance with the specifications of the furnace. For example, a reflow furnace capable of achieving the above temperature distribution while being conveyed at a speed of 1 to 2 m/min is a general reflow furnace. In this case, the number of inputs to the reflow furnace can be 1 to 3 times per minute. When calculating the tact time of a specific reflow process, 30 semiconductor devices can be assembled from one Si interposer 1, and when two pieces are simultaneously input, the number of times of input is 2 times/min, and the tact time of reflow is 0.5 second/IC. .

After the reflow (formal connection), "NCF curing baking" shown in step S13 (step S13 of Fig. 6) of Fig. 2 is performed. Here, the printed wiring board 9 having the Si interposer 1 on which the semiconductor wafer is mounted, which has been subjected to reflow, is housed in a metal case or the like, and is heat-treated in a baking oven to cure the NCF 10 by curing.

By curing by baking, the hardening reaction rate of the NCF 10 is 95% or more. The curing conditions are different according to NCF10, for example, the temperature is 150 ° C ~ 200 ° C, preferably 180 ° C, the time is 20 ~ 60 points, preferably 20 minutes (the actual temperature of the sample forms the aforementioned temperature time). Further, the environment of the baking oven at the time of curing baking is an inert gas which can also flow an atmosphere or a nitrogen gas.

After the NCF is cured and baked, "cover adhesive coating + capping" shown in step S14 (step S14 of Fig. 6) of Fig. 2 is performed.

Here, as shown in step S14 of FIG. 6, the edge portion 7a of the cover 7 and the printed wiring substrate 9 are connected by the adhesive 11, and the back surface 2b and the cover 7 of the logic wafer 2 are connected by the adhesive 11 respectively. Top 7b, and the back 3b of the memory chip 3 of the third stage and the top of the cover 7 7b.

After the cover is applied and the cover is attached, the "cured baking of the cover adhesive" shown in step S15 (step S15 of Fig. 7) of Fig. 2 is performed. Here, the adhesive 11 of the lid 7 is heated to perform a baking treatment.

After the curing of the cover adhesive is baked, "BGA ball mounting + reflow + flux cleaning" shown in step S16 (step S16 of Fig. 7) of Fig. 2 is performed. Here, as shown in step S16 of FIG. 7, a plurality of BGA balls 8 are attached by reflow on the lower surface 9b of the printed wiring board 9, and then the flux 15 formed on the surface of each BGA ball 8 is washed (flux) Washed) removed.

Thereby, the assembly of the BGA 5 shown in Fig. 1 of the present embodiment is completed.

Next, a mechanism for flip chip connection of the assembly of the semiconductor device of the present embodiment will be described.

The columnar bump electrodes (Cu pillars 4) formed on the surface of each semiconductor wafer are formed by sequentially plating UBM (Under Bump Metal), Cu, and solder on an aluminum (Al) pad of a semiconductor wafer. A Ni layer may also be formed between Cu and solder. Since the reflow treatment is performed after the solder plating, the solder 13 at the tip end of the columnar bump electrode has a circular shape.

Further, the solder is softer than other metals, and particularly in the temperature range close to the melting point of the solder when the semiconductor wafer is mounted on the Si interposer 1, the hardness of the solder is lowered and easily deformed. Therefore, once the solder 13 at the front end of the columnar bump electrode is brought into contact with the end of the Si interposer 1 In the sub-portion 1h, first, the solder 13 at the tip end of the columnar bump electrode is deformed. At the same time as this deformation, solid phase diffusion occurs between the solder 13 at the tip end of the columnar bump electrode (Cu pillar 4) and the terminal portion 1h of the Si interposer 1, and the connection for fixing the semiconductor wafer to the Si interposer 1 is obtained. force.

Further, by the heat hardening reaction of the NCF 10, the force for fixing the semiconductor wafer to the Si interposer 1 can be obtained. The specific hardening reaction rate of the NCF 10 (here, the hardening reaction rate when the wafer is temporarily connected) is preferably 50% to 80%. If the hardening reaction rate is too low, the ability to fix the semiconductor wafer to the Si interposer 1 may be insufficient. On the other hand, if the hardening reaction rate is increased at the time of temporary connection, it is difficult to expect a change in the shape of the joint portion due to the surface tension of the solder in the reflow process of the second process. By setting the hardening reaction rate to 50% to 80%, it is possible to prevent the outflow of tin (Sn) or the like during the subsequent melting of the engineered solder. Moreover, the outflow of the resin can also be prevented.

Mounting of the wafer (temporary connection), in order to prevent the solder from melting, to promote the solid phase diffusion between the metals as much as possible, and to improve the thermal hardening reaction of the NCF 10, it is preferable to make the solder not melt as much as possible. The temperature is carried.

In addition, when the solid phase diffusion of the columnar bump electrode (Cu pillar 4) and the electrode terminal (terminal portion 1h) of the substrate and the fixing force obtained by thermally hardening the NCF 10 are weak, the adsorption from the stage 20 is When the workpiece is moved to the reflow process, the columnar bump electrode (Cu pillar 4) is separated from the terminal portion 1h of the Si interposer 1 by vibration or the like.

In this case, even if reflow is performed, it is difficult to electrically connect the half. Conductor wafer and Si interposer 1.

Further, since the temperature of the semiconductor wafer to be mounted is higher than the temperature of the Si interposer 1 by 100 ° C or more, if the material of the stage 20 on which the Si interposer 1 is adsorbed is heat conduction, the semiconductor wafer and the Si interposer 1 are heated. It takes time for the connection portion and the NCF 10 to progress the solid phase diffusion or increase the hardening rate of the NCF 10 . Therefore, it is preferable to use a ceramic material or a glass material having a relatively low thermal conductivity in the stage 20 for adsorption of the flip chip bonder 21.

According to the method of manufacturing a semiconductor device of the present embodiment, the following effects can be obtained.

That is, before the NCF 10 is attached to the Si interposer 1, the surface of the Si interposer 1 is washed by plasma to remove impurities or the like adhering to the surface (surface 1a) of the Si interposer 1. The contamination of the Si interposer 1 occurs, for example, in a baking process or the like. In other words, when the organic material such as the substrate or the resin is heat-treated, various chemical substances are released and adhered to the assembled tool or component, and as a result, the quality of the product (semiconductor device) is lowered, and the reliability is also improved. reduce.

Then, as in the present embodiment, before the NCF 10 is attached to the Si interposer 1, the surface of the Si interposer 1 is washed by plasma, and impurities or the like adhering to the surface of the Si interposer 1 can be removed, whereby Si can be removed. The adhesion of the surface of the interposer 1 to the NCF 10 is improved.

As a result, the Si interposer 1 and the NCF 10 become difficult to peel off, and the quality or reliability of the BGA 5 can be improved.

And mounting the semiconductor wafer on the Si interposer 1 At this time, it is possible that the NCF 10 is pushed out from the lower surface of the semiconductor wafer, climbs up the side surface of the semiconductor wafer, and the NCF 10 is attached to the bonding tool 19 that adsorbs and holds the semiconductor wafer. For this reason, in order to prevent the adhesion of the NCF 10 to the bonding tool 19 with respect to the bonding tool 19 for holding, mounting, heating, and load-applying the semiconductor wafer, as shown in FIG. 11, the plane size of the adsorption surface 19a of the bonding tool 19 is formed into a semiconductor wafer. The planes are the same size or slightly smaller than the planar size of the semiconductor wafer. For example, the plane size of the adsorption face 19a of the bonding tool 19 is formed to be about 0.2 mm on each side of the wafer smaller than the planar size of the semiconductor wafer.

That is, when the semiconductor wafer is mounted, the amount of the NCF 10 that is pushed out from the lower surface of the semiconductor wafer to the side surface depends on the planar size of the semiconductor wafer and the thickness of the NCF 10, and if the amount of the NCF 10 is pushed out, the NCF 10 is likely to adhere to the mounted semiconductor wafer. Bonding tool 19. Further, when the thickness of the semiconductor wafer is thick, the NCF 10 is less likely to adhere to the bonding tool 19, and conversely, if the thickness is thin, adhesion is likely to occur.

Therefore, in the present embodiment, as shown in Fig. 11, the plane size of the suction surface 19a of the bonding tool 19 is smaller than the plane size of the back surface 2b of the logic chip 2, or the same size, thereby being mounted on the wafer. At this time, even if the NCF 10 is pushed out from the lower surface of the logic chip 2 and climbs up to the side surface of the semiconductor wafer, the NCF 10 can be prevented from adhering to the adsorption surface 19a.

As a result, it is possible to prevent the adsorption surface 19a of the bonding tool 19 from being contaminated by the NCF 10 and the contamination of the adsorption surface 19a from adhering to the semiconductor wafer. Thereby, the quality or reliability of the semiconductor device (BGA5) can be improved.

Further, since the semiconductor device of the present embodiment is assembled by reflowing the solder 13 formed on the tip end of the columnar Cu pillar 4 formed on the surface of the wafer, the semiconductor wafer and the Si interposer 1 are electrically joined. The NCF method of heating, soldering, and cooling the semiconductor wafer and the substrate in sequence is also performed, and the connection portion can be uniformly heated. Therefore, the uniformity of the completion of the connection between the semiconductor wafer and the Si interposer 1 in the same wafer can be improved, and high connection quality can be obtained in the semiconductor device (BGA5).

In particular, the four corners of the semiconductor wafer are likely to be exothermic, and the completion of the connection portion of the solder is likely to vary depending on the location of the solder in the same wafer. However, since the connection portion can be uniformly heated in the present embodiment, uniformity can be obtained to obtain the semiconductor. High connection quality of the device (BGA5).

Next, the effect of the production efficiency of the assembly of the semiconductor device of the present embodiment will be described.

The technique reviewed by the inventors of the present invention is to perform heating and soldering at a temperature equal to or higher than the solder melting temperature when the semiconductor wafer is mounted on the substrate, and to cool the solder melting temperature or lower. For this reason, this part takes a long time. Specifically, it takes 7 seconds to 10 seconds/IC.

On the other hand, in the present embodiment, when the semiconductor wafer is mounted on the Si interposer 1, the heating, soldering, and cooling are not performed, and the solder melting is performed in the reflow furnace. Therefore, although the number of projects is increased, the mounting process is completed in a short time. Further, since the reflow furnace has a high processing capability, the method for manufacturing the semiconductor device of the present embodiment is smaller than that for the comparative review. Short beat time can increase production efficiency. NCF10 is generally developed as a quick-curing type resin, and the method of the present embodiment is realized at 220 ° C for about 3 seconds, and is sufficiently cured to a curing rate of about 70%.

Further, the mounting process of the wafer includes wafer pickup or mounting position recognition, and a cycle time of 5 seconds/IC can be expected. Since the tact time of the reflow process is expected to be 0.5 sec/IC as described above, the tact time of the flip chip bonding process for producing one semiconductor device in the method of the present embodiment is expected to be 5.5 seconds. In this way, a 30% reduction in the tact time can be achieved with respect to the method of conducting the comparative review.

Moreover, since the manufacturing method of the semiconductor device of the present embodiment can improve the production efficiency as described above, it is possible to reduce the manufacturing cost.

Further, since the semiconductor device of the present embodiment is assembled with the NCF 10 first, the connection portion of the flip chip connection is covered with the resin (NCF 10) from the initial stage. Thereby, it is possible to reduce the thermal stress applied to the connecting portion. As a result, cracks can be formed in the connection portion, and the connection reliability of the semiconductor device (BGA 5) can be improved.

(Modification)

FIG. 14 is a cross-sectional view and a perspective view showing a first modification of the NCF supply method according to the embodiment, FIG. 15 is a perspective view showing a second modification of the NCF supply method according to the embodiment, and FIG. 16 is a perspective view showing the NCF supply method according to the embodiment. A perspective view of a third modification.

The first to third modifications are illustrative of the base of the NCF 10 The method of forming the board.

The first modification shown in FIG. 14 is a method of supplying the NCF 10 on the film to the wafer (wafer, substrate) 22 side.

First, proceed with NCF preparation. Here, it is prepared to attach the NCF 10 to the base film 10a, and further attach the NCF 10 of the cover film 10b thereto. Next, the cover film 10b is peeled off from the NCF 10 by peeling off the cover film. Then, the NCF stack is performed on the wafer. For example, during the dicing process, the NCF 10 cut into the same size as the wafer 22 (NCF cut) is laminated on the circuit surface of the wafer 22.

The thickness or the attaching condition of the NCF 10 at this time is the same as that described in the embodiment. Further, in the wafer dicing process, the NCF 10 and the semiconductor wafer are simultaneously cut and diced. Then, the semiconductor wafer with the NCF is picked up from the dicing sheet and mounted on the Si interposer or the printed wiring board.

According to the NCF forming method shown in FIG. 14, the number of semiconductor wafers that can be supplied to the NCF 10 in one lamination operation can be increased by performing NCF bonding on the wafer level.

Next, a second modification shown in Fig. 15 will be described.

The second modification is a method of forming the NCF 10 by printing the liquid resin 23 on the plurality of take-out substrates 24 by the doctor blade 25 in a B-stage (B-Stage).

First, in the resin printing, the liquid resin 23 is printed by the doctor blade 25 on the plurality of take-out substrates 24 on which the mask 26 for printing is placed. Then, during baking, most of the ones placed on the platform 27 are taken. The substrate 24 is baked and B-staged. Thereby, a plurality of NCFs 10 are formed on a plurality of take-out substrates 24.

According to the NCF forming method shown in FIG. 15, the NCF 10 is formed by printing on a plurality of take-out substrates 24, and since the printing method has high production efficiency, the NCF 10 can be formed efficiently on a plurality of take-out substrates 24. Further, since the NCF 10 can be supplied in accordance with the design of the mask 26 for printing, the use efficiency of the material can be improved.

Next, a third modification shown in Fig. 16 will be described.

The third modification is a method of forming the NSF 10 by printing the paste resin 28 on the wafer 22 (which may be a wafer or a printed wiring substrate).

First, in the resin printing, the paste 26 and the doctor blade 25 for printing are used, and the paste resin 28 is printed on the wafer (or the printed wiring board) 22 before cutting. Then, during baking, the baking treatment of the wafer 22 is performed on the stage 27, and the paste resin 28 is B-staged. Thereby, the NCF 10 is formed on the wafer 22.

According to the NCF forming method shown in FIG. 16, the NCF 10 is formed by printing on the wafer 22, and since the printing method is highly efficient, the NCF 10 can be efficiently formed on the wafer 22.

Further, similarly to the above, since the NCF 10 can be supplied in accordance with the design of the mask 26 for printing, the use efficiency of the material can be improved.

17 is a cross-sectional view showing a structure of a semiconductor device according to a fourth modified example of the embodiment, and FIG. 18 is a view showing the semiconductor package shown in FIG. FIG. 19 is a cross-sectional view showing a state of flip chip connection in the assembly of the semiconductor device shown in FIG. 17, and FIG. 20 is a view showing a connection before the flip chip connection shown in FIG. An enlarged partial cross-sectional view of the connected structure.

The fourth modification shown in FIG. 17 is a BGA (semiconductor device) 32 in which a germanium wafer (semiconductor wafer) 30 is mounted on a printed wiring board 29 of a wafer supporting substrate by flip chip bonding, and printed wiring boards 29 and 矽The wafers 30 are filled with an NCF 10 that is configured by a pre-installation method.

Further, on the upper surface side of the printed wiring board 29, the tantalum wafer 30 is connected to the plurality of Cu pillars 4 of the columnar bump electrodes, and the lower side is the plural of the external connection terminals provided with the BGA 32. BGA Ball 8.

Next, explain the assembly of the BGA32.

In addition, the assembly of the BGA 32 is a case where a plurality of substrates 31 of the matrix substrate are taken out and assembled.

First, the surface of the plurality of taken-out substrates 31 shown in Fig. 18 is cleaned by plasma. The plasma washing here is the same as the Ar plasma washing shown in step S8 of Fig. 2 of the embodiment. That is, the plasma is washed in the subsequent process to arrange the surface of the substrate 31 of the NCF 10 to be taken out. Thereby, impurities or contamination of the surface (particularly the upper surface) of the plurality of taken-out substrates 31 can be removed.

After the plasma is washed, as shown in FIG. 18, the NCF 10 is placed on the wafer mounting portion on the upper surface of the plurality of taken-out substrates 31. In addition, related In the arrangement of the NCF 10, the NCF 10 is placed in the punching of the press and the mounting operation of the NCF 10 until the NCF 10 is placed in all of the wafer mounting portions of the plurality of taken-out substrates 31.

After the NCF is placed, the germanium wafer 30 is mounted from above via the NCF 10 as shown in FIG.

At this time, as shown in the mounting of FIG. 20, the Cu pillar 4 of the tantalum wafer 30 is aligned with the electrode 29a of the printed wiring board 29, and then the load is applied to the tantalum wafer 30, and the tantalum wafer 30 is pushed into the printing. The wiring board 29 side.

Then, the columnar Cu pillars 4 formed on the wafer side are brought into contact with the electrodes 29a on the side of the printed wiring board 29, and the front end of the columnar Cu pillars 4 formed on the wafer side are formed as shown in FIG. The solder 13 is deformed.

At this time, since the plating Au14 is formed on the surface of the electrode 29a, the solder 13 is caught by the electrode 29a, and the solder 13 is brought into contact with the plating Au14 on the surface of the electrode 29a.

Further, when the wafer mounting shown in FIG. 20 is performed, the solder 13 is heated at a temperature lower than the melting temperature of the solder 13 applied to the tip end of each of the plurality of Cu pillars 4, and the plurality of electrodes are heated. 29a is trapped in each of the solders 13 (destroying the solder 13).

In the operation of the wafer mounting of the plurality of substrates 31, the mounting operation is repeated on one of the plurality of extraction substrates 31, and the wafers are mounted on a predetermined portion (wafer mounting portion) of the plurality of substrates 31.

After the wafer is mounted, the solder 13 is melted while the plating Au14 is in contact with the solder 13, and the solder 13 is melted, and the solder 13 and the plating Au14 are electrically connected. That is, the Cu pillar 4 on the wafer side and the electrode 29a on the substrate side are electrically connected to complete the flip chip connection.

As described above, in the assembly of the BGA 32 in which the printed wiring board 29 is flip-chip bonded, the surface of the plurality of taken-out substrates 31 is washed by plasma before the NCF 10 is attached to the plurality of taken-out substrates 31 (printed wiring board 29). The impurities and the like adhering to the surface (upper surface) of the plurality of taken-out substrates 31 can be removed.

Thereby, the adhesion of the surface of the plurality of taken-out substrates 31 (printed wiring board 29) to the NCF 10 can be improved.

As a result, a plurality of the take-out substrates 31 (printed wiring boards 29) and the NCF 10 are hardly peeled off, and the quality or reliability of the BGA 32 can be improved.

In addition, other assembly methods or other effects of the BGA 32 are the same as those of the BGA 5 assembly method and effect of the embodiment, and thus the repeated description thereof will be omitted.

The invention developed by the inventors of the present invention has been described in detail above. The present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention.

For example, in the fourth modification, the case where the BGA 32 is assembled by using a plurality of extraction substrates (matrix substrates) 31 is described. However, a plurality of the removal substrates 31 may be used, and the small-sized substrate may be used in a small piece.

Further, in the above embodiment, the interposer (second substrate) is a Si interposer made of Si. However, the interposer may be, for example, a glass interposer mainly composed of a glass material or An organic intermediate layer containing organic materials as the main component.

The glass interposer has a glass material as a core material, and since the glass material has high insulation properties, it is possible to obtain an effect of reducing the attenuation even at a high frequency. Further, the glass interposer is cheaper than the Si interposer, and by using the glass interposer, the substrate cost can be reduced.

Moreover, the organic interposer can be, for example, a line/space of wiring of 5 μm/5 μm or less, and the wiring density can be improved as compared with the conventional printed wiring board. Further, the organic interposer is cheaper than the Si interposer or the glass interposer, and by using the organic interposer, the substrate cost can be reduced.

Claims (15)

A method of manufacturing a semiconductor device, comprising: (a) comprising: a surface on which a plurality of electrodes are formed; and a surface of the lower surface of the wafer supporting substrate on the opposite side of the upper surface is plasma-cleaned; b) after the above (a), the insulating adhesive is placed on the upper surface of the wafer supporting substrate; (c) after the above (b), the insulating support is applied to the upper surface of the wafer supporting substrate. After the semiconductor wafer is mounted, and (d) after the above (c), the wafer supporting substrate on which the semiconductor wafer is mounted and the insulating adhesive are heated by reflow, and the wafer support is electrically connected via a plurality of protruding electrodes. In the construction of each of the plurality of electrodes of the substrate and the plurality of electrode pads of the semiconductor wafer, the (d) engineering is performed by arranging the insulating adhesive around each of the plurality of protruding electrodes. In the state, each of the plurality of electrodes and each of the plurality of electrode pads are electrically connected via the plurality of protruding electrodes. The method of manufacturing a semiconductor device according to claim 1, wherein the project of baking the wafer supporting substrate before the (a) project has the foregoing between (b) engineering and (c) engineering Baking of insulating adhesives, The baking process of the insulating adhesive material is performed by baking the insulating adhesive material at a temperature lower than a baking temperature of the wafer support substrate on which the wafer support substrate is baked. The method of manufacturing a semiconductor device according to claim 1, wherein the project of baking the wafer supporting substrate before the (a) project has the foregoing between (b) engineering and (c) engineering In the baking process of the insulating adhesive material, the baking process of the insulating adhesive material is performed in a shorter time than the baking time of the wafer support substrate for baking the wafer support substrate; Baking of sticky materials. The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the (c) project identifies a mark formed on an outer side of the insulating adhesive material on the upper surface of the wafer supporting substrate, and the semiconductor wafer and the semiconductor wafer are The aforementioned wafer support substrate is aligned. The method of manufacturing a semiconductor device according to claim 1, wherein the (c) project is performed by aligning the semiconductor wafer with the wafer supporting substrate, and then applying the plurality of protruding electrodes to each of the plurality of protruding electrodes. At the temperature at which the melting temperature of the solder at the tip end is lower, the solder is heated and deformed, and the plurality of electrodes are respectively immersed in the respective solders. The method of manufacturing a semiconductor device according to claim 5, wherein a plating Au is formed on a surface of each of the plurality of electrodes of the wafer supporting substrate, and the plating Au is connected to the solder. A method of manufacturing a semiconductor device, comprising: (a) mounting a second substrate on a first substrate, the second substrate having an upper surface on which a plurality of electrodes are formed and a lower surface on a side opposite to the upper surface; (b) after the (a) project, the process of baking the first substrate; (c) after the (b) process, the plasma is washed by the above-mentioned second substrate; (d) the aforementioned (c) After the work, the insulating adhesive is placed on the upper surface of the second substrate; (e) after the above (d), the semiconductor wafer is mounted on the upper surface of the second substrate via the insulating adhesive; And (f) after the (e)th process, the second substrate on which the semiconductor wafer is mounted and the insulating adhesive are heated by reflow, and the plurality of electrodes of the second substrate are electrically connected via a plurality of protruding electrodes Each of the above-mentioned (f) engineering is in a state in which the insulating adhesive is placed around each of the plurality of protruding electrodes, and the plurality of electrodes are placed in the state in which the insulating adhesive is placed around the plurality of protruding electrodes. Burst Each electrode pad electrodes are connected to call each of the plural electrodes of the plural persons. The method of manufacturing a semiconductor device according to claim 7, wherein the baking process of the insulating adhesive material is provided between the (d) engineering and the (e) engineering, In the baking process of the insulating adhesive material, the insulating adhesive material is baked at a temperature lower than a baking temperature of the first substrate of the above (b). The method of manufacturing a semiconductor device according to claim 7, wherein the baking of the insulating adhesive material between the (d) engineering and the (e) engineering, the baking of the insulating adhesive material In the engineering, the insulating adhesive is baked in a shorter time than the baking time of the first substrate of the above (b) project. The method of manufacturing a semiconductor device according to the seventh aspect of the invention, wherein the (e) project identifies a mark formed on an outer side of the insulating adhesive of the upper surface of the second substrate, and the semiconductor wafer and the semiconductor wafer are The second substrate is aligned. The method of manufacturing a semiconductor device according to claim 7, wherein the (e) project is performed by aligning the semiconductor wafer and the second substrate, and applying the ratio to each of the plurality of bump electrodes At the temperature at which the melting temperature of the solder at the tip end is lower, the solder is heated and deformed, and the plurality of electrodes are respectively immersed in the respective solders. The method of manufacturing a semiconductor device according to claim 11, wherein a plating Au is formed on a surface of each of the plurality of electrodes of the second substrate, and the plating Au is connected to the solder. The method of manufacturing a semiconductor device according to claim 7, wherein the (e) engineering is by suction of a head of a flip chip bonder. The semiconductor wafer is adsorbed and held by the surface of the substrate, and the semiconductor wafer is mounted on the upper surface of the second substrate. The plane size of the adsorption surface of the head is the same as or smaller than the plane size of the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 7, wherein the second substrate is a substrate formed of ruthenium, and each of the plurality of protruding electrodes is formed of an alloy of Cu as a main component. electrode. The method of manufacturing a semiconductor device according to claim 7, wherein the plasma cleaning of the (c) process is performed by generating plasma by argon gas or oxygen.