TW201507154A - Trench gate MOSFET - Google Patents

Abstract

A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, the first trench is disposed below the second trench, and first trench is narrower than the second trench. A first insulating layer is disposed on a surface of the first trench. A first conductive layer fills up the first trench and extends into the second trench. A second conductive layer fills up the second trench. A second insulating layer is disposed between the second conductive layer and each of the body layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.

Description

Ditch-type gate MOS half-field effect transistor

The present invention relates to a semiconductor device, and more particularly to a trench gate metal-oxide-semiconductor field effect transistor (trench gate MOSFET).

Ditch-type MOS field effect transistors are widely used in power switch components such as power supplies, rectifiers or low voltage motor controllers. In general, trench-type MOS field-effect transistors are designed with vertical structures to increase component density. It uses the back side of the wafer as a drain, and the source and gate of a plurality of transistors are fabricated on the front side of the wafer. Since the drains of multiple transistors are connected in parallel, the current they can withstand can be quite large.

Work loss trench metal-oxide semiconductor field effect transistors may be divided into the switching loss (switching loss) and the conduction loss (conducting loss) two categories, the switching loss which due to the input capacitance C _iss caused due to increase the operating frequency increases. The input capacitor C _iss includes a gate-to-source capacitance C _gs and a gate-to-drain capacitance C _gd .

One conventional practice is to form a gate and a shielded gate in the trench. The shielding gate is located below the gate, the insulating layer separates the gate from the shielding gate, and the shielding gate is connected to the source. Although this method can reduce the capacitance of the gate to the drain C _gd , on the other hand, it increases the capacitance of the gate to the source C _gs , and thus cannot effectively reduce the switching loss.

In view of the above, the present invention provides a trench gate MOS field effect transistor, which can simultaneously reduce the capacitance of the gate to the drain C _gd and the capacitance of the gate to the source C _gs to effectively reduce the switching loss and improve Component performance.

The invention provides a trench gate galvanic half field effect transistor. The epitaxial layer having the first conductivity type is disposed on the substrate having the first conductivity type. The main layer having the second conductivity type is disposed in the epitaxial layer, wherein the epitaxial layer has a first trench, the main layer has a second trench, and the first trench is disposed under the second trench, and the width of the first trench is less than The width of the second ditch. The first insulating layer is disposed on a surface of the first trench. The first conductor layer fills the first trench and extends into the second trench. The second conductor layer fills the second trench. The second insulating layer is disposed between the second conductor layer and the body layer and between the second conductor layer and the first conductor layer. The dielectric layer is disposed on the epitaxial layer and covers the second conductor layer. The two doped regions having the first conductivity type are respectively disposed in the body layers on both sides of the second trench.

In an embodiment of the invention, the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.

In an embodiment of the invention, the top of the first conductor layer is non-flat.

In an embodiment of the invention, the material of the first conductor layer comprises a blend Heteropolycrystalline germanium.

In an embodiment of the invention, the material of the second conductor layer comprises doped polysilicon.

In one embodiment of the present invention, the trench gate MOS field oxide transistor further includes a third conductor layer disposed on the dielectric layer, wherein the third conductor layer is electrically connected to the body layer through the two conductor plug .

In an embodiment of the invention, the material of the third conductor layer comprises a metal.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

The invention further provides a trench-type gate MOS field effect transistor. The epitaxial layer having the first conductivity type is disposed on the substrate having the first conductivity type. The body layer having the second conductivity type is disposed in the epitaxial layer, wherein the epitaxial layer has a first trench, the main layer has a second trench, and the first trench is disposed under the second trench. The first conductor layer is disposed at least in the first trench. The second conductor layer is disposed in the second trench and surrounds an upper portion of the first conductor layer, wherein the second conductor layer is electrically insulated from the first conductor layer. The dielectric layer is disposed on the epitaxial layer and covers the second conductor layer. The two doped regions having the first conductivity type are respectively disposed in the body layers on both sides of the second trench.

In an embodiment of the invention, the first conductor layer is electrically insulated from the epitaxial layer.

In an embodiment of the invention, the second conductor layer is electrically insulated from the body layer.

In an embodiment of the invention, the first conductor layer extends into the second trench.

In an embodiment of the invention, the material of the first conductor layer comprises doped polysilicon.

In an embodiment of the invention, the material of the second conductor layer comprises doped polysilicon.

In one embodiment of the present invention, the trench gate MOS field oxide transistor further includes a third conductor layer disposed on the dielectric layer, wherein the third conductor layer is electrically connected to the body layer through the two conductor plug .

In an embodiment of the invention, the material of the third conductor layer comprises a metal.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

Based on the above, in the trench gate MOS field effect transistor of the present invention, the shielding gate is disposed under the gate, which can reduce the capacitance C _{gd of the} gate to the drain and increase the breakdown voltage of the transistor. In addition, the arrangement of the insulating layer (or dielectric layer) in the gate reduces the coupling effect between the gate and the shadow gate, thereby reducing the gate-to-source capacitance C _gs . In other words, the structure of the present invention can simultaneously reduce the gate-to-drain capacitance C _gd and the gate-to-source capacitance C _gs to effectively reduce switching losses and improve component performance.

The above described features and advantages of the present invention will be more apparent from the following description.

100, 200, 300, 400‧‧‧ Ditch-type gate MOS solar field half-effect transistor

102, 202, 302, 402‧‧‧ base

104, 204, 304, 404‧‧‧ epitaxial layer

105, 305‧‧ ‧ cover layer

107, 109, 111, 207, 209, 211, 307, 309, 311, 407, 409, 411 ‧ ‧ ditches

108, 108a, 112a, 112b, 114, 208, 208a, 212, 310, 310a, 314a, 316, 408, 408a, 412, 414 ‧ ‧ insulation

110, 110a, 116, 128, 210a, 214, 214a, 228, 312, 312a, 318, 328, 410a, 410b, 416, 428‧‧‧ conductor layer

112, 314‧‧‧Insulation material layer

120, 220, 320, 420‧‧‧ main body

122, 222, 322, 422‧‧‧ doped areas

124, 224, 324, 424‧‧ dielectric layers

126, 215, 226, 326, 426‧‧

127, 227, 327, 427‧‧‧ conductor plugs

210, 410‧‧‧ conductor material layer

308‧‧‧ spacer material layer

308a‧‧‧ spacer

1A to 1G illustrate a trench type according to a first embodiment of the present invention. A schematic cross-sectional view of a method for fabricating a gated metal oxide half field effect transistor.

2A to 2F are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a second embodiment of the present invention.

3A to 3H are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a third embodiment of the present invention.

4A to 4F are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a fourth embodiment of the present invention.

First embodiment

1A to 1G are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a first embodiment of the present invention.

First, referring to FIG. 1A, an epitaxial layer 104 having a first conductivity type and a mask layer 105 are sequentially formed on a substrate 102 having a first conductivity type. Substrate 102 is, for example, an N-type heavily doped germanium substrate. The epitaxial layer 104 is, for example, an N-type lightly doped epitaxial layer, and the formation method thereof includes performing a selective epitaxy growth (SEG) process. The material of the mask layer 105 is, for example, tantalum nitride, and the method of forming the same includes performing a chemical vapor deposition process. Next, an etching process is performed using the mask layer 105 as a mask to form the trench 107 in the epitaxial layer 104. Thereafter, the mask layer 105 is removed.

Referring to FIG. 1B, the insulating layer 108 and the conductor layer 110 are conformally formed on the surfaces of the epitaxial layer 104 and the trench 107. The material of the insulating layer 108 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. The material of the conductor layer 110 is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process. Next, an insulating material layer 112 is formed on the conductor layer 110, and the insulating material layer 112 fills the trench 107. The material of the insulating material layer 112 is, for example, tetraethhosiloxane ( TEOS ) cerium oxide, and the method for forming the same includes performing a chemical vapor deposition process.

Referring to FIG. 1C, an etch back process is performed to remove a portion of the insulating material layer 112 to form an insulating layer 112a that fills the trench 107. In an embodiment, the etch back process exposes the top surface of the conductor layer 110, which can use a time mode to control the thickness of the insulating layer 112a.

Referring to FIG. 1D, a portion of the conductor layer 110 is removed to form a conductor layer 110a that exposes the upper portion of the insulating layer 112a and the top surface and a portion of the sidewalls of the insulating layer 108. In particular, the conductor layer 110a is in the shape of a bowl or a U, which is disposed to surround the lower portion of the insulating layer 112a and is located between the insulating layer 112a and the insulating layer 108. The method of forming the conductor layer 110a is, for example, an etch back method which can control the top surface height of the conductor layer 110a using a time mode. In one embodiment, the conductor layer 110a exposes the insulating layer 108, and its height needs to match the body layer (not shown, as described later, as detailed later) or the depth of the trench 107, as an example of the insulating layer 112a. /2 high.

Referring to FIG. 1E, a portion of the insulating layer 112a and a portion of the insulating layer 108 are removed such that the remaining insulating layer 112b and the insulating layer 108a are exposed to the upper portion of the conductor layer 110a. Specifically, the conductor layer 110a protrudes from the insulating layer 112b and the insulating layer 108a, the conductor layer 110a is configured to surround the insulating layer 112b, and the insulating layer 108a is configured to surround the conductor layer 110a. The method of forming the insulating layer 112b and the insulating layer 108a is, for example, an etch back method which can control the top surface height of the insulating layer 112b and the insulating layer 108a using a time mode. In one embodiment, the insulating layer 112b and the insulating layer 108a are exposed to a height of about 1/8 to 1/10 of the conductor layer 110a. However, the invention is not limited thereto. In another embodiment, the top surface of the insulating layer 112b and the insulating layer 108a may also be substantially flush with the top surface of the conductor layer 110a.

Referring to FIG. 1F, an insulating layer 114 is formed on the surface of the epitaxial layer 104 and the trench 107, and the insulating layer 114 covers the conductor layer 110a. The material of the insulating layer 114 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. In an embodiment, the thickness of the insulating layer 114 is less than the thickness of the insulating layer 108a. However, the invention is not limited thereto. In another embodiment, the thickness of the insulating layer 114 may also be equal to or greater than the thickness of the insulating layer 108a. Next, the trench 107 is filled with the conductor layer 116. The method of forming the conductor layer 116 includes forming a layer of conductive material (not shown) on the epitaxial layer 104, and filling the trench 107 with a layer of conductive material. The material of the conductor material layer is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process. Then, an etch back process is performed to remove a portion of the conductor material layer.

Referring to FIG. 1G, two body layers 120 having a second conductivity type are respectively formed in the epitaxial layers 104 on both sides of the trench 107. The body layer 120 is, for example, a P-type body layer, and the method of forming the same includes performing an ion implantation process. Then, two doped regions 122 having a first conductivity type are respectively formed in the body layers 120 on both sides of the trench 107. The doped region 122 is, for example, an N-type heavily doped region, and the method of forming the same includes performing an ion implantation process.

A dielectric layer 124 is formed over the conductor layer 116 and the doped region 122. The material of the dielectric layer 124 is, for example, yttrium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), fluorocarbon glass (FSG) or undoped bismuth glass (USG), and the formation method thereof includes performing chemistry Vapor deposition process. Next, two openings 126 are formed through the dielectric layer 124 and the doped regions 122. The method of forming the opening includes performing a photolithography process. Thereafter, a conductor layer 128 is formed on the dielectric layer 124, wherein the conductor layer 128 fills the opening 126 to The body layer 120 is electrically connected. The conductor layer 128 filled in the opening 126 constitutes a conductor plug 127. In other words, the conductor layer 128 is electrically connected to the body layer 120 through the conductor plugs 127. The material of the conductor layer 128 may be a metal such as aluminum, and the method of forming the same includes performing a chemical vapor deposition process. So far, the manufacture of the trench gate MOS field effect transistor 100 of the first embodiment has been completed.

Hereinafter, the structure of the trench gate MOS field oxide crystal 100 of the present invention will be described with reference to FIG. 1G. Referring to FIG. 1G , the trench gate MOS field oxide crystal 100 includes an N-type substrate 102 , an N-type epitaxial layer 104 , and a P-type body layer 120 . The epitaxial layer 104 is disposed on the substrate 102. The body layer 120 is disposed in the epitaxial layer 104. In addition, the epitaxial layer 104 has a trench 109, the main layer 120 has a trench 111, the trench 109 is disposed under the trench 111, and the trench 109 and the trench 111 form a trench 107.

The trench gate MOS field oxide crystal 100 further includes an insulating layer 108a, a conductor layer 110a, an insulating layer 112b, a conductor layer 116, and an insulating layer 114. The insulating layer 108a is disposed on the surface of the trench 109, the insulating layer 112b is disposed in the trench 109, and the conductor layer 110a is disposed between the insulating layer 108a and the insulating layer 112b. The conductor layer 116 is disposed in the trench 111. The insulating layer 114 is disposed between the conductor layer 116 and the body layer 120 and between the conductor layer 116 and the conductor layer 110a. In an embodiment, the conductor layer 110a extends into the trench 111 and the insulating layer 114 covers the top of the conductor layer 110a.

The trench gate MOS half field effect transistor 100 further includes two N-type doping regions 122, a dielectric layer 124, two conductor plugs 127, and a conductor layer 128. The doped regions 122 are disposed in the body layer 120 on both sides of the trench 111. The dielectric layer 124 is disposed on the conductor layer 116 and the doping region 122. The conductor layer 128 is disposed on the dielectric layer 124, wherein the conductor layer 128 is electrically connected to the body layer 120 through the conductor plugs 127.

In the trench gate MOS field oxide crystal 100 of the first embodiment, the substrate 102 serves as a drain, the doped region 122 serves as a source, the conductor layer 116 serves as a gate, and the conductor layer 110a serves as a shield gate and is insulated. Layer 114 acts as a gate oxide layer. It is particularly noted that due to the configuration of the shadow gate (ie, conductor layer 110a), the gate-to-drain capacitance _Cgd can be reduced and the breakdown voltage of the transistor can be increased. In addition, since the insulating layer 112b is disposed in the shielding gate (ie, the conductor layer 110a) to reduce the coupling effect between the gate (ie, the conductor layer 116) and the shielding gate (ie, the conductor layer 110a), the gate pair can be lowered. The source capacitance C _gs . That is to say, the structure of the first embodiment of the present invention can reduce the capacitance of the gate to the drain C _gd and the capacitance of the gate to the source C _gs to effectively reduce switching losses and improve component performance.

Second embodiment

2A to 2F are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a second embodiment of the present invention.

First, referring to FIG. 2A, an epitaxial layer 204 having a first conductivity type is formed on a substrate 202 having a first conductivity type. The substrate 202 is, for example, an N-type germanium substrate. The epitaxial layer 204 is, for example, an N-type epitaxial layer. Then, a trench 207 is formed in the epitaxial layer 204. For the method of forming the epitaxial layer 204 and the trench 207, refer to the first embodiment, and details are not described herein again.

Next, an insulating layer 208 is conformally formed on the surfaces of the epitaxial layer 204 and the trench 207. The material of the insulating layer 208 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. Then, a conductor material layer 210 is formed on the insulating layer 208, and the conductor material layer 210 fills the trench 207. The material of the conductor material layer 210 is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process.

Thereafter, referring to FIG. 2B, an etch back process is performed to remove a portion of the conductor material layer 210 to form a conductor layer 210a at the bottom of the trench 207. In one embodiment, the etch back process exposes the top surface and portions of the sidewalls of the insulating layer 208, which can control the top surface height of the conductor layer 210a using a time mode. In one embodiment, the height of the top surface of the conductor layer 210a needs to match the depth of the body layer, such as about 1/2 of the trench depth.

Next, referring to FIG. 2C, a portion of the insulating layer 208 is removed to form an insulating layer 208a that exposes the upper portion of the conductor layer 210a. The method of forming the insulating layer 208a includes performing an etch back method until the height of about 1/8 to 1/10 of the conductor layer 210a is exposed. In an embodiment, a time mode can be used to control the bare height of the conductor layer 210a. However, the invention is not limited thereto. In another embodiment, the top surface of the insulating layer 208a may also be substantially flush with the top surface of the conductor layer 210a.

Next, referring to FIG. 2D, an insulating layer 212 is conformally formed on the surface of the epitaxial layer 204 and the trench 207, and the insulating layer 212 covers the conductor layer 210a. The material of the insulating layer 212 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. In an embodiment, the thickness of the insulating layer 212 is less than the thickness of the insulating layer 208a. However, the invention is not limited thereto. In another embodiment, the thickness of the insulating layer 212 may also be equal to or greater than the thickness of the insulating layer 208a. Next, the conductor layer 214 is conformally formed on the insulating layer 212. The material of the conductor layer 214 is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process.

Then, referring to FIG. 2E, a portion of the conductor layer 214 is removed to form a conductor layer 214a on the sidewall of the insulating layer 212. Specifically, the conductor layer 214a is disposed on the sidewall of the insulating layer 212 in the form of a spacer and has an opening 215 exposing a portion of the bottom surface of the insulating layer 212. The method of forming the conductor layer 214a includes performing an anisotropic dry etching process.

Then, referring to FIG. 2F, two body layers 220 having a second conductivity type are respectively formed in the epitaxial layers 204 on both sides of the trench 207. The body layer 220 is, for example, a P-type body layer. Thereafter, a second doped region 222 having a first conductivity type is formed in each of the body layers 220 on both sides of the trench 207. The doped region 222 is, for example, an N-type heavily doped region. Thereafter, a dielectric layer 224 is formed over the conductor layer 214a and the doped region 222, and the dielectric layer 224 is filled in the opening 215. Next, two openings 226 are formed through the dielectric layer 224 and the doped regions 222. Next, a conductor layer 228 is formed on the dielectric layer 224, wherein the conductor layer 228 is filled in the opening 226 to be electrically connected to the body layer 220. The conductor layer 228 filled in the opening 226 constitutes a conductor plug 227. In other words, the conductor layer 228 is electrically connected to the body layer 220 through the conductor plug 227. For the material and formation method of the main body layer 220, the doping region 222, the conductor plug 227, and the conductor layer 228, refer to the first embodiment, and details are not described herein again. So far, the fabrication of the trench gate MOS field effect transistor 200 of the second embodiment has been completed.

Hereinafter, the structure of the trench gate MOS field-effect transistor 200 of the present invention will be described with reference to FIG. 2F. Referring to FIG. 2F , the trench gate MOS field oxide transistor 200 includes an N-type substrate 202 , an N-type epitaxial layer 204 , and a P-type body layer 220 . The epitaxial layer 204 is disposed on the substrate 202. The body layer 220 is disposed in the epitaxial layer 204. In addition, the epitaxial layer 204 has a trench 209, the main layer 220 has a trench 211, the trench 209 is disposed under the trench 211, and the trench 209 and the trench 211 form a trench 207.

The trench gate MOS half field effect transistor 200 further includes an insulating layer 208a, a conductor layer 210a, an insulating layer 212, and a conductor layer 214a. The conductor layer 210a is disposed in the trench 209. The insulating layer 208a is disposed between the conductor layer 210a and the epitaxial layer 204. The conductor layer 214a is disposed on the sidewall of the trench 211. The insulating layer 212 is disposed on the conductor layer Between the 214a and the body layer 220 and between the conductor layer 214a and the conductor layer 210a. In an embodiment, the conductor layer 210a extends into the trench 211 and the insulating layer 212 covers the top of the conductor layer 210a.

The trench gate MOS half field effect transistor 200 further includes two N-type doped regions 222, a dielectric layer 224, two conductor plugs 227, and a conductor layer 228. The doped regions 222 are disposed in the body layer 220 on both sides of the trench 211. The dielectric layer 224 is disposed on the insulating layer 212 and fills the trench 211. That is, the dielectric layer 224 is disposed in the opening 215 of the conductor layer 214a. The conductor layer 228 is disposed on the dielectric layer 224 , wherein the conductor layer 228 is electrically connected to the body layer 220 through the conductor plug 227 .

In the trench gate MOS field-effect transistor 200 of the second embodiment, the substrate 202 serves as a drain, the doped region 222 serves as a source, the conductor layer 214a serves as a gate, and the conductor layer 210a serves as a shield gate and is insulated. Layer 212 acts as a gate oxide layer. It is particularly noted that due to the configuration of the shadow gate (ie, conductor layer 210a), the gate-to-drain capacitance _Cgd can be reduced and the breakdown voltage of the transistor can be increased. In addition, since the dielectric layer 224 is disposed in the gate (ie, the conductor layer 214a) to reduce the coupling effect between the gate (ie, the conductor layer 214a) and the shadow gate (ie, the conductor layer 210a), the gate pair can be lowered. The source capacitance C _gs . That is to say, the structure of the second embodiment of the present invention can simultaneously reduce the capacitance of the gate to the drain C _gd and the capacitance of the gate to the source C _gs to effectively reduce switching losses and improve component performance.

Third embodiment

3A to 3H are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a third embodiment of the present invention.

First, referring to FIG. 3A, an epitaxial layer 304 and a mask layer 305 having a first conductivity type are sequentially formed on a substrate 302 having a first conductivity type. Substrate 302 For example, it is an N-type crucible substrate. The epitaxial layer 304 is, for example, an N-type epitaxial layer. The material of the mask layer 305 is, for example, hafnium oxide, tantalum nitride or hafnium oxynitride, and the method of forming the same includes performing a chemical vapor deposition process. Next, an etching process is performed using the mask layer 305 as a mask to form a trench 311 in the epitaxial layer 304. Next, a spacer material layer 308 is formed on the surface of the epitaxial layer 304 and the trench 311. The material of the spacer material layer 308 is, for example, hafnium oxide, tantalum nitride or hafnium oxynitride, and the method of forming the same includes performing a chemical vapor deposition process. In this embodiment, the mask layer 305 is different in material from the spacer material layer 308.

Thereafter, referring to FIG. 3B, an anisotropic dry etching process is performed to remove a portion of the spacer material layer 308 to form a spacer 308a on the sidewall of the trench 311. In this embodiment, since the etching selectivity of the spacer material layer 308 to the mask layer 305 is sufficiently high, the above-described anisotropic dry etching process substantially stops on the surface of the mask layer 305. In other words, the mask layer 305 can protect the surface of the epitaxial layer 304 from the surface of the epitaxial layer 304 from subsequent etching processes. Then, a portion of the epitaxial layer 304 is removed by using the mask layer 305 and the spacer 308a as a mask to form a trench 309 under the trench 311. The method of forming the trench 309 is, for example, an etching process. Thereafter, the spacer 308a is removed. Since the method of forming the trench 309 is to cover the spacer 308a, it is a self-aligned process in which the width of the trench 309 is smaller than the width of the trench 311. In addition, the trench 309 is disposed below the trench 311, and the trench 309 and the trench 311 form a trench 307.

Next, referring to FIG. 3C, the insulating layer 310 is conformally formed on the surface of the epitaxial layer 304 and the trench 307. The material of the insulating layer 310 is, for example, cerium oxide, and the forming method thereof includes performing a thermal oxidation method or a chemical vapor deposition process. Next, a conductor layer 312 is formed on the insulating layer 310. In particular, the conductor layer 312 is conformally formed On the surface of the epitaxial layer 304 and the trench 311, the trench 309 is filled. The material of the conductor layer 312 is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process. Then, an insulating material layer 314 is formed on the epitaxial layer 304, and the insulating material layer 314 fills the trench 311. The material of the insulating material layer 314 is, for example, cerium oxide, and the method of forming the same includes performing a chemical vapor deposition process.

Then, referring to FIG. 3D, an etch back process is performed to remove a portion of the insulating material layer 314 to form an insulating layer 314a filling the trench 311. In one embodiment, the etch back process exposes the top surface of conductor layer 312, which can use time mode to control the thickness of insulating layer 314a. In one embodiment, the width of the insulating layer 314a is substantially equal to the width of the conductor layer 312 in the trench 309, as shown in Figure 3D. However, the invention is not limited thereto. In another embodiment, the width of the insulating layer 314a may also be greater than the width of the conductor layer 312 in the trench 309.

Next, referring to FIG. 3E, a portion of the conductor layer 312 is removed to form a conductor layer 312a below the insulating layer 314a. The method of forming the conductor layer 312a includes performing an anisotropic dry etching process using the insulating layer 314a as a mask. In addition, since the above method is based on the insulating layer 314a, it is a self-aligned process in which the conductor layer 312a is located directly under the insulating layer 314a. Moreover, since the width of the insulating layer 314a is equal to or greater than the width of the conductor layer 312 in the trench 309, the above etching process does not remove portions of the conductor layer 312 in the trench 309.

Then, referring to FIG. 3F, the insulating layer 314a and the portion of the insulating layer 310 are removed to form an insulating layer 310a that exposes the upper portion of the conductor layer 312a. The method of forming the insulating layer 310a is, for example, an etch back method which can control the top surface height of the insulating layer 310a using a time mode. In one embodiment, the insulating layer 310a exposes a height of about 1/8 to 1/10 of the conductor layer 312a. In another embodiment, the insulating layer 310a is only located in the trench On the surface of 309.

Next, referring to FIG. 3G, an insulating layer 316 is conformally formed on the surface of the epitaxial layer 304 and the trench 307, and the insulating layer 316 covers the conductor layer 312a. The material of the insulating layer 316 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. In an embodiment, the thickness of the insulating layer 316 is less than the thickness of the insulating layer 310a. However, the invention is not limited thereto. In another embodiment, the thickness of the insulating layer 316 may also be equal to or greater than the thickness of the insulating layer 310a. Next, the trench 311 is filled with the conductor layer 318. The method of forming the conductor layer 318 includes forming a layer of conductive material (not shown) on the epitaxial layer 304, and filling the trench 311 with a layer of conductive material. The material of the conductor material layer is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process. Then, an etch back process is performed to remove a portion of the conductor material layer.

Then, referring to FIG. 3H, two body layers 320 having a second conductivity type are respectively formed in the epitaxial layers 304 on both sides of the trench 311. The body layer 320 is, for example, a P-type body layer. Thereafter, a second doped region 322 having a first conductivity type is formed in the body layer 320 on both sides of the trench 311, respectively. Doped region 322 is, for example, an N-type heavily doped region. Thereafter, a dielectric layer 324 is formed over the conductor layer 318 and the doped region 322. Next, two openings 326 are formed through dielectric layer 324 and doped region 322. Next, a conductor layer 328 is formed on the dielectric layer 324, wherein the conductor layer 328 is filled in the opening 326 to be electrically connected to the body layer 320. The conductor layer 328 filled in the opening 326 constitutes a conductor plug 327. In other words, the conductor layer 328 is electrically connected to the body layer 320 through the conductor plug 327. For the material and formation method of the main body layer 320, the doping region 322, the conductor plug 327 and the conductor layer 328, please refer to the first embodiment, and details are not described herein again. So far, the manufacture of the trench gate MOS field effect transistor 300 of the third embodiment has been completed.

Hereinafter, the trench gate galvanic half of the present invention will be described with reference to FIG. 3H. The structure of the field effect transistor 300. Referring to FIG. 3H, the trench gate MOS field oxide transistor 300 includes an N-type substrate 302, an N-type epitaxial layer 304, and a P-type body layer 320. The epitaxial layer 304 is disposed on the substrate 302. The body layer 320 is disposed in the epitaxial layer 304. In addition, the epitaxial layer 304 has a trench 309, the main layer 320 has a trench 311, the trench 309 is disposed under the trench 311, and the trench 309 and the trench 311 form a trench 307.

The trench gate MOS half field effect transistor 300 further includes an insulating layer 310a, a conductor layer 312a, an insulating layer 316, and a conductor layer 318. The insulating layer 310a is disposed on the surface of the trench 309. The conductor layer 312a fills the trench 309. The conductor layer 318 is disposed in the trench 311. The insulating layer 316 is disposed between the conductor layer 318 and the body layer 320 and between the conductor layer 318 and the conductor layer 312a. In an embodiment, the conductor layer 312a extends into the trench 311 and the insulating layer 316 covers the top of the conductor layer 312a.

The trench gate MOS half field effect transistor 300 further includes two N-type doped regions 322, a dielectric layer 324, two conductor plugs 327, and a conductor layer 328. The doped regions 322 are disposed in the body layer 320 on both sides of the trench 311. The dielectric layer 324 is disposed on the conductor layer 318 and the doping region 322. The conductor layer 328 is disposed on the dielectric layer 324 , wherein the conductor layer 328 is electrically connected to the body layer 320 through the conductor plug 327 .

In the trench gate MOS field III transistor of the third embodiment, the substrate 302 serves as a drain, the doped region 322 serves as a source, the conductor layer 318 serves as a gate, and the conductor layer 312a serves as a shield gate and is insulated. Layer 316 acts as a gate oxide layer. It is particularly noted that due to the configuration of the shadow gate (ie, conductor layer 312a), the gate-to-drain capacitance _Cgd can be reduced and the breakdown voltage of the transistor can be increased. Moreover, since the width of the trench 309 is smaller than the width of the trench 311, and the thickness of the insulating layer 310a is greater than the thickness of the insulating layer 316, the width of the shadow gate (ie, the conductor layer 312a) is smaller than the width of the gate (ie, the conductor layer 318). Therefore, the coupling effect between the gate (i.e., the conductor layer 318) and the shadow gate (i.e., the conductor layer 312a) can be reduced, thereby reducing the gate-to-source capacitance _Cgs . That is to say, the structure of the present invention can simultaneously reduce the capacitance of the gate to the drain C _gd and the capacitance of the gate to the source C _gs to effectively reduce switching losses and improve component performance.

Fourth embodiment

4A to 4F are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to a fourth embodiment of the present invention.

First, referring to FIG. 4A, an epitaxial layer 404 having a first conductivity type is formed on a substrate 402 having a first conductivity type. Substrate 402 is, for example, an N-type germanium substrate. The epitaxial layer 404 is, for example, an N-type epitaxial layer. Then, a trench 407 is formed in the epitaxial layer 404. For the method of forming the epitaxial layer 404 and the trench 407, refer to the first embodiment, and details are not described herein again.

Next, an insulating layer 408 is conformally formed on the surface of the epitaxial layer 404 and the trench 407. The material of the insulating layer 408 is, for example, ruthenium oxide, and the method of forming the same includes performing a thermal oxidation process or a chemical vapor deposition process. Then, a conductor material layer 410 is formed on the epitaxial layer 404, and the conductor material layer 410 fills the trench 407. The material of the conductor material layer 410 is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process.

Thereafter, referring to FIG. 4B, an etch back process is performed to remove a portion of the conductor material layer 410 to form the conductor layer 410a in the trench 407. In one embodiment, the etch back process exposes the top surface and portions of the sidewalls of the insulating layer 408, which can control the thickness of the conductor layer 410a using a time mode.

Then, referring to FIG. 4C, a portion of the insulating layer 408 is removed to form a bare The insulating layer 408a on the upper portion of the conductor layer 410a. The method of forming the insulating layer 408a includes performing an etch back method until the height of about 1/3 to 2/5 of the conductor layer 410a is exposed. In an embodiment, the time mode can be used to control the bare height of the conductor layer 410a. In one embodiment, the top surface of the insulating layer 408a is required to match the depth of the body layer, for example about 1/2 of the trench depth.

Next, referring to FIG. 4D, an oxidation process is performed to oxidize the upper portion of the conductor layer 410a not covered by the insulating layer 408a into the insulating layer 412, leaving the conductor layer 410b, and the oxidation process is simultaneously performed on the surface of the epitaxial layer 404 and An insulating layer 414 is formed on the sidewall of the trench 407. The material of the insulating layer 412 and the insulating layer 414 is, for example, yttrium oxide. In one embodiment, the oxidation process oxidizes the entire upper portion of the conductor layer 410a as shown in FIG. 4D. In another embodiment (not shown), the above oxidation process only partially oxidizes the upper portion of the conductor layer 410a. Further, in an embodiment, the thickness of the insulating layer 414 is less than the thickness of the insulating layer 408a. However, the invention is not limited thereto. In another embodiment, the thickness of the insulating layer 414 may also be equal to or greater than the thickness of the insulating layer 408a.

Then, referring to FIG. 4E, a conductor layer 416 is formed in the trench 407. The method of forming the conductor layer 416 includes forming a conductor material layer (not shown) on the epitaxial layer 404, and the conductor material layer covers the insulating layer 412, the insulating layer 414, and fills the trench 407. The material of the conductor material layer is, for example, doped polysilicon, and the method of forming the same includes performing a chemical vapor deposition process. Then, an etch back process is performed to remove a portion of the conductor material layer.

Next, referring to FIG. 4F, two body layers 420 having a second conductivity type are respectively formed in the epitaxial layers 404 on both sides of the trench 407. The body layer 420 is, for example, a P-type body layer. Thereafter, a second doped region 422 having a first conductivity type is formed in the body layer 420 on both sides of the trench 407, respectively. Doped region 422 is, for example, an N-type heavily doped region. It Thereafter, a dielectric layer 424 is formed over the conductor layer 416 and the doped region 422. Next, two openings 426 are formed through dielectric layer 424 and doped region 422. Next, a conductor layer 428 is formed on the dielectric layer 424, wherein the conductor layer 428 is filled in the opening 426 to be electrically connected to the body layer 420. The conductor layer 428 filled in the opening 426 constitutes a conductor plug 427. In other words, the conductor layer 428 is electrically connected to the body layer 420 through the conductor plug 427. For the material and formation method of the main body layer 420, the doping region 422, the conductor plug 427 and the conductor layer 428, refer to the first embodiment, and details are not described herein again. So far, the fabrication of the trench gate MOS field effect transistor 400 of the fourth embodiment has been completed.

Hereinafter, the structure of the trench gate MOS field-effect transistor 400 of the present invention will be described with reference to FIG. 4F. Referring to FIG. 4F , the trench gate MOS field oxide transistor 400 includes an N-type substrate 402 , an N-type epitaxial layer 404 , and a P-type body layer 420 . The epitaxial layer 204 is disposed on the substrate 402. The body layer 420 is disposed in the epitaxial layer 404. In addition, the epitaxial layer 404 has a trench 409, the main layer 420 has a trench 411, the trench 409 is disposed under the trench 411, and the trench 409 and the trench 411 form a trench 407.

The trench gate MOS half field effect transistor 400 further includes an insulating layer 408a, a conductor layer 410b, an insulating layer 412, an insulating layer 414, and a conductor layer 416. The conductor layer 410b is disposed in the trench 409. The insulating layer 408a is disposed between the conductor layer 410b and the epitaxial layer 404. The insulating layer 412 is disposed in the trench 411 and covers the conductor layer 410b. That is, the width of the insulating layer 412 is greater than or equal to the width of the conductor layer 410b. Further, the conductor layer 416 is disposed in the trench 411 and covers the insulating layer 412. The insulating layer 414 is disposed between the conductor layer 416 and the body layer 420.

The trench gate MOS half field effect transistor 400 further includes two N-type doped regions 422, a dielectric layer 424, two conductor plugs 427, and a conductor layer 428. Doping The regions 422 are disposed in the body layer 420 on both sides of the trench 411. The dielectric layer 424 is disposed on the epitaxial layer 404 and covers the conductor layer 416. The conductor layer 428 is disposed on the dielectric layer 424, wherein the conductor layer 428 is electrically connected to the body layer 420 through the conductor plug 427.

In the trench gate MOS field-effect transistor 400 of the fourth embodiment, the substrate 402 serves as a drain, the doped region 422 serves as a source, the conductor layer 416 serves as a gate, and the conductor layer 410b serves as a shield gate and is insulated. Layer 414 acts as a gate oxide layer. It is particularly noted that due to the configuration of the shadow gate (ie, conductor layer 410b), the gate-to-drain capacitance _Cgd can be reduced and the breakdown voltage of the transistor can be increased. In addition, since the dielectric layer 412 is disposed in the gate (ie, the conductor layer 416) to reduce the coupling effect between the gate (ie, the conductor layer 416) and the shadow gate (ie, the conductor layer 410b), the gate pair can be lowered. The source capacitance C _gs . That is to say, the structure of the present invention can simultaneously reduce the capacitance of the gate to the drain C _gd and the capacitance of the gate to the source C _gs to effectively reduce switching losses and improve component performance.

Further, in the first to fourth embodiments, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. Those skilled in the art will appreciate that the first conductivity type may also be P-type and the second conductivity type may be N-type.

In summary, in the trench gate MOS field effect transistor of the present invention, the shielding gate is disposed under the gate, which can reduce the capacitance C _{gd of the} gate to the drain and increase the breakdown voltage of the transistor. In addition, the insulating layer (or dielectric layer) is disposed in the gate or the shielding gate to reduce the coupling effect between the gate and the shielding gate, thereby reducing the gate-to-source capacitance C _gs . Alternatively, by forming the upper and lower narrow trenches, the coupling effect between the gate of the second trench and the shielding gate of the first trench is reduced, and the gate-to-source capacitance C _gs can also be reduced. In other words, the structure of the present invention can simultaneously reduce the gate-to-drain capacitance C _gd and the gate-to-source capacitance C _gs to effectively reduce switching losses and improve component performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

300‧‧‧ Ditch-type gate galvanic half-field effect transistor

302‧‧‧Base

304‧‧‧ epitaxial layer

307, 309, 311‧‧‧ Ditch

310a, 316‧‧‧ insulation

312a, 318, 328‧‧‧ conductor layers

320‧‧‧ body layer

322‧‧‧Doped area

324‧‧‧ dielectric layer

326‧‧‧ openings

327‧‧‧ Conductor plug

Claims (17)

A trench-type gate MOS field-effect transistor comprising: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type disposed on the substrate; and having one of the second conductivity types The main layer is disposed in the epitaxial layer, wherein the epitaxial layer has a first trench, the main layer has a second trench, the first trench is disposed under the second trench, and the first trench The width of the second trench is smaller than the width of the second trench; a first insulating layer is disposed on the surface of the first trench; a first conductive layer fills the first trench and extends into the second trench; a conductor layer filling the second trench; a second insulating layer disposed between the second conductor layer and the body layer and between the second conductor layer and the first conductor layer; a dielectric layer, configured And surrounding the epitaxial layer and covering the second conductive layer; and the two doped regions having the first conductivity type are respectively disposed in the main layer on both sides of the second trench. The trench gate MOS field effect transistor of claim 1, wherein the second insulating layer has a thickness smaller than a thickness of the first insulating layer. The trench gate MOS field effect transistor of claim 1, wherein the top of the first conductor layer is non-flat. The trench gate MOS field effect transistor of claim 1, wherein the material of the first conductor layer comprises doped polysilicon. The trench gate MOS field effect transistor of claim 1, wherein the material of the second conductor layer comprises doped polysilicon. The trench gate MOS field effect transistor of claim 1, further comprising a third conductor layer disposed on the dielectric layer, wherein the third conductor layer passes through the two conductor plug and the The main body layer is electrically connected. The trench gate MOS field effect transistor of claim 6, wherein the material of the third conductor layer comprises a metal. The trench gate MOS field effect transistor of claim 1, wherein the first conductivity type is N type, the second conductivity type is P type; or the first conductivity type is P type, The second conductivity type is an N type. A trench-type gate MOS field-effect transistor comprising: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type disposed on the substrate; and having one of the second conductivity types The main layer is disposed in the epitaxial layer, wherein the epitaxial layer has a first trench, the main layer has a second trench, and the first trench is disposed under the second trench; a first conductor a second conductor layer disposed in the second trench and surrounding the upper portion of the first conductor layer, wherein the second conductor layer is electrically insulated from the first conductor layer; a dielectric layer disposed on the epitaxial layer and covering the second conductor layer; and a second doped region having the first conductivity type disposed in the body layer on both sides of the second trench. The trench gate MOS field effect transistor of claim 9, wherein the first conductor layer is electrically insulated from the epitaxial layer. The trench gate MOS field effect transistor of claim 9, wherein the second conductor layer is electrically insulated from the body layer. The trench gate MOS field effect transistor of claim 9, wherein the first conductor layer extends into the second trench. The trench gate MOS field effect transistor of claim 9, wherein the material of the first conductor layer comprises doped polysilicon. The trench gate MOS field effect transistor of claim 9, wherein the material of the second conductor layer comprises doped polysilicon. The trench gate MOS field effect transistor of claim 9 further comprising a third conductor layer disposed on the dielectric layer, wherein the third conductor layer passes through the two conductor plug and the The main body layer is electrically connected. The trench gate MOS field effect transistor of claim 15, wherein the material of the third conductor layer comprises a metal. The trench-type gate MOS field effect transistor according to claim 9, wherein the first conductivity type is N-type, the second conductivity type is P-type; or the first conductivity type is P-type, The second conductivity type is an N type.