TW201446103A - Circuit board and method for manufacturing same - Google Patents

Abstract

The present invention relates to a circuit board. The circuit board includes a dielectric layer, a first trace later and a second trace layer. The first trace layer and the second trace layer are formed on two opposite side of the dielectrical layer. Portion of the first trace layer is embedded in the dielectrical layer, other portion of the first trace layer protrudes from the dielectrical layer. The second trace layer is formed on the opposite surface of the dielectrical layer. The present disclosure also provides a method for manufacturing the circuit board.

Description

Circuit board and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing technology, and in particular, to a circuit board and a manufacturing method thereof.

In the fabrication process of the circuit board, a build-up method or a semi-additive method is usually employed, and the obtained conductive line is formed on the surface of the dielectric layer. That is, the conductive lines all protrude from the surface of the dielectric layer. In order to protect the conductive lines, it is usually necessary to form a solder resist layer on the surface of the conductive lines. The solder resist layer is usually formed by printing a solder resist ink. When the solder resist layer is formed by printing, the solder resist layer to be formed covers the gap between the conductive trace and the conductive trace to be covered. Since the conductive wiring layer itself has a thickness, the thickness of the solder resist layer to be formed is larger than the thickness of the conductive wiring. When the thickness of the wire line is large, the thickness of the formed solder resist layer also needs to be increased, which is disadvantageous for the thinning of the circuit board.

Moreover, the method of fabricating the conductive lines in the prior art is also disadvantageous for the fabrication of thin lines.

Therefore, it is necessary to provide a method of manufacturing a circuit board, which reduces the thickness of the solder resist layer of the circuit board, thereby reducing the thickness of the circuit board.

A circuit board manufacturing method comprising the steps of: providing a metal carrier having opposite first and second surfaces; forming a first photoresist pattern layer on a side of the first surface; a portion of the metal carrier not covered by the first photoresist pattern layer is etched away to form a recess pattern complementary to the first photoresist pattern layer in the metal carrier; Electroplating metal in the groove pattern forms a first conductive circuit layer, the first conductive circuit layer is completely filled and protrudes from the groove pattern; the first photoresist pattern layer is removed; and the first conductive circuit layer is Pressing a dielectric layer on one side, a first conductive circuit layer protruding from the metal carrier is embedded in the dielectric layer; forming a second conductive circuit layer on a side of the dielectric layer away from the first conductive layer; and removing The metal carrier.

A circuit board comprising a dielectric layer, a first conductive circuit layer and a second conductive circuit layer, the first conductive circuit layer and the second conductive circuit layer being formed on opposite sides of the dielectric layer, the first conductive The wiring layer is partially embedded in the dielectric layer, partially protruding from the dielectric layer, and the second conductive wiring layer is formed on a surface of the dielectric layer.

Compared with the prior art, in the technical solution, since the first conductive circuit layer portion is disposed in the dielectric layer, a portion protrudes from the dielectric layer, so that when the solder resist layer is formed on the surface of the first conductive line, the thickness may be adopted. The smaller solder resist layer can cover the first conductive circuit layer and the second conductive circuit layer, thereby reducing the thickness of the solder resist layer, thereby reducing the thickness of the circuit board. Moreover, since the first conductive wiring layer is partially embedded in the dielectric layer and the remaining portion is located in the solder resist layer, the bonding ability of the first conductive wiring layer and the dielectric layer can be increased. Compared with the prior art, the conductive circuit layer protrudes from the dielectric layer, and the stress concentration on the intersection of the dielectric layer, the conductive circuit layer and the solder resist layer when the circuit board is bent can be avoided to cause the dielectric layer and the conductive circuit layer and The solder resist layers are separated from each other to improve the quality of the board.

100. . . Circuit board

110. . . First copper foil

120. . . Metal carrier

121. . . First surface

122. . . Second surface

131. . . First photoresist pattern layer

132. . . Photoresist layer

140. . . First conductive circuit layer

123. . . Groove pattern

150. . . Dielectric layer

151. . . Blind hole

160. . . Second copper foil

170. . . Second conductive circuit layer

171. . . Electroplated seed layer

173. . . Plating metal graphics

181. . . First solder mask

1811. . . First opening

1401. . . First electrical contact pad

1402. . . First protective layer

182. . . Second solder mask

1821. . . Second opening

1701. . . Second electrical contact pad

1702. . . Second protective layer

1 is a schematic cross-sectional view of a first copper foil and a metal carrier provided by an embodiment of the present technical solution.

2 is a cross-sectional view showing the first photoresist pattern and the second photoresist layer formed on the surface of the first copper foil and the metal carrier of FIG. 1.

3 is a schematic cross-sectional view showing the formation of a groove pattern in the metal carrier of FIG. 2 and electroplating to form a first conductive wiring layer.

4 is a cross-sectional view of the first photoresist pattern and the second photoresist layer of FIG.

FIG. 5 is a cross-sectional view showing the first conductive layer of FIG. 4 after the dielectric layer and the second copper foil are pressed together.

6 is a schematic cross-sectional view showing one side of the dielectric layer of FIG. 5 after forming a plated metal pattern.

Figure 7 is a schematic cross-sectional view of Figure 6 after removal of the metal carrier.

FIG. 8 is a schematic cross-sectional view of FIG. 7 after removing the first copper foil, the second copper foil, and the plating seed layer.

9 is a schematic cross-sectional view of a circuit board provided by the present technical solution.

Hereinafter, the technical solution provided by the present technical solution is described by using a specific embodiment.

The circuit board manufacturing method provided by the embodiment of the technical solution includes the following steps:

In the first step, referring to FIG. 1, a first copper foil 110 and a metal carrier 120 are provided.

The first copper foil 110 is a thin copper foil, and the first copper foil 110 has a thickness of 2 micrometers to 5 micrometers. The metal carrier 120 is made of a metal material different from that of the first copper foil 110. In this embodiment, the metal carrier 120 is made of metal aluminum. It can be understood that the metal carrier 120 can also be made of other metals.

The thickness of the metal carrier 120 is greater than the thickness of the first copper foil 110, and the metal carrier 120 has sufficient mechanical strength to support the first copper foil 110.

The metal carrier 120 has opposing first and second surfaces 121, 122. The first copper foil 110 is formed on the first surface 121 of the metal carrier 120.

In the second step, referring to FIG. 2, a first photoresist pattern layer 131 is formed on the surface of the first copper foil 110, and a photoresist layer 132 is formed on the second surface 122 of the metal carrier board 120.

This step may be specifically: first, a first photoresist layer is formed on the surface of the first copper foil 110, and a photoresist layer 132 is simultaneously formed on the second surface. The first photoresist layer and the photoresist layer 132 may be formed by laminating a dry film or printing a liquid photosensitive ink. Then, the first photoresist layer and the photoresist layer 132 are exposed and developed such that a portion of the material of the first photoresist layer is removed, thereby obtaining a first photoresist pattern. Layer 131. The photoresist layer 132 remains on the second surface 122 after exposure and development.

In the third step, referring to FIG. 3, the first copper foil 110 and the part of the metal carrier 120 not covered by the first photoresist pattern layer 131 are etched away to form and form in the metal carrier 120. A photoresist pattern layer 131 complements the groove pattern 123.

In this step, the first copper foil 110 not covered by the first photoresist pattern layer 131 is first etched away by using a copper etching solution, so that the first surface 121 of the portion of the metal carrier 120 is exposed. Then, an exposed portion of the metal carrier 120 is etched away from the first surface 121 side by an etching liquid corresponding to the metal of the metal carrier 120, thereby obtaining a groove pattern 123. In the present embodiment, the metal carrier 120 is made of aluminum. When the metal carrier 120 is etched, the etching solution used is an aluminum etching solution.

In the fourth step, electroplating is performed inside the groove pattern 123 to form the first conductive wiring layer 140.

In the present embodiment, the inside of the groove pattern 123 is filled with metal by electroplating. The first conductive wiring layer 140 may be formed by plating metal copper. By controlling the time of plating, the plated metal completely fills the groove pattern 123 and protrudes from the groove pattern 123. That is, the thickness of the first conductive wiring layer 140 is greater than the depth of the groove pattern 123.

In the fifth step, referring to FIG. 4 together, the first photoresist pattern layer 131 and the photoresist layer 132 are removed.

In this step, the first photoresist pattern layer 131 and the photoresist layer 132 may be removed by stripping.

In the sixth step, referring to FIG. 5, the dielectric layer 150 is pressed on the side of the first conductive wiring layer 140.

A portion of the first conductive wiring layer 140 protruding from the first copper foil 110 is embedded in the dielectric layer 150 by press bonding. In the present embodiment, when the dielectric layer 150 is pressed, the second copper foil 160 is also press-bonded. The second copper foil 160 is formed on a side of the dielectric layer 150 away from the first conductive wiring layer 140.

In the seventh step, referring to FIG. 6, a plating metal pattern 173 is formed on a side of the dielectric layer 150 away from the first conductive wiring layer 140.

The forming of the electroplated metal pattern 173 can be formed by a semi-additive method, and specifically includes the following steps:

First, a blind via 151 is formed in the dielectric layer 150. If the surface of the dielectric layer 150 is formed with the second copper foil 160, the surface of the second copper foil 160 needs to be blackened before the blind holes 151 are formed, so as to absorb the energy of the laser, so that the laser can penetrate the second The copper foil 160 and the dielectric layer 150 form a blind via 151. After the blind holes are formed, a step of desmear may be further included to clean the inside of the blind holes 151.

Then, a plating seed layer 171 is formed on the inner wall of the blind via 151 and the surface of the dielectric layer 150.

In this embodiment, since the second copper foil 160 is formed on the surface of the dielectric layer 150, the plating seed layer 171 is formed on the surface of the second copper foil 160. The plating seed layer 171 can be formed by electroless copper plating or copper sputtering.

Next, a second photoresist pattern is formed on the surface of the plating seed layer 171.

Next, a plating metal pattern 173 is formed on the surface of the plating seed layer 171 by electroplating. The plated metal pattern 173 completely fills the blind vias 151 and is formed in the spaces between the second photoresist patterns.

Finally, the second photoresist pattern is removed.

In the eighth step, referring to FIG. 7, the metal carrier 120 is removed.

In this step, the metal carrier 120 is removed by etching.

In the ninth step, referring to FIG. 8, the first copper foil 110 is removed, and the plating seed layer 171 not covered by the plated metal pattern 173 is removed to obtain the second conductive wiring layer 170.

Since the thickness of the first conductive wiring layer 140 and the plating metal pattern 173 is much larger than the thickness of the first copper foil 110 and the plating seed layer 171. By controlling the etching time, the first copper foil 110 and the plating seed layer 171 are etched away, and the first conductive wiring layer 140 and the plating metal pattern 173 are only reduced in thickness.

It can be understood that, in this embodiment, since the second copper foil 160 is further disposed between the plating seed layer 171 and the dielectric layer 150, the second copper foil 160 is etched away during etching.

In this embodiment, the functions of the first copper foil 110 and the second copper foil 160 can be used to better conduct current during the electroplating process to ensure that the formed electroplated copper is more dense. It can be understood that, because the metal carrier 120 has electrical conductivity, the first copper foil 110 may not be disposed in the embodiment, and the first photoresist pattern layer 131 may be directly formed on the metal carrier 120. The first surface 121. Moreover, when the groove pattern is formed, a part of the metal carrier 120 may be directly etched to obtain a groove pattern without etching the first copper foil 110. Similarly, the surface of the dielectric layer 150 may not be pressed against the second copper foil 160, and the plating seed layer 171 may be directly formed on the surface of the dielectric layer 150 for electroplating.

When the first copper foil 110 and the second copper foil 160 are not provided, this step only removes the plating seed layer 171 from which the second photoresist pattern 172 is exposed.

The second conductive wiring layer 170 is composed of a second copper foil 160, a plating seed layer 171, and a plating metal pattern 173. The second copper foil 160 is formed on the surface of the dielectric layer 150. The plating seed layer 171 is located between the plating metal pattern 173 and the second copper foil 160. It can be understood that when the second copper foil 160 is not provided, the second conductive wiring layer 170 is composed of the plating seed layer 171 and the plating metal pattern 173.

In the tenth step, referring to FIG. 9, a first solder resist layer 181 is formed on one side of the first conductive wiring layer 140, and a second solder resist layer 182 is formed on the second conductive wiring layer 170 side to obtain a circuit board 100.

The first solder resist layer 181 has a plurality of first openings 1811 , and a portion of the first conductive trace layer 140 is exposed from the first openings 1811 , thereby obtaining a plurality of first electrical contact pads 1401 . The second solder resist layer 182 has a plurality of second openings 1821, and a portion of the second conductive trace layer 170 is exposed from the second openings 1821, thereby obtaining a plurality of second electrical contact pads 1701.

In the eleventh step, a first protective layer 1402 is formed on the surface of the first electrical contact pad 1401, and a second protective layer 1702 is formed on the surface of the second electrical contact pad 1701.

The first protective layer 1402 and the second protective layer 1702 may be an organic solder resist film (OSP) or a nickel palladium gold layer.

After that, solder balls may also be formed on the first protective layer 1402 and the second protective layer 1702 to facilitate packaging of the components.

Further, the circuit board manufacturing method provided by the technical solution can also be used for the fabrication of a multi-layer circuit board, that is, after the ninth step, the layer-by-layer fabrication is continued, so that the multilayer circuit board can be obtained.

Referring to FIG. 9 , the technical solution further provides a circuit board 100 . The circuit board 100 includes a dielectric layer 150 , a first conductive circuit layer 140 , and a second conductive circuit layer 170 .

The first conductive wiring layer 140 and the second conductive wiring layer 170 are respectively formed on opposite sides of the dielectric layer 150. The first conductive wiring layer 140 is partially embedded in the dielectric layer 150, and the remaining portion protrudes from the dielectric layer 150. The second conductive wiring layer 170 protrudes from the dielectric layer 150. The first conductive circuit layer 140 and the second conductive circuit layer 170 are electrically connected to each other through the conductive blind holes.

In this embodiment, the second conductive circuit layer 170 is composed of a second copper foil 160, a plating seed layer 171, and a plated metal pattern 173. The second copper foil 160 is formed on the surface of the dielectric layer 150. The plating seed layer 171 is located between the plating metal pattern 173 and the second copper foil 160.

The circuit board manufacturing method provided by the technical solution can also be applied to the fabrication of a rigid-flex board.

In the technical solution, since the first conductive circuit layer 140 is partially disposed in the dielectric layer and partially protrudes from the dielectric layer, when the solder resist layer is formed on the surface of the first conductive line, the solder resist having a small thickness may be used. The layer can cover the first conductive circuit layer and the second conductive circuit layer, thereby reducing the thickness of the solder resist layer, thereby reducing the thickness of the circuit board.

Moreover, since the first conductive wiring layer 140 is partially embedded in the dielectric layer 150 and the remaining portion is located in the solder resist layer, the bonding ability of the first conductive wiring layer 140 and the dielectric layer 150 can be increased. Compared with the prior art, the conductive circuit layer protrudes from the dielectric layer 150, and the stress concentration on the intersection of the dielectric layer, the conductive circuit layer and the solder resist layer when the circuit board is bent can be avoided to cause the dielectric layer and the conductive circuit layer. And the solder resist layers are separated from each other to improve the quality of the board.

Further, in the circuit board manufacturing process provided by the technical solution, the second copper foil 160 is press-bonded on the surface of the dielectric layer, and the bonding capability of the second copper foil 160 and the dielectric layer 150 is greater than that of the plating seed layer 171 and the dielectric layer. 150 combined ability. Therefore, in the etching process, the circuit board manufacturing method provided by the present technical solution does not separate the plating seed layer from the dielectric layer due to etching side etching, compared to the prior art forming the plating seed layer directly on the surface of the dielectric layer. This causes the plating metal to separate from the dielectric layer.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100. . . Circuit board

140. . . First conductive circuit layer

160. . . Second copper foil

170. . . Second conductive circuit layer

171. . . Electroplated seed layer

173. . . Plating metal graphics

181. . . First solder mask

1811. . . First opening

1401. . . First electrical contact pad

1402. . . First protective layer

182. . . Second solder mask

1821. . . Second opening

1701. . . Second electrical contact pad

1702. . . Second protective layer

Claims (10)

A circuit board manufacturing method includes the steps of:
Providing a metal carrier having opposite first and second surfaces;
Forming a first photoresist pattern layer on one side of the first surface;
Etching a portion of the metal carrier that is not covered by the first photoresist pattern layer to form a recess pattern complementary to the first photoresist pattern layer in the metal carrier;
Plating metal in the groove pattern to form a first conductive circuit layer, the first conductive circuit layer is completely filled and protrudes from the groove pattern;
Removing the first photoresist pattern layer;
Pressing a dielectric layer on one side of the first conductive circuit layer, and embedding the first conductive circuit layer protruding from the metal carrier into the dielectric layer;
Forming a second conductive wiring layer on a side of the dielectric layer away from the first conductive wiring layer; and removing the metal carrier. The circuit board manufacturing method of claim 1, wherein the groove pattern is formed by chemically etching the metal carrier. The method of fabricating a circuit board according to claim 1, wherein the fabricating the second conductive circuit layer comprises the steps of:
Forming a blind hole in the dielectric layer;
Forming a plating seed layer on the inner wall of the blind hole and the surface of the dielectric layer;
Forming a second photoresist pattern on a surface of the plating seed layer;
A plating metal pattern is formed on the surface of the plating seed layer by electroplating; and the second photoresist pattern is removed. The method of fabricating a circuit board according to claim 1, wherein a second copper foil is further formed on the surface of the dielectric layer when the dielectric layer is pressed, and the forming the second conductive circuit layer comprises the steps of:
Forming a blind hole in the dielectric layer and the second copper foil;
Forming a plating seed layer on the inner wall of the blind hole and the surface of the second copper foil;
Forming a second photoresist pattern on a surface of the plating seed layer;
A plating metal pattern is formed on the surface of the plating seed layer by electroplating; and the second photoresist pattern is removed. The method of fabricating a circuit board according to claim 1, further comprising removing the plating seed layer and the second copper foil not covered by the plating metal. The circuit board manufacturing method of claim 1, wherein the first surface of the metal carrier is formed with a first copper foil, and the first photoresist pattern layer is formed on the first copper The surface of the foil, in forming the groove pattern, first etches away the first copper foil not covered by the first photoresist pattern layer. The method of fabricating a circuit board according to Item 1, wherein the material of the metal carrier is aluminum. A circuit board comprising a dielectric layer, a first conductive circuit layer and a second conductive circuit layer, the first conductive circuit layer and the second conductive circuit layer being formed on opposite sides of the dielectric layer, the first conductive The wiring layer is partially embedded in the dielectric layer, partially protruding from the dielectric layer, and the second conductive wiring layer is formed on a surface of the dielectric layer. The circuit board of claim 8, wherein the second conductive circuit layer is composed of a second copper foil, a plating seed layer and a plated metal, and the second copper foil is formed on a surface of the dielectric layer. The circuit board of claim 8, wherein the first conductive circuit layer and the second conductive circuit layer are electrically connected to each other through a conductive via hole.