TW201304098A - Wafer level chip scale package with wire-bonding connection and its fabricating process - Google Patents

Abstract

Primarily disclosed is a wafer level chip scale package with wire-bonding connection. A first encapsulating layer is formed on a passivation layer of a chip. A RDL (redistribution layer) is formed on the first encapsulating layer. A plurality of wire-bonded pads are disposed on the wiring terminals of the RDL. Each wire-bonded pad has an upper surface and a side. A surface plated layer completely covers the upper surfaces of the wire-bonded pads. A second encapsulating layer is formed on the first encapsulating layer to cover the RDL and the sides of the wire-bonded pads. The openings of the second encapsulating layer are smaller than the upper surfaces of the corresponding wire-bonded pads to partially expose the surface plated layer. Accordingly, it can solve conventional issue of chip crack when wire-bonding on thinned chip.

Description

Wafer-level wafer size package wire bonding structure and process thereof

The present invention relates to packaging techniques for semiconductor devices, and more particularly to a wire bonding structure for a wafer level wafer size package.

The conventional integrated circuit is fabricated in a semiconductor wafer. As the process progresses, the integrated circuit of more functions or larger capacity is accommodated in the wafer. At the same time, the thickness of the wafer is thinner and thinner, so the conventional wire is on the wafer. The action will easily lead to cracking of the wafer, which in turn will damage the integrated circuit.

In addition, the wafer level chip scale package (WLCSP) is a rapidly developing semiconductor packaging technology that completes the initial package size at the wafer stage, which not only reduces the package size, but also achieves low cost. demand. The key components in the wafer level wafer size package construction (WLCSP) are the reconfigured wiring layer (RDL), under bump metallurgy (UBM), and solder balls. The wafer-level wafer size package structure (WLCSP) is connected to the external board by Flip Chip bonding.

FIG. 1 illustrates a conventional wafer level wafer scale package structure 100 for flip chip bonding, comprising a wafer 110, an encapsulation layer 120, a relocation wiring layer 130, and a plurality of solder balls 170. The wafer 110 is provided with a plurality of pads 113 on the active surface on which the integrated circuit is formed and covered by at least one passivation layer 112. The reconfigurable circuit layer 130 is formed on the protective layer 112 and has a plurality of line ends 132 that are pad-shaped and away from the corresponding pads 113. The encapsulation layer 120 is formed on the protective layer 112 and covers the reconfiguration wiring layer 130 and has openings for exposing the line ends 132. A sub-bump metal layer 133 includes a plurality of shims that are aligned with the openings of the encapsulation layer 120 to connect the line ends 132. The solder balls 170 are bonded to the under bump metal layer 133 and partially encapsulate the solder balls 170 with a liquid or semi-cured adhesive layer 160 such as an underfill. It is known that the solder balls 170 are formed by forming bumps on the under bump metal layer 133 by electroplating, printing or ball bonding, and then forming them into a spherical shape by reflow, so the line ends 132 Will not withstand excessive ball stress. When the solder balls 170 are simply replaced by wire bonding pads, the bonding pressure of the wire bonding will easily cause cracking of the wafer 110. Especially when copper is wired or other solder wires that are harder than gold wires are used, the problem of wafer cracking will be more serious.

In view of this, the main object of the present invention is to provide a wire bonding structure for a wafer level wafer size package, which solves the problem that the conventional wire bonding causes the wafer to be broken when the wafer is thinned.

A second object of the present invention is to provide a wire bonding structure for a wafer level wafer size package to avoid the problem of exposed oxidation and electromigration of the wire bonding pads.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a wire bonding structure for a wafer level wafer size package, comprising a wafer, a first encapsulation layer, a reconfiguration circuit layer, a plurality of wire bonding pads, a surface plating layer and a second encapsulation layer. The wafer has a semiconductor substrate, a protective layer, and a plurality of pads. The first encapsulation layer is formed on the protection layer, and the first encapsulation layer has a plurality of first openings to expose the pads. The reconfiguration circuit layer is formed on the first encapsulation layer, the reconfiguration circuit layer has a plurality of first line ends extending into the first openings to connect the pads, the reconfiguration The circuit layer further has a plurality of second line ends connected to the corresponding first line ends and located on the first encapsulation layer. The wire mats are disposed on the second line ends, and each of the wire mats has an upper surface and a side surface. The surface coating completely covers the upper surface of the wire bonding pads. The second encapsulation layer is formed on the first encapsulation layer and covers the side of the reconfiguration circuit layer and the wire bonding pads. The second encapsulation layer has a plurality of alignments corresponding to the wire bonding pads. And a second opening that is smaller than the upper surface of the corresponding wire receiving pad to partially expose the surface plating.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the wire bonding structure of the wafer level wafer package described above, at least one wire bonding point may be further disposed on the surface plating layer.

In the wire bonding structure of the wafer level wafer size package, the wire bonding point may be one end of a bonding wire, and the other end of the bonding wire may be bonded to a substrate, and the chip is mounted on the substrate. .

In the wire bonding structure of the wafer level wafer size package, the wire bonding point may be a residual portion of a bonding wire and is a bump shape.

In the wire bonding structure of the wafer level wafer package described above, the second line ends may be larger than the wire bonding pads and have a protruding ring.

In the wire bonding structure of the wafer level wafer size package, the thickness of the second encapsulation layer may be greater than the thickness of the reconfiguration wiring layer, the sum of the average pad thickness of the wire bonding pads and the thickness of the surface plating layer. .

In the wire bonding structure of the wafer level wafer package, the thickness of the second encapsulation layer may be greater than the thickness of the protection layer, and the thickness of the first encapsulation layer may be greater than the thickness of the protection layer.

In the wire bonding structure of the wafer level wafer size package, the bottom of the reconfiguring circuit layer may be provided with a bump underlying metal layer attached to the first encapsulation layer.

It can be seen from the above technical solutions that the wire bonding structure of the wafer level wafer size package of the present invention has the following advantages and effects:

1. The problem of the wafer rupture caused by the conventional wire bonding when thinning the wafer can be solved by additionally providing the wire bonding pad on the reconfiguration circuit layer and sealing the two layers of the sealing layer.

2. The wire bonding pad on the reconfigurable circuit layer and the opening of the upper encapsulation layer are smaller than the wire bonding pad by the two layers of encapsulation layer, and the wire bonding pad has no exposed surface and the surface plating layer Only partial exposure is provided to avoid the problem of exposure oxidation and electromigration outside the wire bond pad.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a wire bonding structure 200 of a wafer level wafer size package is illustrated in a cross-sectional view of FIG. 2 and a partial enlarged view of FIG. The wire bonding structure 200 of the wafer level wafer package comprises a wafer 210, a first encapsulation layer 220, a re-distribution circuit layer 230, a plurality of wire bonding pads 240, a surface plating layer 250, and a second encapsulation layer 260.

As shown in FIGS. 2 and 3, the wafer 210 has a semiconductor base layer 211, at least one protective layer 212, and a plurality of pads 213. The active surface of the wafer 210 can be formed with various integrated circuits and covered by the protective layer 212, and the pads 213 serve as external contacts of the integrated circuit. In this embodiment, the pads 213 are central pads. In addition, the wafer 210 has a thickened protective layer 214 having a thickness greater than that of the protective layer 212, and is disposed between the protective layer 212 and the first encapsulation layer 220 to improve the total of the protective layer. thickness. The protective layer 212 and the thickened protective layer 214 do not completely cover the pads 213.

The first encapsulation layer 220 is formed on the protection layer 212. The first encapsulation layer 220 has a plurality of first openings 221 to expose the pads 213. The first encapsulation layer 220 is electrically insulating, for example, a polyimide. Generally, the thickness of the first encapsulation layer 220 is greater than the thickness of the protective layer 212, and may be greater than the thickness of the thickened protective layer 214. .

The reconfiguration circuit layer 230 is formed on the first encapsulation layer 220. The reconfiguration circuit layer 230 includes a plurality of lines formed at the wafer level, and the material thereof may be copper or other conductive metal. The reconfiguration circuit layer 230 has a plurality of first line ends 231 extending into the first openings 221 to connect the pads 213. The reconfiguration circuit layer 230 has a plurality of second lines. The end 232 is connected to the corresponding first line end 231 and located on the first encapsulation layer 220. The second line ends 232 may be in the shape of a spacer and away from the pads 213 , but are electrically connected to the corresponding pads 213 via the first line ends 231 . In this embodiment, the second line ends 232 are disposed in a peripheral configuration and are located around the active surface of the wafer 210. More specifically, the bottom of the reconfiguration circuit layer 230 may be provided with a sub-bump metal layer 233 attached to the first encapsulation layer 220 to form a seed layer of the re-distribution circuit layer 230 as electroplating. The under bump metal layer 233 can be formed by a vapor deposition method of an integrated circuit process, and can be a thin gold layer or a thin copper layer.

The wire ferrules 240 are disposed on the second wire ends 232. Each wire ferrule 240 has an upper surface 241 and a side surface 242. It is noted that the wire ferrules 240 are not part of the reconfiguration circuit layer 230, but are additional pads disposed above the reconfiguration circuit layer 230 for withstanding the wire bonding force. The wire ferrules 240 should be made of a rigid material such as copper, and the pad thicknesses of the wire ferrules 240 are preferably greater than the thickness of the wire of the reconfiguration circuit layer 230. In addition, the wire bonding pads 240 are not directly disposed on the protective layer 212. The second wire ends 232 of the reconfigurable circuit layer 230 are still between the wire bonding pads 240 and the protective layer 212. An encapsulation layer 220 can avoid direct wire impact on the wafer 210 and its semiconductor base layer 211. Preferably, the second line ends 232 are larger than the wire receiving pads 240 and have a protruding ring, that is, the side surfaces 242 of the wire receiving pads 240 are removed, so that the wire receiving pads 240 do not completely cover the wires. The second line end 232 is effective to receive the wire ferrules 240, and retains the advantage that the reconfiguration circuit layer 230 and the second encapsulation layer 260 are better (as shown in FIG. 3).

The surface plating layer 250 completely covers the upper surface 241 of the wire bonding pads 240 to prevent oxidation of the surface of the wire bonding pads 240 and to facilitate wire bonding. The material of the surface plating layer 250 may be nickel gold or gold, and the thickness of the surface plating layer 250 should be smaller than the thickness of the pad of the wire bonding pads 240.

The second encapsulation layer 260 is formed on the first encapsulation layer 220 and covers the rewiring circuit layer 230 and the side surface 242 of the wire bonding pads 240. The second encapsulation layer 260 has a plurality of alignments. The second openings 261 of the wire receiving pads 240 are smaller than the upper surface 241 of the corresponding wire receiving pads 240 to partially expose the surface plating layer 250. The material of the second encapsulation layer 260 may be the same as the first encapsulation layer 220, such as polyimide. The thickness of the second encapsulation layer 260 can be greater than the thickness of the reconfiguration wiring layer 230, the sum of the average pad thickness of the wire bonding pads 240 and the thickness of the surface plating layer 250. Preferably, the thickness of the second encapsulation layer 260 can be greater than the thickness of the protection layer 212, and the thickness of the first encapsulation layer 220 can be greater than the thickness of the protection layer 212 to strengthen the bonding pads 240. Seal protection effect.

Therefore, the wire bonding pads 240 are sealed between the first encapsulation layer 220 and the second encapsulation layer 260, and have no directly exposed surface, which solves the problem that the conventional wire bonding causes the wafer to be broken when the wafer is thinned. . Moreover, the wire bonding pads 240 are defined by the second openings 261 of the second encapsulation layer 260. The periphery of the wire bonding pads 240 has an overlapping area with the second encapsulation layer 260. The periphery of the plating layer 250 is covered by the second encapsulating layer 260. The surface plating layer 250 does not have an edge peeled outward by the second encapsulating layer 260. This structure prevents the metal components of the wire bonding pads 240 from being electrically generated. The migration problem can increase the line layout space of the reconfiguration line layer 230 and reduce the pad spacing of the wire pads 240.

In addition, the wire bonding structure 200 of the wafer level wafer size package may further include at least one wire bonding pad 270 disposed on the surface plating layer 250. The wire bond 270 is a ball bond formed by wire bonding, rather than a solder ball formed by reflow. In this embodiment, the wire bonding pad 270 can be a residual portion of a bonding wire and has a convex shape.

4A to 4J illustrate the manufacturing process of the wire bonding structure 200 of the wafer level wafer size package. First, as shown in FIG. 4A, the wafer 210 is provided. In this step, the wafer 210 is uncut and formed in a wafer. The pads 213 of the wafer 210 are disposed on the active surface of the wafer and the protective layer 212 and the thickened protective layer 214 are formed on the active surface of the wafer. The wafer can be back-grinded such that the wafer 210 has a thickness below 10 mils and can even reach about 6 mils. Then, as shown in FIG. 4B, the first encapsulation layer 220 is formed on the protective layer by liquid coating or tape bonding, such as printing or spin coating, and the first encapsulation layer 220 is formed by exposure development or etching. The first openings 221 are formed to expose the pads 213. Then, as shown in FIG. 4C, the under bump metal layer 233 is formed on the first encapsulation layer 220 by a vapor deposition method. In this step, the under bump metal layer 233 completely covers the first package. Layer 220. Then, as shown in FIG. 4D, a first photoresist layer 410 may be formed on the under bump metal layer 233 by printing or dry film bonding; and the first photoresist layer 410 may be made specific by exposure and development. An opening of the pattern is patterned to expose a region of the under bump metal layer 233 where the reconfigured wiring layer is to be formed. Then, as shown in FIG. 4E, the under-bump metal layer 233 is used as a seed layer, and the re-arranged wiring layer 230 having a large thickness is formed in a specific pattern opening of the first photoresist layer 410 by electroplating. Provided on the under bump metal layer 233 above the first encapsulation layer 220 and having a predetermined line pattern, the reconfiguration circuit layer 230 having the first line ends 231 and the Two line ends 232. Next, as shown in FIG. 4F, a second photoresist layer 420 is formed on the first photoresist layer 410 without removing the first photoresist layer 410; and the first photoresist layer 410 is formed by exposure and development. The two photoresist layers 420 are openings of a specific pattern to pattern the regions of the second line ends 232 that are intended to form the wire bonding pads. Then, as shown in FIG. 4G, the sub-bump metal layer 233 can be shared as a seed layer via the re-arrangement line layer 230 electrically connected to the under bump metal layer 233, and the electroplating is further formed. A wire bonding pad 240 is formed on the second line ends 232, and the surface plating layer 250 is formed on the upper surface 241 of the wire bonding pads 240. Then, as shown in FIG. 4H, the second photoresist layer 420 and the first photoresist layer 410 are simultaneously removed in a photoresist removal manner to expose the under bump metal layer 233, the relocation wiring layer 230, The side surfaces 242 of the wire bonding pads 240 and the surface plating layer 250. Thereafter, as shown in FIG. 4I, the under bump metal layer 233 is removed by etching to not cover the exposed region by the reconfigurable wiring layer 230; in this step, even the metal material of the under bump metal layer 233 is The metal material of the re-distribution circuit layer 230 is the same, for example, copper, but the thickness of the under-metal layer 233 is much smaller than the thickness of the re-distribution circuit layer 230, and can be moved under the control of appropriate etching temperature and time. Except for the exposed area of the under bump metal layer 233, most of the structure of the reconfigured wiring layer 230 remains. Then, as the first encapsulation layer 220 is formed, the second encapsulation layer 260 is formed on the first encapsulation layer 220 to cover the reconfigurable circuit layer 230 and the side surface 242 of the wire bonding pads 240, and The second encapsulation layer 260 has a plurality of second openings 261 aligned with the wire bonding pads 240. The second openings 261 are smaller than the upper surface 241 of the corresponding wire bonding pads 240. The surface coating 250 is partially exposed. As shown in FIG. 2, at least one of the wire bonding points 270 formed by the wire bonding can be disposed on the surface plating layer 250. Therefore, the wafer level wafer size packaging process of the present invention can meet the high product reliability and low process cost of the wire bonding structure.

In accordance with a second embodiment of the present invention, another wire bonding structure 300 of a wafer level wafer size package is illustrated in cross-section of FIG. The wire bonding structure 300 of the wafer level wafer size package will have the same reference numerals as the components of the first embodiment, and the same detailed functions and connections will not be described again. The wire bonding structure 300 of the wafer level wafer package includes a wafer 210, a first encapsulation layer 220, a relocation wiring layer 230, a plurality of wire bonding pads 240, a surface plating layer 250, and a second encapsulation layer 260. The first encapsulation layer 220 is formed on the protection layer 212. The first encapsulation layer 220 has a plurality of first openings 221 to expose the pads 213. The reconfiguration circuit layer 230 is formed on the first encapsulation layer 220. The reconfiguration circuit layer 230 has a plurality of first line ends 231 extending into the first openings 221 to connect the solder lines. The pad 213 has a plurality of second line ends 232 connected to the corresponding first line ends 231 and located on the first encapsulation layer 220. The wire ferrules 240 are disposed on the second line ends 232. The surface plating layer 250 completely covers the upper surface of the wire bonding pads 240. The second encapsulation layer 260 is formed on the first encapsulation layer 220 and covers the side of the re-wiring circuit layer 230 and the wire bonding pads 240. The second encapsulation layer 260 has a plurality of alignment lines. The second opening 261 of the pad 240 is smaller than the upper surface 241 of the corresponding wire receiving pad 240 to partially expose the surface plating layer 250.

The wire bonding structure 300 of the wafer level wafer size package may further include at least one wire bonding pad 270 disposed on the surface plating layer 250. In this embodiment, the wire bonding point 270 can be one end of a complete bonding wire 371, and the other end of the bonding wire 371 can be bonded to a plurality of fingers 381 of a substrate 380, and the wafer 210 can be borrowed. A die layer 390 is disposed on the substrate 380. In the embodiment, the die layer 390 adheres the back surface of the wafer 210 to the surface of the substrate 380. The substrate 380 can be a printed circuit board.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100. . . Wafer level wafer size package construction

110. . . Wafer

112. . . The protective layer

113. . . Solder pad

120. . . Encapsulation layer

130. . . Reconfigure the line layer

132. . . Line end

133. . . Under bump metal layer

160. . . Adhesive layer

170. . . Solder ball

200. . . Wafer-level wafer size package wire bonding structure

210. . . Wafer

211. . . Semiconductor substrate

212. . . The protective layer

213. . . Solder pad

214. . . Thickened protective layer

220. . . First encapsulation layer

221. . . First opening

230. . . Reconfigure the line layer

231. . . First line end

232. . . Second line end

233. . . Under bump metal layer

240. . . Line mat

241. . . Upper surface

242. . . side

250. . . Surface coating

260. . . Second encapsulation layer

261. . . Second opening

270. . . Wire solder joint

300. . . Wafer-level wafer size package wire bonding structure

371. . . Welding wire

380. . . Substrate

381. . . Finger

390. . . Binder layer

410. . . First photoresist layer

420. . . Second photoresist layer

Figure 1: Schematic cross-sectional view of a conventional wafer level wafer size package structure.

2 is a cross-sectional view showing a wire bonding structure of a wafer level wafer size package in accordance with a first embodiment of the present invention.

Fig. 3 is a partially enlarged view showing the wire bonding structure of the wafer level wafer size package in Fig. 2.

4A to 4J are cross-sectional views showing the wire bonding structure of the wafer level wafer size package in the process according to the first embodiment of the present invention.

Figure 5 is a cross-sectional view showing a wire bonding structure of a wafer level wafer size package in accordance with a second embodiment of the present invention.

200. . . Wafer-level wafer size package wire bonding structure

210. . . Wafer

211. . . Semiconductor substrate

212. . . The protective layer

213. . . Solder pad

214. . . Thickened protective layer

220. . . First encapsulation layer

221. . . First opening

230. . . Reconfigure the line layer

231. . . First line end

232. . . Second line end

233. . . Under bump metal layer

240. . . Line mat

250. . . Surface coating

260. . . Second encapsulation layer

261. . . Second opening

270. . . Wire solder joint

Claims (10)

A wire bonding structure for a wafer level wafer size package, comprising: a wafer having a semiconductor base layer, a protective layer and a plurality of pads; a first encapsulation layer formed on the protective layer, the first encapsulation layer a plurality of first openings for exposing the pads; a reconfigurable circuit layer formed on the first encapsulation layer, the reconfiguration circuit layer having a plurality of first line ends extending to the The first opening is connected to the pads, the reconfiguration circuit layer further has a plurality of second line ends connected to the corresponding first line end and located on the first encapsulation layer; the plurality of wire bonding pads Provided on the second line ends, each of the wire mats has an upper surface and a side surface; a surface plating layer completely covering the upper surface of the wire bonding pads; and a second encapsulating layer, Formed on the first encapsulation layer and covering the reconfigured circuit layer and the side of the wire bonding pads, the second encapsulation layer having a plurality of second openings aligned with the wire bonding pads, The second opening is smaller than the pair Wire rim of the upper surface to expose the partial surface coating. According to the wire bonding structure of the wafer level wafer size package of claim 1, the method further comprises at least one wire bonding point disposed on the surface plating layer. The wire bonding structure of the wafer level wafer size package according to claim 2, wherein the wire bonding point is one end of a bonding wire, and the other end of the bonding wire is bonded to a substrate, and the chip is attached to the substrate On the substrate. The wire bonding structure of the wafer level wafer size package according to claim 2, wherein the wire bonding point is a residual portion of a bonding wire and is in a bump shape. The wire bonding structure of the wafer level wafer size package according to claim 1, 2, 3 or 4, wherein the second line ends are larger than the wire bonding pads and have a protruding ring. The wire bonding structure of the wafer level wafer size package according to claim 1, 2, 3 or 4, wherein the thickness of the second encapsulation layer is greater than the thickness of the reconfiguration circuit layer, and the average of the wire bonding pads The sum of the thickness of the pad and the thickness of the surface coating. The wire bonding structure of the wafer level wafer size package according to claim 1, 2, 3 or 4, wherein the thickness of the second encapsulation layer is greater than the thickness of the protective layer, and the thickness of the first encapsulation layer is Greater than the thickness of the protective layer. The wire bonding structure of the wafer level wafer size package according to claim 1, 2, 3 or 4, wherein the bottom of the reconfigurable circuit layer is provided with a metal under bump attached to the first encapsulation layer . A wafer level wafer size packaging process comprising the steps of: providing a wafer formed in a wafer having a semiconductor substrate, a protective layer and a plurality of pads; forming a first package layer for the protection Laying the first encapsulation layer with a plurality of first openings to expose the pads; forming a bump underlying metal layer on the first encapsulation layer; forming a patterned first photoresist layer thereon Forming a re-distribution circuit layer in the first photoresist layer by electroplating, which is disposed on the under bump metal layer above the first encapsulation layer, the under bump metal layer The system has a plurality of first line ends and a plurality of second line ends, the first line ends extending into the first openings to connect the pads, and the second line ends are connected to the corresponding a line end is located on the first encapsulation layer; in a state where the first photoresist layer is not removed, a patterned second photoresist layer is formed on the first photoresist layer to pattern the exposed portions Second line end; forming a plurality of wire-bonding lines by electroplating Forming a surface plating on the upper surface of the wire bonding pads on the second line ends; simultaneously removing the second photoresist layer and the first photoresist layer; and removing the under bump metal by etching The layer is not covered by the reconfigured circuit layer; and a second encapsulation layer is formed on the first encapsulation layer to cover the reconfigured circuit layer and the side of the wire bonding pads, and the second encapsulation layer And having a plurality of second openings aligned with the wire receiving pads, the second openings being smaller than the upper surface of the corresponding wire receiving pads to partially expose the surface plating. According to the wafer level wafer size packaging process of claim 9 of the patent application, the method further comprises the steps of: setting at least one wire bonding spot formed by wire bonding on the surface plating layer.