201135390六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於一種線性穩壓電路，特別是指一種 可4貞測一輸入電壓，藉此可調整並獲得一穩定之輸出電 壓的線性穩壓電路。 [0002] 〇 [0003]201135390 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a linear regulator circuit, and more particularly to an input voltage that can be adjusted to obtain a stable output voltage. Linear regulator circuit. [0002] 〇 [0003]
[0004] 099110679 【先前技術J 通訊和電子技術不斷發展’使得電子產品逐漸縮小 其體積並追求更精密的操作，而這些電子產品，例如手 機、相機等均需要較高的電源斥拒比（p〇Wei· supply rejection ratio ’ 簡稱PSRR)，以達到低雜訊（i〇w noise)以及低漣波（ripple)的供電，因而内部皆設置穩 定電壓之裝置’如穩壓器（voltage regulat〇r)，以提 供該些精密電子產品一穩定的供應電;1 ^ 圖1顯示習用技藝中所使用的一低壓降（1〇w dr〇_ pout ’簡稱LD0)穩壓電路1 ’包括一輪入電壓v ，為一直流訊號’因常伴隨連波（ripple)及雜訊（n〇ise)等干 擾源，致使輸出狀態不穩定’故利用該Ld〇穩壓電路1抑 制該等干擾源’以獲取一穩定之輸出電壓V 。 out 該LD0穩壓電路1包含一功率電晶體1〇，該功率電晶 體10之源極（source)係連接於該輸入電愿v ，其波極 ( =輸出電壓電f生相連 ’該功率電晶體10 之閘極（gate)並串聯至一誤差放大amplifi_ er) 11之輸出端。該誤差放大器丨丨之反相輸入接受一由 參考電路12而來之參考訊號\ ;而該輪出之 經 out 電阻S、I?2分壓後之一回授訊號Vf，並回授至該誤差放 表單編號 A〇m ^ 3 I/* 15 I 0992018786-0 201135390 大器11的同相輸入端。 [0005] [0006] [0007] [0008] 上述誤差放大器11係用於比較回授訊號乂|與該參考 電壓訊號V間之差異，並補償（compensate)—誤差電壓 r (error vo 11age)至該功率電晶體10，作調整該輸出電 壓V 準位之用。 out 受到輸出電壓V +回授時間之牽制，使該LD0穩壓電 out 路1無法即時反應。具體而言，該輸出電壓V +的變化 係透過回授，反應至誤差放大器11的同相輸入端，再經 由該誤差放大器11處理後輸出，補償至功率電晶體10的 閘極。因此，為迴路所限制，而無法快速反應並補償輸 入電壓V.的雜訊或是漣波。此外，輸出電壓V +的穩定 1 n out 度除了受到輸入電壓V.雜訊和漣波影響，亦與參考電壓 in 訊號v相關。 r 【發明内容】 本發明之一目的在於提供一種線性穩壓電路，可增 強低壓降穩壓電路抗雜訊（η 〇 i s e)之能力及電源斥拒比 (Power Supply Rejection Ratio，簡稱PSRR)，並 快速反應輸入電壓的變化，以提供負載電路穩定的電源 供應。 本發明之另一目的在於提供一種線性穩壓電路，所 增之升降電路以切換模式控制，並進行適度的補償， 因此不影響線性穩壓電路的穩定性。 根據本發明之線性穩壓電路的一實施例，其包括 :一功率電晶體，其源極輸入一輸入電壓，而其汲極則 099110679 表單編號A0101 第4頁/共15頁 0992018786-0 [0009] 201135390 輸出一輸出電壓；一誤差放大器之輸出端與該功率電晶 體之閘極形成串聯，藉以控制該功率電晶體之閘極電壓 ，來調整該輸出電壓，並同時偵測該輸出電壓變化；以 及一升降電路包括一升廢單元、一降屋單元、一第一切 換器以及一第二切換器；該升降電路以該輸入電壓變化 轉換為一電流型式，藉以電流型式來控制該第一切換器 或該第二切換器的開啟，使該功率電晶體之閘極電壓改 變，藉以獲致穩態之輸出電壓者。 【實施方式】 [0010] 有關本發明之前述目的及其他技術内容，特點與功 效，在以下配合參考圖式之實施方式的詳細說明中，將 可清楚了解。 [0011] 請參閱圖2，為本發明之線性穩壓電路一實施例示意 圖。本發明之線性穩壓電路2包括一功率電晶體20、一誤 差放大器21、以及一升降電路3。該功率電晶體20源極與 一輸入電壓V.相連，其汲極則連接一輸出電壓V +。該 in out 輸出電壓V^t經電阻\，R2分壓回授後，形成一回授訊 號Vf，連接於該誤差放大器21之同相輸入，而以一參考 電壓作為其反相輸入，其中該參考電壓可由輸入電 壓V.輸入至一參考電路22而產生。如圖2之實施例所顯 1 η 示，該功率電晶體20可為一Ρ型電晶體，但實務上亦可使 用Ν型電晶體，並不以此為限。 [0012] 本發明之升降電路3包含一升壓單元30、一降壓單元 31、一第一切換器32以及一第二切換器33。該第一切換 器32—端連接輸入電壓V.，另一端則與該第二切換器33 in 099110679 表單編號 A0101 第 5 頁/共 15 頁 0992018786-0 201135390 =串聯’兩切換器32, 33連接處並電性連接至該功率 :體20之閘極’藉以選擇拉升或降低功率電晶體別的 間極《，而抑·出電壓匕之上升或下降，達到穩壓 之目的。 [0013] [0014] “輪入電壓Vin分別作為升壓單元30以及降壓單元31 之輸入，||升壓單元3()細—㈣訊號'μ控制降壓單 兀31之開關。而該第"切換器32以及該第二切換器33分 別以升壓單元3G以及降壓單元31之輸出，包括—升壓訊 號νΡϋ以及一降壓訊號VpD，作為開關控制：當第一切換器 32連通時，將提升該功率電晶體20之閘極電壓，因此抑 制輸出电壓V〇ut之繼續上升；而當第土切換器33連通時 ，5玄功率電晶體2〇之閘極電壓將下降，因此抑制輸出電 壓vout之繼續下降。 如圖3所示’其顯示本發明升降電路之一實施例。該 升Μ單元30包含一阻抗電晶體30〇、複數個電阻Rsq， R31’ R32以及一升壓延遲單元301。如圖3之實施例所顯 示’該阻抗電晶體300可為一p型電晶體，但並不以此為 限。該阻抗電晶體300的源極連接輸入電壓v ，其汲極 in 與該些電阻R3()，R31，r32形成電性串聯，其閘極則電性 連接至電阻R3l，R32之連接處，形成一二極體等效阻抗 。輸入電壓Vin經阻抗電晶體300後輸出一分壓訊號VD， 並於電阻1?3&，R31之連接處輸出控制訊號。該二極 體等效阻抗之功用係於輸入電壓V.上升或下降時，同時 in 牵引該分壓訊號乂^與該控制訊號v 4之上升或下降。而 y Ctrl 該些電阻r3Q，R3l，R32係用以決定分壓訊號VD#及控制 099110679 表單編號A0101 第6頁/共15頁 0992018786-0 201135390 訊號Vctrl的電壓準位，於實施上並不以電阻為限，亦可 使用二極體或是其他功能相等的電子元件，而形成適當 的電壓準位偏移（level shift)。 [0015] Ο 〇 [0016] 如圖3之實施例，該第一切換器可為一 p型電晶體32〇 ，但不以此為限。該分壓訊號、藉由升壓延遲單元3〇1延 遲，產生升壓訊號Vpu，並作為該p型電晶體32〇閘極之控 制，P型電晶體320的源極則連接輸入電壓v 。因此當輸 入電壓Vin持續上升，該p型電晶體32〇之源極電壓將隨之 增加，而閘極電壓（即為νρϋ)因為受到升壓延遲單元301 之延遲抑制，因此無法瞬時增加，造成該ρ型電晶體32〇 之源閘極電壓差（表示為變大。是故，ρ型電晶體32〇 將導通，輸入電壓Vin經導通之ρ型電晶體320將補償至功 率電晶體20(顯示於圖2)之閘極，因此抑制輸出電壓v out 隨輸入電壓Vin上升。反之，當輸入電壓Vin持續下降時， s玄P型電晶體320將無法導通，輸出電壓'Μ將維持不變 〇 該降壓單元31包含一電流啟動單元31〇、一鏡射 (mirror)單元311以及一降壓延遲單元312 β如圖3之實 施例所顯示，該電流啟動單元31〇可為一ρ型電晶體，該 鏡射單元311可為-Ν型電晶體，而該第二切換器可為一Ν 型電晶體330，但並不以所舉例者為限。該輸入電壓ν 經降壓延遲單元312後與電流啟動單元3丨〇之源極電性相 連，而電流啟動單元310之閘極則以該控制訊號¥ 所 ctrl 工!如圖3所顯示，當輸入電塵ν。持續下降時，該控 制電壓Vetrl將隨之下降，然該钱啟料元31〇之源極 099110679 表單編號A0101 第7頁/共15頁 0992018786-0 201135390 電屋’因受到降Μ延遲單训2的延遲㈣，因此無法瞬 時下降’造成該電流啟動單元31〇之源閘極電壓差（表示 為變大，因此電流啟動單元310將開啟，並透過該鏡 | °…丨1將電壓變化轉換為m彡式，且依比例關係鏡 射該電流至該W電晶體33()，於該N型電晶體咖之閉極 成所揭的降壓5fl號、。反之，如輪人電壓'η持續升高 ' 说V Ctrl 將隨之持續上升，無法順利開啟電 流啟動單元31G，該降鮮灿將無法作用。 [0017] [0018] 則揭之升壓延遲單元301以及降壓延遲單元312可選 自一 RC濾波器（RC fiHer)或一緩衝器，藉以 延遲輸人電·，分壓訊號、輸人之時間，但並不以所 舉例者為限》 综上所述，本發明以升壓電路3〇以及降壓電路31分 別產生升壓訊號VPU以及降壓訊號VPD。於輸入電壓Vin持 續上升的情況下，㈣升壓訊號VP#·—切換器之 控制，俾使功率電晶體20之閘極電屋拉升，而抑制輸出 電壓V〇ut隨輪入電壓升高。於輸入電壓'η持續下降的 情況下’以降屋訊號VPD作為第二切換器33之控制，俾使 該功率電晶體20之閘極電壓降低’以抑制該輸出電壓 Vout隨輸人電麗'η繼續下降。本發明之線性穩壓電路2藉 -前饋路徑(feed-i〇rward path)方式而掌控反應時間 ，致使该升降電路3達到對雜訊反應速度快於回授電路的 反應速度；且該升降電路3利用虛擬開關之切換方式控制 補償電流，達到快速地抑制輸出電壓v〇m的變化，進而不 影響回授電路’有效增加對系統的穩定度。 099110679 表單編號A0101 第8頁/共15頁 0992018786-0 201135390 [0019] 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 [0020] 為使本發明之上述及其他目的、特徵，優點與實施 例得以容易瞭解，所述圖式之詳細說明如下： [0021] 圖1顯示習用技藝中所使用的一低壓降穩壓電路；[0004] 099110679 [Previous technology J communication and electronic technology is constantly evolving] to make electronic products gradually shrink their size and pursue more sophisticated operations, and these electronic products, such as mobile phones, cameras, etc., require a higher power rejection ratio (p 〇Wei·supply rejection ratio 'PSRR), in order to achieve low noise (i〇w noise) and low ripple power supply, so the device is internally set to stabilize voltage 'such as voltage regulator (voltage regulat〇r ) to provide a stable supply of the precision electronic products; 1 ^ Figure 1 shows a low voltage drop (1〇w dr〇_ pout 'abbreviated as LD0) voltage regulator circuit 1 ' used in the conventional technology, including a wheel-in voltage v, is the constant stream signal 'caused by the interference source such as ripple and noise, causing the output state to be unstable. Therefore, the Ld〇 voltage regulator circuit 1 is used to suppress the interference sources to obtain A stable output voltage V. The LD0 voltage stabilizing circuit 1 includes a power transistor 1 〇, the source of the power transistor 10 is connected to the input power v, and its wave (= output voltage is electrically connected to the power) The gate of crystal 10 is connected in series to the output of an error amplifier amplifi_ er) 11. The inverting input of the error amplifier 接受 receives a reference signal from the reference circuit 12; and the rounded output of the out-of-resistance S, I?2 is returned to the signal Vf, and is fed back to the The error is placed on the form number A〇m ^ 3 I/* 15 I 0992018786-0 201135390 The non-inverting input of the amplifier 11. [0008] [0008] [0008] The error amplifier 11 is used to compare the difference between the feedback signal 乂| and the reference voltage signal V, and compensate - error voltage r (error vo 11age) to The power transistor 10 is used to adjust the output voltage V level. Out is pinned by the output voltage V + feedback time, so that the LD0 regulated current out channel 1 cannot react immediately. Specifically, the change of the output voltage V + is reflected to the non-inverting input terminal of the error amplifier 11 through the feedback, and then outputted by the error amplifier 11 to be output to compensate the gate of the power transistor 10. Therefore, it is limited by the loop, and it is impossible to quickly react and compensate for the noise or chopping of the input voltage V. In addition, the stable 1 n out degree of the output voltage V + is affected by the input voltage V. noise and chopping, and also with the reference voltage in signal v. r [ SUMMARY OF THE INVENTION] It is an object of the present invention to provide a linear voltage stabilizing circuit capable of enhancing the anti-noise (η 〇 ) capability and the power supply rejection ratio (PSRR) of a low-dropout voltage stabilizing circuit. And quickly react to changes in the input voltage to provide a stable power supply to the load circuit. Another object of the present invention is to provide a linear voltage stabilizing circuit which is controlled in a switching mode and moderately compensated, so that the stability of the linear voltage stabilizing circuit is not affected. An embodiment of the linear voltage stabilizing circuit according to the present invention comprises: a power transistor having a source inputting an input voltage and a drain of 099110679 Form No. A0101 Page 4 / Total 15 Page 0992018786-0 [0009 ] 201135390 outputs an output voltage; an output of the error amplifier is connected in series with the gate of the power transistor to control the gate voltage of the power transistor to adjust the output voltage and simultaneously detect the output voltage change; And a lifting circuit comprising a lifting unit, a downsizing unit, a first switch and a second switch; the lifting circuit is converted into a current type by the input voltage change, and the current switching is used to control the first switching The opening of the second switch or the second switch causes the gate voltage of the power transistor to change, thereby obtaining a steady-state output voltage. The above and other technical contents, features and effects of the present invention will become apparent from the following detailed description of the embodiments of the invention. Please refer to FIG. 2, which is a schematic diagram of an embodiment of a linear voltage stabilizing circuit of the present invention. The linear regulator circuit 2 of the present invention comprises a power transistor 20, an error amplifier 21, and a rise and fall circuit 3. The source of the power transistor 20 is connected to an input voltage V., and the drain is connected to an output voltage V + . The in out output voltage V^t is converted by the resistance \, R2, and a feedback signal Vf is formed, which is connected to the non-inverting input of the error amplifier 21, and uses a reference voltage as its inverting input, wherein the reference The voltage can be generated by inputting an input voltage V. to a reference circuit 22. As shown in the embodiment of FIG. 2, the power transistor 20 can be a Ρ-type transistor, but a Ν-type transistor can also be used in practice, and is not limited thereto. [0012] The rise and fall circuit 3 of the present invention includes a boosting unit 30, a step-down unit 31, a first switch 32, and a second switch 33. The first switch 32 is connected to the input voltage V., and the other end is connected to the second switch 33 in 099110679 Form No. A0101 Page 5 / 15 Page 0992018786-0 201135390 = In-line 'Two Switchers 32, 33 Connection It is electrically connected to the power: the gate of the body 20 'by selecting to pull up or lower the other poles of the power transistor, and suppressing the rise or fall of the voltage , to achieve the purpose of voltage regulation. [0014] "The turn-in voltage Vin is used as the input of the boosting unit 30 and the step-down unit 31, respectively, || boosting unit 3 () is fine - (four) signal 'μ controls the switch of the step-down unit 31. The "switch" 32 and the second switch 33 are respectively outputted by the boosting unit 3G and the step-down unit 31, including a -boost signal νΡϋ and a step-down signal VpD as switch control: when the first switch 32 When connected, the gate voltage of the power transistor 20 will be raised, thereby suppressing the output voltage V〇ut from continuing to rise; and when the earth switch 33 is connected, the gate voltage of the 5th power transistor will decrease. Therefore, the output voltage vout is continuously decreased. As shown in Fig. 3, it shows an embodiment of the lifting circuit of the present invention. The lifting unit 30 includes an impedance transistor 30A, a plurality of resistors Rsq, R31' R32 and one liter. The voltage delay unit 301. As shown in the embodiment of FIG. 3, the impedance transistor 300 can be a p-type transistor, but is not limited thereto. The source of the impedance transistor 300 is connected to the input voltage v. The pole in and the resistors R3 (), R31, r32 form an electrical string The gate is electrically connected to the junction of the resistors R31 and R32 to form a diode equivalent impedance. The input voltage Vin passes through the impedance transistor 300 and outputs a voltage dividing signal VD, and the resistor 1?3& The connection of R31 outputs a control signal. The function of the equivalent impedance of the diode is when the input voltage V. rises or falls, and at the same time, the voltage-divided signal 牵引^ and the control signal v 4 rise or fall. Ctrl These resistors r3Q, R3l, R32 are used to determine the voltage division signal VD# and control 099110679 Form No. A0101 Page 6 / Total 15 Page 0992018786-0 201135390 The voltage level of the signal Vctrl is not implemented by the resistor. Alternatively, a diode or other functionally equivalent electronic component can be used to form an appropriate voltage shift. [0015] 00 〇 [0016] As in the embodiment of FIG. 3, the first switching The device can be a p-type transistor 32 〇, but not limited thereto. The voltage dividing signal is delayed by the boost delay unit 3〇1 to generate a boost signal Vpu, and is used as the p-type transistor 32. For the ultimate control, the source of the P-type transistor 320 is connected to the input voltage v. Therefore, when the input voltage Vin continues to rise, the source voltage of the p-type transistor 32〇 will increase, and the gate voltage (ie, νρϋ) is suppressed by the delay of the boost delay unit 301, so that it cannot be instantaneously increased, resulting in The source gate voltage difference of the p-type transistor 32〇 is expressed as being large. Therefore, the p-type transistor 32〇 will be turned on, and the input voltage Vin is turned on by the p-type transistor 320 to compensate the power transistor 20 ( The gate shown in Figure 2) is shown, so that the output voltage v out is suppressed from rising with the input voltage Vin. On the contrary, when the input voltage Vin continues to drop, the s-P-type transistor 320 will not be turned on, and the output voltage 'Μ will remain unchanged. The buck unit 31 includes a current-starting unit 31〇 and a mirror unit. 311 and a buck delay unit 312 β as shown in the embodiment of FIG. 3, the current starting unit 31 can be a p-type transistor, the mirror unit 311 can be a -Ν type transistor, and the second switching The device may be a 电-type transistor 330, but is not limited to the examples. The input voltage ν is electrically connected to the source of the current starting unit 3 经 via the step-down delay unit 312 , and the gate of the current starting unit 310 is ctrl by the control signal ¥ as shown in FIG. 3 . Enter the electric dust ν. When the voltage drops continuously, the control voltage Vetrl will drop accordingly, but the source of the money source 31〇099110679 Form No. A0101 Page 7 / Total 15 Page 0992018786-0 201135390 Electric house 'send single training due to hail delay 2 The delay (4), so it cannot be instantaneously dropped 'causes the source gate voltage difference of the current starting unit 31〇 (indicated to become large, so the current starting unit 310 will be turned on, and the voltage change is converted into the through the mirror | °...丨1 m彡, and according to the proportional relationship, the current is mirrored to the W transistor 33(), and the N-type transistor is closed to the depressed 5fl number. Conversely, if the wheel voltage 'η continues Raise 'said V Ctrl will continue to rise, unable to smoothly turn on the current starting unit 31G, the fresh-keeping can not work. [0018] The boost delay unit 301 and the step-down delay unit 312 are optional. From an RC filter (RC fiHer) or a buffer, to delay the input of the power, the voltage division signal, the time of input, but not limited to the examples. In summary, the present invention is boosted The circuit 3〇 and the step-down circuit 31 respectively generate a boost signal VPU and The voltage signal VPD. When the input voltage Vin continues to rise, (4) the control of the boost signal VP#·-switch, so that the gate of the power transistor 20 is pulled up, and the output voltage V〇ut is suppressed. The input voltage rises. In the case where the input voltage 'n continues to decrease', the downsampling signal VPD is used as the control of the second switch 33, so that the gate voltage of the power transistor 20 is lowered to suppress the output voltage Vout. The electric current circuit of the present invention continues to decline. The linear voltage stabilizing circuit 2 of the present invention controls the reaction time by means of a feed-i〇rward path, so that the lifting circuit 3 achieves faster response to noise than feedback. The reaction speed of the circuit; and the lifting circuit 3 uses the switching mode of the virtual switch to control the compensation current, so as to quickly suppress the change of the output voltage v〇m, thereby not affecting the feedback circuit 'effectively increasing the stability of the system. 099110679 Form number A0101 Page 8 of 15 0992018786-0 201135390 [0019] Although the present invention has been disclosed in a preferred embodiment as above, it is not intended to limit the invention, and anyone skilled in the art will not In the spirit and scope of the present invention, the scope of the present invention is defined by the scope of the appended claims. [0020] In order to make the present invention The above and other objects, features, advantages and embodiments are readily apparent. The detailed description of the drawings is as follows: [0021] FIG. 1 shows a low dropout voltage regulator circuit used in the prior art;
[0022] 圖2係為本發明之線性穩壓電路一實施例；以及 [0023] 圖3為本發明之升降電路一實施例。 【主要元件符號說明】 [0024] 1, 2:線性穩壓電路 [0025] 12, 22 :參考電路 [0026] 11, 21 :誤差放大器 [0027] 10, 20 :功率電晶體 [0028] 3 ： 升降電路 [0029] 30 :升壓單元 [0030] 300 :阻抗電晶體 [0031] 301 :升壓延遲單元 [0032] 31 ： 降壓單元 [0033] 310 :電流啟動單元 表單編號A0101 099110679 第9頁/共15頁 0992018786-0 201135390 [0034] 31 1 :鏡射單元 [0035] 312 :降壓延遲單元 [0036] 32 :第一切換器 [0037] 3 2 0 : P型電晶體 [0038] 33 :第二切換器 [0039] 3 3 0 : N型電晶體 _〇] Rr R2, R3〇, R31，R32 :電阻 [0041] V.:輸入電壓 in [0042] V + :輸出電壓 out [0043] V :參考電壓 r [0044] Vf :回授訊號 [0045] VD :分壓訊號 [0046] V + :控制訊號2 is an embodiment of a linear voltage stabilizing circuit of the present invention; and [0023] FIG. 3 is an embodiment of a lifting circuit of the present invention. [Main component symbol description] [0024] 1, 2: linear regulator circuit [0025] 12, 22: reference circuit [0026] 11, 21: error amplifier [0027] 10, 20: power transistor [0028] 3 : Lifting circuit [0029] 30: boosting unit [0030] 300: impedance transistor [0031] 301: boosting delay unit [0032] 31: step-down unit [0033] 310: current starting unit form number A0101 099110679 page 9 / Total 15 pages 0992018786-0 201135390 [0034] 31 1 : Mirror unit [0035] 312 : Buck delay unit [0036] 32 : First switch [0037] 3 2 0 : P type transistor [0038] 33 :Second switcher [0039] 3 3 0 : N type transistor _〇] Rr R2, R3〇, R31, R32 : Resistor [0041] V.: Input voltage in [0042] V + : Output voltage out [0043 ] V : Reference voltage r [0044] Vf : feedback signal [0045] VD : voltage division signal [0046] V + : control signal
Ctrl [0047] Vpu :升壓訊號 [0048] VpD :降壓訊號 099110679 表單編號A0101 第10頁/共15頁 0992018786-0Ctrl [0047] Vpu: boost signal [0048] VpD: step-down signal 099110679 Form number A0101 Page 10 of 15 0992018786-0