201030781 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電容器（capacitor)，特別是指一種 具有摻雜介電層的薄膜電容器（thin film capacitor)。 【先前技術】 參圖1，顯示有一種三層結構的傳統電容器1，包含： 一第一電極11、一與該第一電極11相反設置的第二電極 12，及一夾置於該等電極11、12之間且是由絕緣材料 0 (insulator)所構成的介電層（dielectric layer)13。如以下公式 (I)所示： ...................................................(I) 該三層結構之傳統電容器1的電容值（capacitance，C) 是正比於該等電極11、12其中一者的面積（4)與該介電層 13的介電係數（permittivity，f)，且是反比於該介電層13 的厚度（^)。一般而言，經由增加該等電極11、12其中一者 的面積（J)與該介電層13的介電係數（f)，或減少該介電層 ® 13的厚度可提昇該傳統電容器1的電容值（c)。 當該傳統電容器1被充電後，將於該傳統電容器1產 生一電場（electric field);其中，介電係數（f)的數值在上述 公式⑴中意義則涉及其介電材料本身之絕緣特性、在該電 場下產生感應耗極矩（induced dipole moments)的能力、自激 麵極矩（self-excited dipole moments)的強度等介電材料本身 的特性。此等介電材料本質上的特性可防止該傳統電容器1 在該電場的作用下所產生的漏電流（current leakage)與介電 3 201030781 崩潰（breakdown)，並提昇電荷儲存量，以使得電容值（c)得 以增加。因此，此技術領域者一方面是尋求巨介電材料 (giant dielectrics)來提昇電容值（C)，如，CaCu3Ti4012。 此處需說明的是，一般用來做為電容器使用的介電材 料需具備有低孔隙率與優異的結晶品質等特點，才足以抵 擋形成於電容器内的電場。然而，此等結晶品質優異的介 電材料不僅需透過800°C以上的燒結製程（sintering)才可製 成；此外，經由燒結製程所製得之介電層的厚度（^)往往已 高達數個微米（〜μπι)或數十個微米厚。因此，對於提昇電容 器的電容值（C)而言，其貢獻度有限。再者，以高溫的燒結 製程及最終製得之介電層的厚度來說，其並不利於元件微 型化以被整合至積體電路（integrated circuit，1C)中。 又，利用化學氣相沉積法（CVD)等薄膜製程（thin film process)來製作介電層，雖然可降低介電層的厚度（rf)。然 而，所製得之介電層的結晶品質差，且孔隙率高。因此， 崩潰電壓低，且易有漏電流的問題產生。 隨著積體電路之元件（IC device)的尺寸持續地下降，電 容器的微型化在積體電路元件中則成為了必不可少的重要 技術。典型地被使用於積體電路中的元件可見有薄膜電容 器，如，動態隨機存取記憶體（dynamic random access memory，簡稱DRAM)，其通常具有一被兩電極板所夾置的 介電材料層。照慣例，被用於該薄膜電容器之介電材料層 的介電材料包括有氧化石夕（silicon dioxide)、氮化碎（silicon nitride)及其類似材料。然而，當該介電材料層的厚度被降 201030781 低至一特定程度時，此等介電材料則呈現出一相當高的漏 電流及一低的崩潰電壓。 經上述說明可知’提供一種崩潰電壓高且漏電流低的 薄臈電容器，以利於將其整合至由薄膜製程所構成的積體 電路中，是此技術領域者所需改進的課題。 【發明内容】 因此，本發明之目的，即在提供一種薄膜電容器。 於疋’本發明之薄膜電容器，包含：一第一電極、一 參與該第一電極相對立的第二電極，及一夾置於該第一、二 電極之間的介電膜層結構。該介電膜層結構具有一經摻雜 的介電層。該經摻雜的介電層具有一大於零且小於1〇1〇原 子/cm3的摻雜濃度的摻雜物。 本發明之功效在於：提供崩潰電壓高且漏電流低的薄 膜電容器，以利於將其整合至積體電路中。 【實施方式】 <發明詳細說明> 鲁 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之三個較佳實施例、一個具趙例與一個 比較例的詳細說明中，將可清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。 參閱圖2’本發明之薄膜電容器的一第—較佳實施例是 經由濺鍍法（sputtering)所製得。本發明之薄膜電容器的第一 較佳實施例’包含：一第一電極2、一與該第—電極2相對 5 201030781 立的第二電極3，及一夾置於該第一、二電極2、3之間的 介電膜層結構4。該介電膜層結構4具有一經摻雜的介電層 41。該經摻雜的介電層41具有一大於零且小於1〇10原子 /cm3的摻雜濃度的摻雜物。此處需說明的是，本發明於呈 絕緣性的介電材料内摻雜入摻雜濃度低於l〇1Q原子/cm3的 摻雜物；因此，該經摻雜的介電層41是被定義為半絕緣層 (semi-insulated layer)。該經摻雜的介電層41之摻雜物是選 自下列所構成之群組的元素：過渡元素（transition elements)、IIIA族元素、VA族元素，及前述元素的組合。 較佳地，該經摻雜的介電層41之摻雜濃度是介於106 原子/cm3至101G原子/cm3之間。 該等過渡金屬元素包括IB族、IIB族、IIIB族、VIB 族、VB 族、VIB 族、VIIB 族，及 VIIIB 族。 較佳地，該經摻雜的介電層41是由一氧化物所構成； 該經摻雜的介電層41之摻雜物是Co、Fe、Ni、Ga、Mn、 As、Al、Zn、Ti、P，或前述之組合。在本發明一具體例 中，構成該經摻雜的介電層41的氧化物是Si02。 較佳地，該第一、二電極2、3至少其中之一為導電材 料所構成；更佳地，該第一、二電極2、3至少其中之一是 由一磁性材料所構成。 適用於本發明之磁性材料是鐵磁性材料（ferromagnetic material)或反鐵磁性材料（antiferromagnetic material)。較佳 地，該鐵磁性材料是鐵基合金（Fe-based alloy)、鈷基合金 (Co-based alloy)、錄基合金（Ni-based alloy)，或前述之組 201030781 合；該反鐵磁性材料是猛（Μη)或猛基合金（Μη-based alloy)。此處值得說明的是，本發明利用濺鍍法來鍍製該等 電極2、3(即，磁性材料）時，可同時經由對一鍍製該磁性材 料之反應室（圖未示）提供一預定方向的外加磁場（applied magnetic field)來設定該磁性材料内的磁矩（magnetic moment) 方向，藉以提昇其淨磁化量（net magnetization)。 較佳地，該經摻雜的介電層41之厚度是介於50 nm至 3000 nm之間；更佳地，該經摻雜的介電層41之厚度是介 _ 於50 nm至500 nm之間。 參閱圖3,本發明之薄膜電容器的一第二較佳實施例大 致上是相同於該第一較佳實施例，其不同處是在於，該介 電膜層結構4更具有至少一未經摻雜的介電層42。 較佳地，該未經摻雜的介電層42是由該氧化物所構成 (例如Si02等）。 較佳地，該未經摻雜的介電層42之厚度是介於50 nm 至3000 nm之間；更佳地，該未經摻雜的介電層42之厚度 ^ 是介於50 nm至500 nm之間。 參閱圖4,本發明之薄膜電容器的一第三較佳實施例大 致上是相同於該第二較佳實施例，其不同處是在於，該介 電膜層結構4具有二未經摻雜的介電層42以將該經摻雜的 介電層41夾置於其中。 <具體例1> 本發明之薄膜電容器的一具體例1是經由濺鍍法所製 得，其包含：兩對立設置且是由一鐵鈷鎳合金（FeCoNi alloy) 201030781 之鐵磁性材料所構成之尺寸為200 μιη x 600 μιη x 30 nm 的電極，及一夾置於該等電極之間且厚度50 nm之經A1與 Co摻雜的Si02層，藉以於該具體例1之薄膜電容器内產生 一約 680 Oe 至 1500 Oe 的内建磁場（build-in magnetic field)。在本發明該具體例1中，該薄膜電容器的膜層結構 為 FeCoNi Alloy/Al，Co-doped Si02/FeCoNi Alloy，且該經 A1 與Co摻雜的Si02層之摻雜濃度約107 atoms/cm3。 本發明該具體例1之薄膜電容器經電源供應系統量 測，在275V電壓之下仍然沒有崩潰。且經數據收集器 (KEITHLEY 2400)量測取得該具體例1之薄膜電容器在5 V 的外加電壓下之漏電流約1(Γ8 A。 <比較例> 本發明之薄膜電容器的一比較例大致上是相同於該具 體例1，其不同處是在於，以一厚度約50 nm之未經摻雜的 Si02層來取代該經A1與Co掺雜的Si02層，且該等電極是 由鉑（Pt)所構成。在本發明該比較例中，該薄膜電容器的膜 層結構為 Pt/undoped-Si〇2/Pt。 本發明該比較例之薄膜電容器經量測取得之崩潰電壓 僅約7至8 V，且該比較例之薄膜電容器在5 V的外加電壓 下之漏電流約高達1〇_6 A。 為更明確顯示本發明之薄膜電容器所具有之低漏電流 的優點，圖5顯示該具體例1及比較例所量測之漏電流比 較圖。如圖5所示，在0 V至5V的外加電壓範圍下，該具 體例1的漏電流一值維持在1(Τ8 A以下；反觀該比較例， 201030781 在此相同的外加電壓範圍下其漏電流最高達到1〇_6a。 綜上所述，本發明之薄臈電容器的崩潰電壓高且漏電 流低，有利於被整合至積體電路中，故確實能達成本發明 之目的。 惟以上所述者，僅為本發明之較佳實施例與具體例而 已，當不能以此限定本發明實施之範圍，即大凡依本發明 申請專利範圍及發明說明内容所作之簡單的等效變化與修 飾，皆仍屬本發明專利涵蓋之範圍内。 _ 【圖式簡單說明】 圖1是一正視示意圖，說明習知一種傳統電容器； 圖2是一正視示意圖，說明本發明之薄膜電容器的一 第一較佳實施例； 圖3是一正視示意圖，說明本發明之薄膜電容器的一 第二較佳實施例； 圖4是一正視示意圖，說明本發明之薄膜電容器的一 第三較佳實施例；及。 Φ 圖5是一電流對電壓（I-V)曲線圖，說明本發明之薄膜 電容器的一具體例1與一比較例之電性比較。 201030781 【主要元件符號說明】 2 第一電極 41 經摻雜的介電層 3 第二電極 42 未經掺雜的介電層 4 介電膜層結構201030781 VI. Description of the Invention: [Technical Field] The present invention relates to a capacitor, and more particularly to a thin film capacitor having a doped dielectric layer. [Prior Art] Referring to Figure 1, there is shown a conventional capacitor 1 having a three-layer structure comprising: a first electrode 11, a second electrode 12 disposed opposite the first electrode 11, and a sandwiching electrode Between 11, 12 and is a dielectric layer 13 composed of an insulating material (insulator). As shown in the following formula (I): ........................................ ..... (I) The capacitance value (C) of the conventional capacitor 1 of the three-layer structure is proportional to the area (4) of one of the electrodes 11, 12 and the dielectric The dielectric constant (f) of the layer 13 is inversely proportional to the thickness (^) of the dielectric layer 13. In general, the conventional capacitor 1 can be improved by increasing the area (J) of one of the electrodes 11, 12 and the dielectric constant (f) of the dielectric layer 13, or reducing the thickness of the dielectric layer 13 Capacitance value (c). When the conventional capacitor 1 is charged, an electric field is generated in the conventional capacitor 1; wherein the value of the dielectric constant (f) in the above formula (1) relates to the insulating property of the dielectric material itself, The characteristics of the dielectric material itself such as the ability to induce induced dipole moments and the strength of self-excited dipole moments under the electric field. The intrinsic properties of these dielectric materials prevent the current leakage of the conventional capacitor 1 under the action of the electric field and the breakdown of the dielectric 3 201030781, and increase the charge storage amount so that the capacitance value (c) can be increased. Therefore, one skilled in the art is to seek giant dielectrics to increase the capacitance value (C), such as CaCu3Ti4012. It should be noted here that the dielectric material generally used as a capacitor needs to have low porosity and excellent crystal quality to resist the electric field formed in the capacitor. However, these dielectric materials excellent in crystal quality are not only required to be sintered through a sintering process of 800 ° C or higher; in addition, the thickness (^) of the dielectric layer obtained through the sintering process is often as high as several Micron (~μπι) or tens of microns thick. Therefore, the contribution of the capacitor (C) of the boost capacitor is limited. Furthermore, in terms of the high temperature sintering process and the thickness of the finally produced dielectric layer, it is not advantageous for component miniaturization to be integrated into an integrated circuit (1C). Further, the dielectric layer is formed by a thin film process such as chemical vapor deposition (CVD), although the thickness (rf) of the dielectric layer can be lowered. However, the resulting dielectric layer has poor crystal quality and high porosity. Therefore, the breakdown voltage is low and the problem of leakage current is generated. As the size of the IC device continues to decrease, the miniaturization of the capacitor becomes an indispensable important technique in the integrated circuit component. A component typically used in an integrated circuit can be seen as a film capacitor, such as a dynamic random access memory (DRAM), which typically has a layer of dielectric material sandwiched between two electrode plates. . Conventionally, dielectric materials used for the dielectric material layer of the film capacitor include silicon dioxide, silicon nitride, and the like. However, when the thickness of the dielectric material layer is lowered to a certain extent, the dielectric material exhibits a relatively high leakage current and a low breakdown voltage. As apparent from the above description, it is an object of the art to provide a thin tantalum capacitor having a high breakdown voltage and a low leakage current to facilitate integration into an integrated circuit composed of a thin film process. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a film capacitor. The film capacitor of the present invention comprises: a first electrode, a second electrode opposite to the first electrode, and a dielectric film layer sandwiched between the first and second electrodes. The dielectric film layer structure has a doped dielectric layer. The doped dielectric layer has a dopant concentration greater than zero and less than 1 〇 1 〇 atoms/cm 3 . The effect of the present invention is to provide a thin film capacitor having a high breakdown voltage and a low leakage current to facilitate integration into an integrated circuit. [Embodiment] <Detailed Description of the Invention> The foregoing and other technical contents, features, and effects of the present invention are described in detail below with reference to three preferred embodiments of the drawings, a detailed example of a Zhao and a comparative example. In the description, it will be clearly presented. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. Referring to Fig. 2', a first preferred embodiment of the film capacitor of the present invention is produced by sputtering. The first preferred embodiment of the film capacitor of the present invention comprises: a first electrode 2, a second electrode 3 opposite to the first electrode 2, 5201030781, and a first electrode and a second electrode 2 a dielectric film layer structure between 3. The dielectric film layer structure 4 has a doped dielectric layer 41. The doped dielectric layer 41 has a dopant concentration greater than zero and less than 1 〇 10 atoms/cm 3 . It should be noted that the present invention is doped with a dopant having a doping concentration lower than 10 〇 1 Q atoms/cm 3 in an insulating dielectric material; therefore, the doped dielectric layer 41 is Defined as a semi-insulated layer. The dopant of the doped dielectric layer 41 is an element selected from the group consisting of: transition elements, group IIIA elements, group VA elements, and combinations of the foregoing. Preferably, the doped dielectric layer 41 has a doping concentration of between 106 atoms/cm3 and 101 G atoms/cm3. The transition metal elements include Groups IB, IIB, IIIB, VIB, VB, VIB, VIIB, and VIIIB. Preferably, the doped dielectric layer 41 is composed of an oxide; the dopant of the doped dielectric layer 41 is Co, Fe, Ni, Ga, Mn, As, Al, Zn. , Ti, P, or a combination of the foregoing. In one embodiment of the invention, the oxide constituting the doped dielectric layer 41 is SiO 2 . Preferably, at least one of the first and second electrodes 2, 3 is made of a conductive material; more preferably, at least one of the first and second electrodes 2, 3 is made of a magnetic material. A magnetic material suitable for use in the present invention is a ferromagnetic material or an antiferromagnetic material. Preferably, the ferromagnetic material is an Fe-based alloy, a Co-based alloy, a Ni-based alloy, or the aforementioned group 201030781; the antiferromagnetic The material is 猛η or Μη-based alloy. It should be noted here that when the present invention utilizes a sputtering method to plate the electrodes 2, 3 (ie, magnetic materials), a reaction chamber (not shown) for plating the magnetic material may be simultaneously provided. An applied magnetic field in a predetermined direction is used to set a magnetic moment direction in the magnetic material, thereby increasing its net magnetization. Preferably, the thickness of the doped dielectric layer 41 is between 50 nm and 3000 nm; more preferably, the thickness of the doped dielectric layer 41 is between 50 nm and 500 nm. between. Referring to FIG. 3, a second preferred embodiment of the film capacitor of the present invention is substantially the same as the first preferred embodiment, except that the dielectric film layer structure 4 has at least one undoped A heterogenous dielectric layer 42. Preferably, the undoped dielectric layer 42 is composed of the oxide (e.g., SiO 2 or the like). Preferably, the thickness of the undoped dielectric layer 42 is between 50 nm and 3000 nm; more preferably, the thickness of the undoped dielectric layer 42 is between 50 nm and Between 500 nm. Referring to FIG. 4, a third preferred embodiment of the film capacitor of the present invention is substantially the same as the second preferred embodiment, except that the dielectric film layer structure 4 has two undoped layers. The dielectric layer 42 is sandwiched between the doped dielectric layer 41. <Specific Example 1> A specific example 1 of the film capacitor of the present invention is produced by a sputtering method comprising: two oppositely disposed and composed of a ferromagnetic material of FeCoNi alloy 201030781 An electrode having a size of 200 μm x 600 μm x x 30 nm, and an A1 and Co doped SiO 2 layer sandwiched between the electrodes and having a thickness of 50 nm, thereby being produced in the film capacitor of the specific example 1. A build-in magnetic field of about 680 Oe to 1500 Oe. In the specific example 1 of the present invention, the film structure of the film capacitor is FeCoNi Alloy/Al, Co-doped SiO 2 /FeCoNi Alloy, and the doping concentration of the A1 and Co doped SiO 2 layer is about 107 atoms/cm 3 . . The film capacitor of this specific example 1 of the present invention was measured by a power supply system and did not collapse under a voltage of 275V. The leakage current of the film capacitor of this specific example 1 at an applied voltage of 5 V was measured by a data collector (KEITHLEY 2400) to be about 1 (Γ8 A. <Comparative Example> A comparative example of the film capacitor of the present invention It is substantially the same as the specific example 1, except that the A1 and Co doped SiO 2 layers are replaced by an undoped SiO 2 layer having a thickness of about 50 nm, and the electrodes are made of platinum. In the comparative example of the present invention, the film structure of the film capacitor is Pt/undoped-Si〇2/Pt. The film capacitor of the comparative example of the present invention has a breakdown voltage of only about 7 Up to 8 V, and the leakage current of the film capacitor of this comparative example at an applied voltage of 5 V is as high as about 1 〇 6 A. In order to more clearly show the advantage of the low leakage current of the film capacitor of the present invention, FIG. 5 shows The comparison of the leakage currents measured in the specific example 1 and the comparative example. As shown in FIG. 5, the leakage current value of the specific example 1 is maintained at 1 (Τ8 A or less) in the applied voltage range of 0 V to 5 V; In contrast, the comparative example, 201030781 has the highest leakage current under the same applied voltage range. Up to 1〇_6a. In summary, the thin tantalum capacitor of the present invention has a high breakdown voltage and a low leakage current, which is advantageous for integration into an integrated circuit, so that the object of the present invention can be achieved. It is only the preferred embodiments and specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are still 1 is a schematic front view showing a conventional capacitor; FIG. 2 is a front view showing a first preferred embodiment of the film capacitor of the present invention. 3 is a front view showing a second preferred embodiment of the film capacitor of the present invention; and FIG. 4 is a front elevational view showing a third preferred embodiment of the film capacitor of the present invention; 5 is a current versus voltage (IV) graph illustrating the electrical comparison of a specific example 1 of the film capacitor of the present invention with a comparative example. 201030781 [Explanation of main component symbols] 2 First electrode 41 doped dielectric layer 3 second electrode 42 undoped dielectric layer 4 dielectric film layer structure
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