200929467 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板結構，尤指一種增加導電 元件結合力之封裝基板結構。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniaturization)的封裝要求， 10 提供多數主被動元件及線路連接之電路板，亦逐漸由單層 板演變成多層板，以使在有限的空間下，藉由層間連接技 術（interlayer connection)擴大電路板上可利用的佈線面積 而配合高電子密度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 15 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、壓 模、以及植球等製程，又一般半導體封裝結構是將半導體 晶片背面黏貼於基板頂面，進行打線接合（wire bonding )， 或將半導體晶片主動面以覆晶接合（flip chip)方式與基板 20 電性連接，再於基板之背面植以錫球以供與外部電子裝置 進行電性連接。 表面具有導電元件之習知封裝基板請參見圖1。要製成 如圖1所示之結構，主要先提供一基板11。而後，利用無電 電鍍於基板11之一表面11a形成一晶種層12。再透過此晶種 5 200929467 5 Ο 10 15 ❹ 層12導通電流，使用電鍍結合電鍍阻層之微影製程等習知 技術，於基板11表面11a形成一線路層14。爾後，再形成一 防焊層15於該基板11表面lla，同樣利用圖案化之技術，於 此防焊層15形成複數開孔153，使開孔153顯露部份的線路 層14作為電性連接塾142 ’該線路層14復包括線路141導接 至電性連接墊142。接著，於顯露之電性連接墊142表面以 印刷或電鑛法形成焊料凸塊18 ’俾完成一表面具有導電連 接結構之習知封裝基板。 雖然此種焊料凸塊18可供與半導體晶片電性連接，但 在半導體封裝件高積集度以及微型化的封裝要求下，造成 線路的線寬/線距不斷縮小的趨勢。當封裝基板表面結構線 寬及線距縮短時，倘若應用此種習知導電連接結構，因接 點強度亦隨著接合面積而縮小，則面臨接合半導體晶片及 封裝基板間之焊料凸塊18其強度不足以承受晶片與基板間 的剪應力（shear stress)，至此加劇造成焊料凸塊18斷裂 的現象，而無法達到可靠度的需求。 此外’當此種結構之封裝基板接受信賴度測試，如熱 衝擊（不論是溫度上升或下降）、濕度變化等，由於基板 與蟬料凸塊因溫度變化而產生剪應力，而焊料凸塊與基板 之接合強度不足以抵抗煎應力，此使得焊料凸塊與電性連 接墊之間的接合面發生斷裂現象，此等現象致使基板與晶 片之間的電性連接失效。 20 200929467 因此，為提高基板與晶片間電性連接之品質，強化基 板表面用於電性連接功能之導電元件的可靠度，實為一需 積極解決的課題。 5 ❿ 10 15 ❹ 【發明内容】 本發明提供一種封裝基板結構，其包括：一基板，其 表面具有複數電性連接墊；複數金屬凸塊，係分別配置於 該些電性連接墊表面；以及一介電層，係覆蓋該基板及該 些金屬凸塊，且該介電層具有複數凹口（ recesses )以顯露 該些金屬凸塊頂部，其中該些凹口内表面係為粗糙化表面。 上述之結構可更包含複數條線路，該些線路係配置於 該基板表面並電性連接該些電性連接墊。另外，本發明之 封裝基板結構也可包含複數焊料凸塊，該些焊料凸塊係配 置於該些凹口上並覆蓋該些金屬凸塊頂部。此外，於該些 金屬凸塊及該些焊料凸塊之間，亦可包含一金屬黏著層配 置其間。其中該金屬黏著層之材料係選自由錫、銀、鎳、 金、鉻/鈦合金、鎳/金合金、鎳/把合金、與鎳/把/金合金所 組群組其中之一者。 上述之結構中，該基板可為任何基板，較佳可使用一 完成前段製程之電路板。另一方面，該介電層可為一般之 平滑表面，但較佳為粗糙化表面。再者，該些金屬凸塊之 高度不限，但較佳為分別突出該些凹口之内表面。此外， 該些凹口之内徑較佳係大於該些金屬凸塊之内徑。 20 200929467 本發明上述之結構中，該金屬黏著層之材料可為任何 材料，較佳係選自由錫、銀、錄、金、絡/欽合金、鎳/金合 金、鎳/鈀合金、與鎳/把/金合金所組群組其中之一者。另 外，該些電性連接墊及該些金屬凸塊之材料不受限制，較 5 佳係選自由錫、銀、銅、金、麵、錄、鋅、錄、錯、鎮、 銦、鎵、及其合金所組群組其中之一者。此外，該介電層 之材料不受限制，較佳係選自由ABF (Ajinomoto Build-up Film)、聯二苯環丁二烯（benzocylobutene，BCB)、液晶 〇 聚合物（liquid crystal polymer，LCP )、聚亞醯胺 10 ( polyimide ’ PI )、聚乙烯謎（poly(phenylene ether)，PPE )、 聚四氟乙烯（poly(tetra-fluoroethylene)，PTFE ) 、FR4、 FR5、雙順丁醢二酸醯亞胺/三氮胖（bismaleimide triazine， BT)、芳香尼龍（aramide)、及環氧樹脂與玻璃纖維之混 合物所組群組其中之一者。 15 因此，本發明所提供之封裝基板結構，由於電性連接 墊表面具有金屬凸塊，所以可以減少焊料使用量。另外， φ 介電層對應金屬凸塊之位置具有凹口，此凹口之内表面有 經過粗糙化處理，因此能夠增加介電層與焊料凸塊間之接 合能力，再者，因其於電性連接墊表面配置有金屬凸塊， 20 且金屬凸塊頂部突出於凹口，故該可藉由焊料凸塊覆蓋金 屬凸塊頂部，以增加焊料凸塊的結合能力，避免習知焊料 凸塊容易掉落的缺失。 所以，在半導體封裝件高積集度以及微型化的封裝要 求下，當線路的線寬/線距不斷縮小時’本發明封裝基板結 200929467 構之電性連接墊及焊料凸塊間，因上述介電層凹口及突出 於介電層凹口的金屬凸塊’所以仍然能具有良好的結合強 度，減少發生焊料凸塊斷裂的現象，而具有較佳的可靠度。 且當本發明封裝基板結構接受信賴度測試，如熱衝擊（不 5 論是溫度上升或下降）、濕度變化等，由於其接合強度已 加強’因此不僅減少焊料凸塊斷裂現象，同時增加產品良 率〇 v 【實施方式】 10 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 15 種修飾與變更。 本發明之實施例甲該等圖式均為簡化之示意圖。惟該 〇 等圖示僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 20 請參考圖2A〜2H，此為製作本實施例封裝基板結構之 製作流程示意圖。 首先，如圖2A所示，提供一基板21。而本實施例所使 用之基板21係為一完成前段製程之電路板，圖2A之基板21 僅為示意，故省略詳細的線路連結。其係可利用無電電鍍 9 200929467 5 ❹ 10 15 ❹ 技術，於此基板21表面21a形成一晶種層22。此晶種層22之 材料可以選用自銅、錫、錄、鉻、鈦、銅/鉻合金、以及錫 /鉛合金所組群組其中之一者。本實施例使用銅作為此晶種 層22之材料。接著，利用習知曝光顯影等圖案化之技術， 形成具有開口區230之第一阻層23於導電層22上。再於第一 阻層23之開口區230内，經由晶種層22導通電流使用電鍍技 術形成一線路層24，此線路層24具有複數條線路241及複數 電性連接墊242，且線路241電性連接電性連接墊242。 接著，如圖2B所示，再次利用曝光顯影的方式，形成 具複數開孔253之第二阻層25,其中，第二阻層25之開孔253 對應於電性連接墊242，而本實施例中開孔253略小於電性 連接墊242。上述之該第一阻層23及第二阻層25可選擇使用 液態光阻或乾膜。 接著，如圖2C所示，同樣利用電鍍方式，於開孔253 内形成複數金屬凸塊26，此金屬凸塊26之材料可選用自 錫、銀、銅、金、秘、録、辞、鎳、錯、鎮、銦、嫁及其 合金所組群組其中之一者。於本實施例中，則使用銅作為 金屬凸塊26之材料。 然後，見圖2D所示，將第二阻層25、第一阻層23及兩 者所覆蓋之導電層22完全移除，而顯露出線路241、金屬凸 塊26以及未受金屬凸塊26覆蓋之部分電性連接墊242。 接著，如圖2E所示，於基板21之表面21a形成一介電層 27以覆蓋線路24卜金屬凸塊26以及未受金屬凸塊26覆蓋之 部分電性連接墊242。而後，利用雷射银孔（laser ablation ) 20 200929467 技術，將覆蓋於金屬凸塊26表面之介電層27移除，於是形 成複數凹口 274顯露金屬凸塊26頂部（參見圖2F)。本實施 例中，這些凹口 274之内徑大於金屬凸塊26之内徑，且金屬 凸塊26頂部分別突出凹口 274之内表面，且。再如圖2G所 5 示，利用物理或化學方式如化學藥劑侵蝕介電層27，將介 電層27表面及凹口 274内表面進行粗糙化。此一粗糙化的步 驟，因為增加介電層27的表面積，故於後續製程中，可增 加焊料與介電層27之結合力，亦可增加底膠（underfill)與 © 介電層27表面之結合力。而後，在暴露之金屬凸塊26表面， 10 可選擇性形成一金屬黏著層（圖未示），以增加金屬凸塊 26及焊料之接合能力。此金屬黏著層的材料，較佳可選自 錫、銀、錄、金、鉻/鈦合金、錄/金合金、鎳/纪合金、與 鎳/鈀/金合金所組成群組其中之一者，本實施例則使用鎳/ 鈀合金。形成該金屬黏著層之方式係可為電鍍、物理沉積 15 及化學沉積之其中一者，其中，該物理沉積方式係為濺鍍 及蒸鍍之其中一者，該化學沉積係為無電電鍍。 φ 最後，為形成作為封裝基板與晶片兩者間之電性連接 點，如圖2H所示，在金屬凸塊26及介電層27之凹口 274上， 經由印刷及回焊製程，形成一焊料凸塊28。此焊料凸塊28 20 之材料較佳可選自銅、錫、錯、錄、金、銀、銀及其合金 所組群組其中之一者，本實施例使用之材料為錫。 經由上述製程後，可得到一封裝基板結構。如圖2H所 示，此封裝基板結構包含一基板21，其表面21a具有複數電 性連接墊242 ;複數金屬凸塊26，係分別配置於該些電性連 11 200929467 5 ❹ 10 15 ❹ 20 接墊表面242;以及一介電層27,係覆蓋該基板以及該些金 屬凸塊26，且該介電層27具有複數凹口 274 (recesses)以 顯露該些金屬凸塊26頂部，其中該些凹口 274内表面係為粗 糙化表面。此外，此封裝基板結構更包含複數焊料凸塊28， 其係配置於該些凹口 274上並覆蓋該些金屬凸塊26頂部。 因此’本發明所提供之封裝基板結構，由於電性連接 墊表面具有金屬凸塊’所以可以減少焊料使用量。另外， 介電層對應金屬凸塊之位置具有凹口，此凹口之内表面有 經過粗糙化處理，因此能夠增加介電層與焊料凸塊間之接 合能力，再者，因其於電性連接墊表面配置有金屬凸塊， 且金屬凸塊頂部.突出於凹口，故該可藉由焊料凸塊覆蓋金 屬凸塊頂部’以增加焊料凸塊的結合能力，避免習知焊料 凸塊容易掉落的缺失。 本發明所提供之封裝基板結構，具有良好的接合強 度，可減少發生焊料凸塊斷裂的現象，並具有較佳的可靠 度。且當本發明封裝基板結構接受信賴度測試，如熱衝擊 (不論是溫度上升或下降）、濕度變化等，由於其接合強 度已加強’因此不僅減少焊料凸塊斷裂現象，同時增加產 品良率。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例》 \ 【圖式簡單說明】 12 200929467 圖1係習知封裝基板結構之剖面示意圖β 圖2Α至2Η係本發明一較佳實施例中封裝基板結構之流程 不意圖。 【主要元件符號說明】 11, 21 基板 11a, 21a 表面 12, 22 晶種層 14, 24 線路層 141, 241 線路 142, 242 電性連接墊 15 防焊層 153, 253 開孔 18, 28 焊料凸塊 230 開口區 23 第一阻層 25 第二阻層 26 金屬增厚塊 27 介電層 274 凹口 13200929467 IX. Description of the Invention: [Technical Field] The present invention relates to a package substrate structure, and more particularly to a package substrate structure that increases the bonding force of a conductive member. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization packaging requirements of semiconductor packages, 10 most of the active and passive components and circuit-connected circuit boards are gradually evolved from single-layer boards to multi-layer boards to make them limited. In the space, the wiring area available on the circuit board is expanded by an interlayer connection to meet the demand for an integrated circuit of high electron density. In the general semiconductor device process, the wafer carrier manufacturer 15 first produces a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. Then, the wafer carrier boards are transferred to a semiconductor package manufacturer for processing such as crystallization, stamping, and ball implantation. In general, the semiconductor package structure is to adhere the back surface of the semiconductor wafer to the top surface of the substrate for wire bonding. Or the semiconductor wafer active surface is electrically connected to the substrate 20 by flip chip bonding, and the solder ball is implanted on the back surface of the substrate for electrical connection with the external electronic device. See Figure 1 for a conventional package substrate with conductive elements on its surface. To form the structure shown in Fig. 1, a substrate 11 is mainly provided first. Then, a seed layer 12 is formed on one surface 11a of the substrate 11 by electroless plating. Further, through the seed crystal 5 200929467 5 Ο 10 15 ❹ The layer 12 is turned on, and a wiring layer 14 is formed on the surface 11a of the substrate 11 by a conventional technique such as electroplating in which a plating resist is applied. Then, a solder resist layer 15 is formed on the surface 11a of the substrate 11, and a patterning technique is also used. The solder resist layer 15 forms a plurality of openings 153, so that the exposed portion of the circuit layer 14 of the opening 153 is electrically connected. The circuit layer 14 includes a line 141 that is electrically connected to the electrical connection pad 142. Next, a solder bump 18' is formed on the surface of the exposed electrical connection pad 142 by printing or electrowinning to complete a conventional package substrate having a conductive connection structure on the surface. Although such solder bumps 18 are electrically connectable to the semiconductor wafer, the line width/line spacing of the lines tends to shrink as the semiconductor package has a high degree of integration and miniaturized package requirements. When the line width and the line pitch of the surface of the package substrate are shortened, if the conventional conductive connection structure is applied, since the joint strength is also reduced with the joint area, the solder bump 18 between the semiconductor wafer and the package substrate is faced. The strength is insufficient to withstand the shear stress between the wafer and the substrate, thereby aggravating the phenomenon that the solder bumps 18 are broken, and the reliability cannot be achieved. In addition, when the package substrate of such a structure is subjected to a reliability test such as thermal shock (whether temperature rise or fall), humidity change, etc., the substrate and the bump are subjected to shear stress due to temperature changes, and the solder bumps and The bonding strength of the substrate is insufficient to resist the frying stress, which causes the bonding surface between the solder bump and the electrical connection pad to be broken, which causes the electrical connection between the substrate and the wafer to fail. 20 200929467 Therefore, in order to improve the quality of the electrical connection between the substrate and the wafer, it is a problem that needs to be actively solved to enhance the reliability of the conductive member on the surface of the substrate for electrical connection. 5 ❿ 10 15 ❹ The present invention provides a package substrate structure, comprising: a substrate having a plurality of electrical connection pads on the surface; and a plurality of metal bumps respectively disposed on the surface of the electrical connection pads; A dielectric layer covers the substrate and the metal bumps, and the dielectric layer has a plurality of recesses to expose the tops of the metal bumps, wherein the inner surfaces of the recesses are roughened surfaces. The above structure may further include a plurality of lines disposed on the surface of the substrate and electrically connected to the electrical connection pads. In addition, the package substrate structure of the present invention may also include a plurality of solder bumps disposed on the recesses and covering the tops of the metal bumps. In addition, a metal adhesion layer may be disposed between the metal bumps and the solder bumps. The material of the metal adhesion layer is selected from the group consisting of tin, silver, nickel, gold, chromium/titanium alloy, nickel/gold alloy, nickel/bar alloy, and nickel/bar/gold alloy. In the above structure, the substrate may be any substrate, and it is preferable to use a circuit board which completes the front-end process. Alternatively, the dielectric layer can be a generally smooth surface, but is preferably a roughened surface. Moreover, the heights of the metal bumps are not limited, but it is preferred to respectively protrude the inner surfaces of the notches. In addition, the inner diameters of the notches are preferably larger than the inner diameters of the metal bumps. 20 200929467 In the above structure of the present invention, the material of the metal adhesion layer may be any material, preferably selected from the group consisting of tin, silver, gold, gold, cobalt alloy, nickel/gold alloy, nickel/palladium alloy, and nickel. / One of the groups of / gold alloys. In addition, the electrical connection pads and the materials of the metal bumps are not limited, and are selected from the group consisting of tin, silver, copper, gold, surface, recorded, zinc, recorded, wrong, town, indium, gallium, One of the group of its alloys. In addition, the material of the dielectric layer is not limited, and is preferably selected from ABF (Ajinomoto Build-up Film), benzocylobutene (BCB), liquid crystal polymer (LCP). , polyimide ' PI ', poly(phenylene ether, PPE ), poly(tetra-fluoroethylene, PTFE ), FR 4 , FR 5 , bis-succinic acid One of the group consisting of bismaleimide triazine (BT), aramide, and a mixture of epoxy resin and glass fiber. Therefore, in the package substrate structure provided by the present invention, since the surface of the electrical connection pad has metal bumps, the amount of solder used can be reduced. In addition, the φ dielectric layer has a recess corresponding to the position of the metal bump, and the inner surface of the recess has been roughened, so that the bonding ability between the dielectric layer and the solder bump can be increased, and further, The surface of the connection pad is provided with a metal bump, 20 and the top of the metal bump protrudes from the recess, so the top of the metal bump can be covered by the solder bump to increase the bonding ability of the solder bump, and the conventional solder bump can be avoided. A drop that is easy to drop. Therefore, under the high integration of the semiconductor package and the miniaturized package requirement, when the line width/line distance of the line is continuously reduced, the electrical connection pad and the solder bump of the package substrate 200929467 of the present invention are The dielectric layer recess and the metal bumps protruding from the recess of the dielectric layer can still have good bonding strength, reduce the occurrence of solder bump breakage, and have better reliability. And when the package substrate structure of the present invention is subjected to a reliability test, such as thermal shock (not rising or falling in temperature), humidity change, etc., since the joint strength has been strengthened, the solder bump fracture phenomenon is not reduced, and the product is improved. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Embodiments of the Invention These drawings are simplified schematic diagrams. However, the drawings and the like only show the components related to the present invention, and the components shown therein are not in actual implementation, and the actual number of components in the actual implementation is a selective design and its components. The layout type can be more complicated. 20, please refer to FIG. 2A to FIG. 2H, which are schematic diagrams showing the manufacturing process of the package substrate structure of the present embodiment. First, as shown in FIG. 2A, a substrate 21 is provided. The substrate 21 used in this embodiment is a circuit board which completes the front-end process, and the substrate 21 of FIG. 2A is only schematic, and detailed wiring connections are omitted. It is possible to form a seed layer 22 on the surface 21a of the substrate 21 by electroless plating 9 200929467 5 ❹ 10 15 ❹ technology. The material of the seed layer 22 can be selected from the group consisting of copper, tin, copper, chromium, titanium, copper/chromium alloy, and tin/lead alloy. This embodiment uses copper as the material of the seed layer 22. Next, a first resist layer 23 having an open region 230 is formed on the conductive layer 22 by a patterning technique such as conventional exposure development. Further, in the open region 230 of the first resist layer 23, a current is conducted through the seed layer 22, and a circuit layer 24 is formed by using an electroplating technique. The circuit layer 24 has a plurality of lines 241 and a plurality of electrical connection pads 242, and the line 241 is electrically The electrical connection pads 242 are connected. Next, as shown in FIG. 2B, a second resist layer 25 having a plurality of openings 253 is formed by exposure and development. The opening 253 of the second resist layer 25 corresponds to the electrical connection pad 242. In the example, the opening 253 is slightly smaller than the electrical connection pad 242. The first resist layer 23 and the second resist layer 25 may be selected from liquid photoresist or dry film. Then, as shown in FIG. 2C, a plurality of metal bumps 26 are formed in the opening 253 by using the plating method. The material of the metal bumps 26 can be selected from tin, silver, copper, gold, secret, recorded, resigned, and nickel. One of the groups of groups, faults, towns, indiums, marry and alloys. In the present embodiment, copper is used as the material of the metal bumps 26. Then, as shown in FIG. 2D, the second resist layer 25, the first resist layer 23 and the conductive layer 22 covered by the two are completely removed, and the line 241, the metal bumps 26 and the unobtained metal bumps 26 are exposed. A portion of the electrical connection pads 242 are covered. Next, as shown in FIG. 2E, a dielectric layer 27 is formed on the surface 21a of the substrate 21 to cover the wiring 24 and the metal bumps 26 and the portion of the electrical connection pads 242 not covered by the metal bumps 26. The dielectric layer 27 overlying the surface of the metal bumps 26 is then removed using laser ablation 20 200929467 technology, thereby forming a plurality of recesses 274 to reveal the tops of the metal bumps 26 (see Figure 2F). In this embodiment, the inner diameter of the notches 274 is larger than the inner diameter of the metal bumps 26, and the tops of the metal bumps 26 respectively protrude the inner surfaces of the notches 274. Further, as shown in Fig. 2G, the surface of the dielectric layer 27 and the inner surface of the recess 274 are roughened by etching the dielectric layer 27 by physical or chemical means such as chemical. In this roughening step, since the surface area of the dielectric layer 27 is increased, the bonding force between the solder and the dielectric layer 27 can be increased in the subsequent process, and the underfill and the surface of the dielectric layer 27 can be increased. Binding force. Then, on the surface of the exposed metal bumps 26, a metal adhesion layer (not shown) may be selectively formed to increase the bonding ability of the metal bumps 26 and the solder. The material of the metal adhesion layer is preferably selected from the group consisting of tin, silver, gold, chromium/titanium alloy, nickel alloy/nickel alloy, and nickel/palladium/gold alloy. In this embodiment, a nickel/palladium alloy is used. The metal adhesion layer may be formed by one of electroplating, physical deposition, and chemical deposition, wherein the physical deposition method is one of sputtering and evaporation, and the chemical deposition is electroless plating. φ Finally, in order to form an electrical connection point between the package substrate and the wafer, as shown in FIG. 2H, on the metal bump 26 and the recess 274 of the dielectric layer 27, a printing and reflow process is formed to form a Solder bumps 28. The material of the solder bumps 28 20 is preferably selected from the group consisting of copper, tin, aluminum, silver, silver, silver, and alloys thereof. The material used in this embodiment is tin. After the above process, a package substrate structure can be obtained. As shown in FIG. 2H, the package substrate structure includes a substrate 21 having a surface 21a having a plurality of electrical connection pads 242. The plurality of metal bumps 26 are respectively disposed on the electrical connections 11 200929467 5 ❹ 10 15 ❹ 20 a pad surface 242; and a dielectric layer 27 covering the substrate and the metal bumps 26, and the dielectric layer 27 has a plurality of recesses 274 (recesses) to expose the tops of the metal bumps 26, wherein the The inner surface of the recess 274 is a roughened surface. In addition, the package substrate structure further includes a plurality of solder bumps 28 disposed on the recesses 274 and covering the tops of the metal bumps 26. Therefore, the package substrate structure provided by the present invention can reduce the amount of solder used since the surface of the electrical connection pad has metal bumps. In addition, the dielectric layer has a recess corresponding to the position of the metal bump, and the inner surface of the recess has been roughened, thereby increasing the bonding ability between the dielectric layer and the solder bump, and further, because of its electrical property. The surface of the connection pad is provided with a metal bump, and the top of the metal bump protrudes from the recess, so the top of the metal bump can be covered by the solder bump to increase the bonding ability of the solder bump, and the solder bump is easy to avoid. The drop is missing. The package substrate structure provided by the invention has good joint strength, can reduce the occurrence of solder bump breakage, and has better reliability. Further, when the package substrate structure of the present invention is subjected to a reliability test such as thermal shock (whether temperature rise or fall), humidity change, etc., the joint strength is enhanced, thereby not only reducing solder bump fracture but also increasing product yield. The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims should be based on the scope of the patent application, and is not limited to the above embodiments. [ [Simple description] 12 200929467 A schematic cross-sectional view of a conventional package substrate structure. Fig. 2 to 2 are schematic flows of a package substrate structure in a preferred embodiment of the present invention. [Major component symbol description] 11, 21 substrate 11a, 21a surface 12, 22 seed layer 14, 24 circuit layer 141, 241 line 142, 242 electrical connection pad 15 solder mask 153, 253 opening 18, 28 solder bump Block 230 open area 23 first resistive layer 25 second resistive layer 26 metal thickening block 27 dielectric layer 274 notch 13