SU1499389A1 - Transmitting device for adaptive telemetery system - Google Patents

Abstract

The invention relates to information-measuring technology and can be used in cases where redundancy is required in the discrete representation of signals. The purpose of the invention is to increase the information content and accuracy of the device. The device contains a switch 1, analog-to-digital converter 2, blocks 3 and 4 of the buffer memory, control block 5 containing elements AND 6,7,8,14,15,27, elements OR 9,10,19,20, inverter 11 , pulse generator 12, trigger 13, address counter 16, signal activity analyzer 17, code comparison circuit 18, address buffer registers 21, clock distributor 22, switch 23, demultiplexer 24, multiplexer 25, pulse counter 26 and output block 28. 3 silt

Description

This invention relates to an information measuring technique and can be used in a magnetic recording technique. . .

The purpose of the invention is to increase the information content and accuracy of the device.

FIG. 1 is a functional diagram of the deviceJ in FIG. 2 shows the signal activity analyzer in FIG. 3; a time diagram of the operation of the device.

The device contains (FIG. 1) switch 1, analog-to-digital converter 2, blocks 3 and 4 of the buffer unit, control unit 5 containing elements AND 6-8, elements OR 9 and 10, inverter 11, generator 12 pulses, trigger 13, elements 14 and 15, address counter 16, signal activity analyzer 17, code comparison circuit 18, elements OR 19 and 20, address buffer registers 21, clock distributor 22, switch 23, demultiplexer 24, multiplexer 25, the pulse counter 26, the element AND 27 and the output block 28. The signal activity analyzer 17 may contain s, for example, transducers 29 error approximations tion, the analyzer 30 and the analyzer 31. The demultiplexer 30 outputs LxM where M -.chislo code bits, L address number - the number of registers 21.

The device works, the sequence is our, they are.

The input signals X (t) ... X (t) are connected to the input of switch 1, which is controlled by the first (1-n ,,) bits of the address counter 16. Counter 16 consists of () bits. If a binary counter is used, then n log, jN, n 2. 7 2n, + 15 where N is the number of input channels of the system. The counter 16 is started from the generator of 12 clock pulses through the element 14. Analog-to-digital converter (A / D converter) 2 sequentially codes the current values of the input signals. The output code of the A / D converter 2 is fed in parallel to blocks 3 and 4 of the buffer memory and the signal activity analyzer 17.

Blocks 3 and 4 operate alternately in write mode and read mode (Fig. 3), the control circuits for blocks 3 and 4 are the same. Elements 27 and 1 are used to form gating signals (Read / Write)

When recording information, and elements 6 and 8 - when reading. The elements OR 9 and 10 combine the outputs of elements 27 and 6 or 7 and B, respectively, for the shaping of read / write gates. The operation mode of blocks 3 and 4 is determined by the state of the last () -1 about the discharge of the counter 16. This output signal from the (n, + 1) - th digit of the counter 16 is fed to. input mode selection Read / write unit 4 and the inputs of the elements And 6 and 7, as well as through the inverter 11 to the input mode selection Read / write unit 3 and the inputs of the elements And 27 and 8. Inverter 11 causes the operation of blocks 3 and 4 in different modes. In the write mode, a write pulse is generated by the output signal of the A / D converter 2 End of conversion, which is fed to the inputs of And 27 and 7. In the read mode, a read pulse is generated at the output of the code comparison circuit 18 and fed to the inputs of And 6 and 8. The read pulse is gated generator pulse 12 clock pulses, which are fed through the element And 14 to the inputs of elements 6 and 8.

The address inputs of blocks 3 and 4 are paralleled by the signals- (NP) bits of the counter 16.

Recording mode Let the recording mode require signal 1

to the read / write mode selection input Then, with the zero signal being removed from the output of the () th 16th address (1st transmission frame), unit 3 will work in write mode, and unit 4 in read mode. In this case, a single signal is applied to the elements And 27 and 8, providing the ability to write to block 3 and read the contents of block 4, and the zero signal is applied to. elements 6 and 7, blocking the write pulses in block 4 and reading pulses on block 3..

In recording mode, multiple interrogation of input signals occurs. One polling cycle is provided by the cycle of operation of the first bits of the counter 15. The number of such cycles is determined by bits with (ni + 1) -ro in P.2-D. For a binary counter. For example, when N 32 we have n, 5, n., I.e. A frame consists of 64 cycles, each of which has 32 polling cycles of input signals. Therefore, required. in this example, the memory size is 2048 words, the word length is determined by the ADC resolution. With the arrival of the 12 () th pulse from the generator, the state of the last is changed (n + O-th digit of counter 16, which changes the operation mode, i.e. it writes to block 4 and reads from block 3.

To implement a read algorithm that provides a representation

In the first cycle of operation of the counter 26 (after switching the trigger 13), the first register 21, in which the address of one of the L most active signals is recorded, is connected to the input of the multiplexer 24 and, in turn, to the input of the output unit 28, which is opened by the inverse output of the last bit counter 26 dp transmission of this address to the communication line. For selection (identification) of address parcels

signals with different sampling rates, it is necessary to determine the signals-15 from the information addressing sprinkles that have the most dynamic are made longer. Rear activity. For this purpose, the simultaneous front of the address parcel is determined by recording the measurement control information signal sent to one of the buffer memory blocks by the output block 28 from the inverse output, the current active-20 last bit of the counter 26 is analyzed. channel. Dp this output is achieved, the necessary duration of the information code of the ADC 2 delivers the address parcel.

from the analyzer 17 controlled by the account- At the completion of each cycle by the counter 16 addresses synchronously from the switch (passing 2 pulses from the generator 1. At the end of each addressor block 25) the counter 26 by the pulse of the channel of the active control signals -. Filling through the OR 20 element with a jog pulse from trigger 13 switches the valve 22 and writes the line to the register 21. The contents are transferred to the line as follows. When the full frame is written to the memory, the state of the (n, + 1) -th bit changes yes, the trigger 13, controlled by the falling edge of the pulse from the penultimate bit of counter 16, closes AND 14, disconnects counter 16 from generator 12, rewrites the addresses of the most active channels to registers 21, sets distributor 22 through OR 19 element

Registrar 21. The outputs of the distribution 30 of the bodies 22 from the second to the (L + 1) -th are also connected to the switch 23, with which the user, before starting the operation of the system, sets the number of L channels transmitted with adaptation by frequency of the poll. This number should not exceed the number of hardware-provided registers 21.

After polling the distributor 22 of all selected registers 21 by the front-stroke pulses to the initial position, the demultiplexer 24 switches to the position of the output unit 28 and opens element 15. In this position of the trigger 13 pulses from generator 12 pass through element 15 to counter 26.

Counter 26 has n bits and the same structure as n bits of counter 16. Therefore, the cycle of counter 26 is equal to the polling cycle of N input signals determined by the cycle of operation of the first n bits of counter 16. By filling the counter 26 from its output Overflow through the element OR 20, a pulse is applied to the clock input of the distributor 22, the outputs of which connected to the inputs Reading the address registers 21 alternately give permission to connect the contents

Press the last to the input of the demultiplexer 24.

In the first cycle of operation of the counter 26 (after switching the trigger 13), the first register 21, in which the address of one of the L most active signals is recorded, is connected to the input of the multiplexer 24 and, in turn, to the input of the output unit 28, which is opened by the inverse output of the last bit counter 26 dp transmission of this address to the communication line. For selection (identification) of address parcels

5 from the information address dressings are made longer. The falling edge of the address burst is determined by the control signal supplied to the output unit 28 from the inverse output 0 of the last bit of the counter 26. This achieves the required duration of the address burst.

The second register 21. The outputs of the distributor 22 from the second to (L + 1) -th are also connected to the switch 23, with which the user, before starting the operation of the system, sets the number of L channels transmitted adapting to the polling frequency. This number should not exceed the number of hardware-provided registers 21.

After polling the distributor 22 of all selected registers 21 on the leading edge of the next (L + 1) -ro pulse, specified by switch 23, the distributor 22 through the element OR 19 is set to the initial state and resets by setting

the trigger input 13 to the main operating state, i.e. when the element And 14 is open, and the element And 15 is closed. This completes the session of transferring the addresses of the most active signals to the communication line. The combination of these address parcels in the system can personnel sync pulse. Thereafter, reading from block 3 and writing to block 4 begins.

To generate information control pulses from block 3, the first inputs of the code comparison circuit 18 feed the current state of the first bit of the counter 16. The second inputs of the circuit 18 through the multiplexer 25 are alternately supplied with signals from (n, + 1) through bits of counter 16, or through demultiplexer 2A, the addresses of the most active signals recorded in registers 21. The switching sequence of multiplexer 25 is determined by the control signal, which is removed from the () bit of counter 16. The same control signals through element LI 20 is supplied to the distributor 22, which switches the addresses of the transmitted active channels by connecting the registers 21 to the demultiplexer 24. The cycle of the distributor 22 is determined, as in the case of transferring addresses to the communication line, by the position of the switch 23, t . predetermined number of adaptive signals L.

When the codes on both inputs of the circuit 18 coincide, the last control pulse that permits the passage of the strobe from the generator 12 through the elements AND 6 and OR 9 to the gate input Read / write block 3. At the same time, the element 8 is closed with zero potential output inverter 11.

Claims (1)

Invention Formula An adaptive telemetering system of the IZI transmitter, containing a switch whose information inputs are the device inputs the switch output is connected to the input of an analog-digital converter, the first outputs of which are connected to the information inputs of the first block of the buffer memory, the outputs of which are the device outputs, and the control unit , characterized in that, in order to increase the information content and accuracy of the device, a second buffer memory block is inserted into it and the control block is executed on the multiplexer, demultiplexer, address counter, pulse distributor, switch, buffer registers, io-pulse counter, pulse generator, signal activity analyzer, trigger, output block, AND elements, OR elements, inverter and code comparison circuit, the pulse generator input is connected to 0 5 o five d 5 Q the first inputs of the first and second elements And the output of the first element And connected to the first inputs of the third and fourth elements And the input of the address counter, the output of the second element And connected to the input of the pulse counter, the first and second outputs of which are connected to the first inputs of the first, respectively the OR element and the code block, the outputs of which are connected to the outputs of the device, the first outputs of the address counter are connected to the control inputs of the switch, the first inputs of the code comparison circuit and the address inputs of the analyzer signal activity, the information inputs of which are connected to the first inputs of the analog-digital converter, the outputs of the signal activity analyzer are connected to the first inputs of the same buffer registers, the outputs of which are combined and connected to the first inputs of the demultiplexer, the first and second outputs of which are connected - respectively to the second inputs of the output the block and the first inputs of the multiplexer, the outputs of which are connected to the corresponding second inputs of the comparison circuit, the output of which is connected to the second moves of the third and fourth elements AND, the outputs of which are connected to the first inputs of the second and third elements OR, respectively, the second outputs of the address counter are connected to the corresponding second inputs of the multiplexer, the third input of which is combined with the second input of the first OR element and connected to one of the second outputs of the address counter , the third output of which is connected to the third input of the third element I, the first input of the fifth element I, the input of the inverter and the first control input of the first block of the buffer memory, the output of the investment The rotor is connected to the third input of the fourth element I, the first input of the sixth element I and the first control input of the second block of the buffer memory; the output of the sixth element I is connected to the second input of the second IZH element whose output is connected to the second control input of the second block of the buffer memory , the output of the fifth element AND is connected to the second input of the third element OR, the output of which is connected to the second control input of the first block of the buffer memory, the first output of the trigger is connected to the second inputs of the first element And demultiplex ora and the buffer address registers and the first input of the fourth OR element, the output of which and the output of the first element OR are connected respectively to the first and second inputs of the pulse distributor, the output element and the first trigger input, the second output of which is connected to the second input of the second element AND, the second output analog-to-digital converter is connected to the second inputs of the fifth and sixth elements And, the first and second outputs of the address counter are connected to the address the ports of which, except for the last, connectors of the first and second blocks are buny with the third inputs of the corresponding memory, information inputs buffer registers, the first and second of which are connected to the first outputs a swarm of pins. a switch connected to a analog-to-digital converter, corresponding to the corresponding uy outputs of the second buffer memory block by turns, except for the first one, are distributed to the output of the device, l pulses and the second input of the fourth element and the first trigger input, the second output of which is connected to the second input of the second And element, the second output of the analog-digital converter is connected to the second inputs of the fifth and the sixth elements And, the first and second outputs of the address counter are connected to the address L ... KC W P1 2