SU1370611A1 - Device for measuring resistance and capacitance of electric and signalling networks relative to ground - Google Patents

Abstract

The invention relates to electrical measuring technology and serves to increase the noise immunity of the information signal transmitted over a monitored network from the spectrum of the monitoring signal. The device contains a pulse generator 1, a sample resistor 2, a capacitor 3, a software block 6, a block 7 for fixing levels. Introduction of a capacitor 4, a decoupling unit 5, a calculator 8, analog switches 9 and 10, indicators I and 12, a block (a 13 correction and the formation of new functional connections allow the use of a control signal of a special form. In the description are examples of the implementation of the pulse generator 1 , razbivayuschego block 5, program block 6, block 7 fixing levels, the calculator 8 and block 13 correction. 6 Cp. f-ly, 7 ill. with s /)

Description

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with

about

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phage. /

This invention relates to an electrical measurement test and can be used to measure the resistance and capacitance of electrical or signal networks with respect to earth.

The purpose of the invention is to increase the noise immunity of the information signal transmitted from a controlled signal spectrum over a controlled network through the use of a control signal of a special form.

FIG. 1 is a block diagram of the device; in fig. 2 is a diagram of a custom unit; in fig. 3 - functional program block diagram; in fig. 4 - functional block level fixing scheme; in fig. 5 - functional scheme of the calculator; in fig. 6 - functional block correction circuit; in fig. 7 - voltage diagrams at the main points of the device.

FIG. 1 denotes a pulse generator 1, an exemplary resistor 2, the first 3 and second 4 capacitors, the decoupling unit 5, the software unit 6, the level fixing unit 7, the calculator 8, the first 9 and the second 10 analog switches, the first 11 and the second 12 indicators, Correction unit 13, first 14 and second 15 terminals for connecting to the measurement object, the first output of generator 1 is connected to the first terminal of resistor 2, the second terminal of which is connected to the common bus, the second output of generator 1 is connected to the first terminal of first capacitor 3 whose second terminal connected to The first terminal 14, the first output of the program block 6 is connected to the first input of the level fixing unit 7, the second output of the program block is connected to the input of the generator 1, the first output i of the second capacitor 4 is connected to the second output of the generator 1, and the second to the second terminal 15, the third and fourth outputs of the software unit 6 are connected respectively to the second and third inputs of the level fixing unit 7, the first, second and third outputs of which are connected respectively to the first, second and third inputs of the correction unit 13, the first, second and third The first outputs of which are connected respectively to the first, second and third inputs of the calculator 8, the fourth, fifth and sixth inputs of which are connected respectively to the first, third and fifth outputs of software block 6, the sixth and seventh outputs of which are connected to the switching inputs of the first 9 and 10 second analog keys, the inputs of which are connected respectively to the first and second outputs of the calculator 8, and the outputs to the inputs of the first 11 and second 12 indicators respectively, the fourth input of the correction unit 13 is connected to retim output program unit 6, a fourth input levels fixing unit 7 connected to the output decoupling unit 5, the first and second inputs connected respectively to the first 14 and second 15 terminals.

FIG. 2, the first 16 and second 17 decoupling capacitors and the adder 18 are labeled; the first terminals of the first 16 and second 17 decoupling capacitors are connected respectively to the first and second inputs of the block 5 and the second to the first and second inputs of the adder 18, the output of which is connected to the output of block 5.

The program block (Fig. 3) contains a clock pulse generator 19, first to fifth delay elements 20-24, trigger 25 and first 26 and second 27 elements AND, the output of generator 19 is connected to the input of each of delay elements 20-24 and the counting input of the trigger 25, the inverse output of which is connected to the first inputs of the first 26 and second 27 And elements, the second inputs of which are connected to the outputs of the fourth 23 and fifth 24 delay elements, respectively; the outputs of the first 20, second 21 and third 22 delay elements are respectively connected seventh per the output and third outputs of block 6, the outputs of the first 26 and second 27 elements And are connected respectively to the fifth and sixth outputs of block 6, the fourth output of which is connected to the output of the fifth delay element 24 and the input of the generator 19.

FIG. 4, the first 28, second 29 and third 30 analog keys and the first 31, second 32 and third 33 analog memory elements are designated, the information inputs of the first 28, second 29 and third 30 keys are connected to the fourth output of block 7, the control inputs are respectively the first, second, and third inputs of block 7, and the outputs — to the inputs of the first 31, second 32, and third 33 memory elements, respectively, whose outputs are connected to the first, second, and third outputs of block 7, respectively.

The calculator 8 contains (Fig. 5) first to fourth differential amplifiers 34-37, scale 38 amplifier, adder 39, quad AO first dividing block 41, trigger 42, second 43 and third 44 dividing blocks, logarithmic amplifier 45, fourth block 46 dividing voltage source 47, the first 48 and second 49 analog switches and the integrator 50, the first input of the calculator 8 is connected to the inverting inputs of the first 34 and second 35 differential amplifiers, the non-inverting inputs of which are connected respectively to the second and third inputsthe calculator 8, the output of the first differential amplifier 34 is connected to the inputs of the quad 40, the scale amplifier 38 and the first input of the first dividing unit 41, the output of which is connected to the first input of the fourth differential amplifier 37, the output of which is connected to the input of the logarithmic amplifier 45, the source 47 the reference voltage is connected to the inverting input of the fourth differential amplifier 37, the information input of the first switch 48 and the first input of the adder 39, the output of which is connected to the second input of the calculator 8, the input is with the output of the second dividing unit 43, the first input of which is connected to the output of the fourth dividing unit 46, and the second to the second input of the first dividing unit 41, the first output of the calculator 8 and the output of the third dividing unit 44, the Bbrfi input of which is connected to the output 40, and the second with the output of the third differential amplifier 36, the inverting input of which is connected to the output of the second differential amplifier 35, and the non-inverting input to the output of the scale amplifier 38, the fourth and fifth inputs of the calculator 8 are connected to the inputs of the co respectively set to 1 and setting the flip-flop 42, whose inverse output is connected to the control input of the first switch 48, whose output is connected to the input of integrator 50, and

the information input of the second key 49, the control input of which is connected to the sixth input of the calculator 8 and the output to the output of the integrator 50 and the first input of the fourth dividing unit 46, the second input of which is connected to the output of the logarithmic amplifier 45.

FIG. 6 denote first to sixth analog switches 51-56, first to sixth analog memory elements 57-62, first 63, second 64 and third 65 differential amplifiers and trigger 66 with a counting input, with the information D1 inputs of the first 51 and fourth 54 keys connected to the first input of block 13, information inputs of the second 52 and fifth 55 keys are connected to the second input of block 13, information inputs of the third 53 and sixth 56 keys are connected to the third input of block 13, the outputs of the keys 5L-56 are connected respectively to the inputs of the elements 57- 62 memories, exits first 57, second 58 and third 59 elements of ty are connected to the inverting inputs of the first 63, second 64 and third 65 amplifiers, respectively; the outputs of the fourth 60, fifth 61 and sixth 62 memory elements are connected to the non-inverting inputs of the first 63, second 64 and 65 third amplifiers whose outputs are connected respectively to the first, second and third outputs of block 13, the fourth input of which is connected to the counting input of trigger 66, the direct output of which is connected to the control inputs of the first 51, second 52 and third 53 keys And inverted - with the control input of the fourth 54, fifth 55 and sixth 56 keys.

The device works as follows.

From generator 1, a test two-pole sawtooth voltage + E (t) (Fig. 7) is sequentially passed through an exemplary resistor 2 and capacitors 3 and 4 simultaneously to both poles of the monitored network. At the same time, the information signal Uj (t) is allocated to the isolation impedance (Fig.7), the voltage of which in operational form we write in the form

+ - P

Co + Cx

one

(I)

where GX С; // С

I / / (I

X

+ p

 X

- equivalent network capacity;

C + C is equivalent to the capacitance of exemplary capacitors; R, (C + C) - constant time

,- ten

, R; // R J

R x rk

P hr f x f

nor the transient charters of Lenin's network response to test exposure;

- equivalent co-15 network isolation resistance;

TO.

the rise rate of the edges of the test signal E (t). In temporary form, the voltage

U., (T) is written while

UK (t) ± К „cVc, x (-), (1 -,). (2)

Controlled insulation resistance is determined by the measured at fixed times t, and t n – t, the instantaneous values of the information signal U (t,) Ux and U (t) U. Indeed, these values based on (2) can be written as

and ,,, (1 -

and..

. , () - from where we have

one

 1 - / db.

where n tj / t, 1 is any real positive number.

With n 2, solving equation (4) is not difficult with hardware implementation. The value of insulation resistance is determined from the ratio

R,

(five)

/ k "/ - with; 72i ,, - and, /

The transformation equation (5) is invariant to the choice of the duration of the cycle of change. Methodical error is determined only by the error of settling the ratio n, 2.

5 10

15

20

25

thirty

35

40

d

. 50

This allows varying the measurement response over a wide range by changing the frequency of the test generator 1 without changing the pitch of the device to be set.

The information signal Ux (t) allocated at the poles of the monitored network is fed to both inputs of the coupling unit 5. At the same time, the differential component (relative to the network poles) of the signal, caused by changes in the operating voltage of the network and d, is mutually compensated at the output of the unit 5, and the sum of in-phase information signals is fed to the first input of block 7.

The measurement process is synchronized by software block 6, at the first output of which there is a sequence of pulses arriving at the input of generator 1 (Fig. 7) and the switching polarity of the sawtooth voltage fronts ± E (t), and at the seventh, first and third outputs of block 6 - pulses fixing the time points of measurement of instantaneous values of the information signal U, (t;) - the initial t (Fig. 76), t, (Fig. 7c) and, (Fig. 7d), arriving at the first, second and third inputs of block 7 respectively. Three instantaneous values of the voltage U (t,), where, 2,3, are memorized on the first, second and third outputs of block 7 for the duration of the measurement period T, (respectively, and (t), and (t,) and U (t,)).

The measured instantaneous values of the information signal are fed to the first, second and third inputs of correction block 13, where for the full measurement cycle (two generator half-periods 1) the modulus of their algebraic sum is determined. The outputs of block 13 then have voltage: UXQ / Ux (toi) / + / U (to ;,) / - on the ground; U, | U, (t ,, i) / - b / u, (t ,,; ,, ,,) / - on the second; U, / U, (t ,,;) / + / U, (t ,, i ,,) / - on the third.

This allows for two half-periods of operation of the device to compensate for the unipolar voltage of the measurement error at the output of the unit, due to the displacements of the zeros of the real circuit elements, as well as the infra-low-frequency common-mode sweep of the operating voltage of the network (Fig. 7).

Correction unit 13 is controlled by a sequence of clockwise

713

the bot of the device of impulses from the second output of the program block 6 (Fig. 7a). The signals from the first, second and third outputs of the block 13 correction arrive at the first, second and third inputs of the transmitter 8.

The calculator 8 determines the value of the monitored insulation resistance R based on the conversion equation (5), using as an argument the measured voltage drops of the information signal and, and X, and Ux2 (Fig. 7l) t

s, fU ,, s, „| ,,,

and. / and, s,

(6)

  2 g o I The capacity of the monitored network is determined on the basis of the algorithm derived from (3) and 5):

C. t

CZK

- WITH,

(7)

en / 1 -,

I K „/ g

R,

The parameter Ry calculated at the end of each measurement cycle is the argument of the transformation equation (7). Controlled fourth, fifth and sixth inputs of calculator 8 receive pulses synchronizing its operation, respectively, from the first (Fig. 7c), the third (Fig. 7d) and the fifth (Fig. 7e) outputs of the program block 6.

At the end of each measurement cycle, the voltage proportional to the insulation isolation R on the basis of (5), from the first output of the calculator 8 through the public key 9 goes to the indicator 11, and the second output of the calculator 8, the voltage proportional to the network capacity C based on (7), through the public key 10 enters the indicator 12. The keys are controlled from the sixth (Fig. 7g) and the seventh (Fig. 7h) outputs of the program block 6. In FIG. 7m, n shows time diagrams for establishing indications of indicators 11 and 12 during the measurement process.

The development of block 5 (Fig. 2) provides galvanic isolation of the device from the constant operating voltage of the controlled network. Through separation capacitors 16 and 17. In addition, the symmetrical connection of the device to both poles of the network provides the output

eight

adder 18 compensation of the differential component of the operating voltage of the network Upqg and voltage surges

ten

15

20

25

thirty

35

40

c

50

five

network poles in dynamic modes and in the on / off modes of the operating voltage. The in-phase (with respect to the poles of the network) information signal Uj (t) is doubled in this case.

Program block 6 (Fig. 3) works as follows. The clock pulse generator 19 generates a pulse sequence (Fig. 7a) of the synchronizing operation of the generator 1 and delay elements 20-24 of block 6. At the seventh, first and third outputs of the block, single pulses are generated at times t, and, respectively (Fig. 76, c, d), gating the process of fixing the instantaneous values of the information signal U (t) in lock 7. At the fifth and sixth outputs of the program block 6, the control pulses are received only in the even half-periods of the device operation, which is provided by the enable signal from the output gage 25 (fig. 7e) for elements 26 and 27. The pulses from the fifth and sixth outputs of block 6 (fig. 7g, h) control the keys 9 and 10, respectively, and allow the measured parameters R to pass at the end of each measurement cycle , and C to device output indicators. The pulses from the fourth output of block 6 synchronize the operation of the calculator 8 and the clock generator 19 (fig.7d).

In block 7 (Fig. 4), the three instantaneous values of the aperiodic information signal l (t,), U, (t,) and U, (C, 2.t,) are fixed via keys 28-30 to the inputs of elements 31- 32 analog memory respectively.

The calculator 8 (Fig. 5) implements the transformation equations (5) and (7). The first, second and third inputs of block 8 receive voltages proportional to the arguments of the system of equations (6), and the fourth, fifth and sixth inputs receive pulses, synchronizing its operation. At the same time, at the first and second outputs of the calculator 8, at the end of each measurement cycle, voltages are proportional to the current values of the monitored 913

Nbix are insulation resistances R and network capacity C, respectively.

The transmitter 8 operates as follows. The voltages U, and Z, which are the arguments of the transformation equation (5), are determined at the outputs of the first 3A and the second 35 differential amplifiers. The voltage proportional to the sought insulation resistance R is at the output of the system of decisive blocks: TO quad, mashard amplifier 38, third differential amplifier 36 and third block 4D, realizing the conversion algorithms (5).

The network capacitance C is determined at the second output of the calculator 8 as a proportional voltage based on the algorithm (7). At the same time, the denominator of the transformation equation (7) is determined at the output of the MJ system of decision blocks: the first division block 41, the fourth differential amplifier 37 and the logarithm amplifier 45. The arguments of the block system are the voltage U, the voltage is the result of calculating the equivalent insulation K the network from the first output of block 8 and the reference voltage and from the output of source 47., op,

The value of the numerator of the equation | (7;

is available at the output of the integrator 50 connected to the source 47 of the reference voltage during the interval T t, -tn.3TO is provided with a control C r 1 and

a locked key 48 and a trigger 42 with setup inputs controlled by clock pulses from the first and third outputs of the software block 6 (Fig. 76, c). Finally, the conversion algorithm (7) is implemented at the output of the system of decision blocks: the fourth 46 and second 43 blocks of division and adder 39. At the end of each half-period of measurement, integrator 50 is reset to the zero state by means of a key 49 controlled by a sync pulse from the fourth output of the program block 6 (fig.7d). This is necessary to prepare integrator 50 for a new half-period of measurement.

The correction unit 13 (FIG. B) is intended to compensate for the error voltage and (FIG. 7i) measure the levels of the information signal U (t) caused by the process being slow.

five

0 5 o

with

About h Q

five

ten

but the flowing redistribution of the operating voltage of the network between the poles in dynamic switching modes of consumers with asymmetrical isolation of the poles and the zero drift of real amplifying circuit elements. The correction is carried out in two half-periods of the circuit operation, and the keys 51-53 of block 13 are opened in even-half periods and the instantaneous values of the information signal} (t), U (t) and U) ((. T,) are memorized by elements 57-59 of the analog memory). respectively, and at odd values of U (), U, () and U, (. tV), keys 54–56 are memorized by elements of analog memory 60-62. The keys are controlled from the antiphase outputs of trigger 66 with counting input, switchable clock pulses from the second output of software block 6 (Fig. 7a). At the same time, the stored information The signals from the outputs of the first and second groups of elements 57-59 and 60-62 of analog memory are fed to the differential inputs of the corresponding amplifiers 63-65 in antiphase. This ensures a doubling of the level of information signals at the corresponding moments to, t ,, ,, measured to even and odd half-periods of operation of the device, and also compensates for the outputs of the differential amplifiers 63-65, the common-mode voltage of the error DOUJ (Fig. 7k).

Claims (7)

1. A device for measuring the resistance and capacitance of electrical and signal networks with respect to ground, comprising a pulse generator, an exemplary resistor, a first capacitor, a software unit, a level fixing unit, a first terminal for connecting to the measurement object, the first output of the pulse generator is connected to the first output of the reference resistor , the second output of which is connected to the common bus, the second output of the pulse generator is connected to the first output of the first capacitor, the second output of which is connected to the first terminal for for prison to the measuring object. The first output of the software block is connected to the first input of the level fixation block, the second output of the software eleven The unit is connected to the input of a pulse generator, characterized in that, in order to increase the noise immunity of the information signal transmitted from the controlled network from the spectrum of the monitored signal, a second capacitor, a decoupling unit, a correction unit, a calculator, the first and second analog keys, the first and the second indicator and the second terminal for connecting to the measurement object, the first output of the second capacitor connected to the second output of the pulse generator, and the second to the second terminal for connecting to The measurement program, the third and fourth outputs of the software block are connected respectively to the second and third inputs of the level fixing block, the first, second and third outputs of which are connected respectively to the first, second and third inputs of the correction block, the first, second and third outputs of which are connected respectively to the first , the second and third inputs of the calculator, the fourth, fifth and sixth inputs of which are connected respectively to the first, third and fifth outputs of the program block, the sixth and seventh outputs of which are connected s with switching inputs, respectively, of the first and second analog switches, whose inputs are connected respectively to the first and second outputs of the calculator, and outputs to the inputs of the first and second indicators, respectively, the fourth input of the correction block is connected to the third output of the program block, the fourth input of the level fixing block-g it is connected to the output of a development unit, the first and second inputs of which are connected respectively to the first and second terminals for connecting the measurement object, 2. The device according to claim 1, wherein the generator is designed as a generator of a two-pole saw-tooth voltage linearly varying in time. 3. The device according to claim 1, wherein the decoupling unit contains two decoupling capacitors and an adder, with the first terminals of the first and second decoupling capacitors 0 five 0 five 06 0 five 0 five 0 five eleven . 12 not, respectively, with the first and second inputs of the block, and the second respectively with the first and second inputs of the adder, the output of which is connected to the output of the block. 4. The device according to claim 1, which is: the program block contains a clock pulse generator, five delay elements, a trigger and two AND elements, and the clock pulse generator output is connected to the input of each of the delay elements and the counting input of the trigger, the inverse output of which is connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the outputs of the fourth and fifth delay elements respectively the first and third outputs of the block, the outputs of the first and second elements And are connected respectively to the fifth and sixth outputs of the block, the fourth output of which is connected to the output of the fifth delay element and the input generator clock., 5. The device according to claim 1, characterized in that the block for fixing the levels contains three analog keys and three analog memory elements, the information inputs of the first, second and third analog keys are connected to the fourth block input, the control inputs are respectively to the first, the second and third inputs of the block, and the outputs with the inputs of the first, second, and third analog memory elements, respectively, the outputs of which are connected respectively to the first, second, and third outputs of the block. 6. The device according to claim 1, wherein the calculator comprises four differential amplifiers, a scale-up and logarithmic amplifiers, four division blocks, a quad, an adder, a source of reference voltage, a trigger, two analog switches and an integrator the first input of the calculator is connected to the inverting inputs of the first and second differential amplifiers, the non-inverting inputs of which are connected respectively to the secondary 13 137061 eye and the third inputs of the calculator, the output of the first differential amplifier is connected to the inputs of the quad, the scale amplifier and the first input of the first dividing unit, the output of which is connected to the first input of the fourth differential amplifier, the output of which is connected to the input of a logarithmic amplifier, the output of the reference voltage source is connected with the digital input of the fourth differential amplifier, information input of the first analog switch and the first input of the adder, the output of which is connected to the second output the calculator’s house, and the input with the output of the second dividing unit, the first input of which is connected to the output of the fourth dividing unit, and the second to the second input of the first dividing unit, the first output of the calculator and the output of the third dividing unit, the first input of which is connected to the output of the quadrant, and the second - with the output of the third differential amplifier, the inverting input of which is connected to the output of the second differential amplifier, and those of inverting power - to the output of the scale amplifier, the fourth and fifth inputs of the calculator are connected to The signals are respectively set to 1 and set to O flip-flop, the inverse output of which is connected to the control input of the first analog switch, the output of which is connected to the integrator input and the information input of the second analog switch, the control input of which is connected to the sixth input of the calculator, and output - with the integrator output and the first input of the fourth division block, the second input of which is 5 o 0 five 114 dinene with a logarithmic amplifier output. 7. The device according to claim 1, that is, that the correction block contains six analog switches, six analog memory elements, three differential amplifiers and a trigger with a counting input, and the information inputs of the first and fourth analog switches are connected with the first input of the block, the information inputs of the second and fifth analog switches are connected to the second input of the block a, the information inputs of the third and sixth analog switches are connected to the third input of the block, the outputs of the first, second, third, fourth, fifth and sixth en The keys are connected to the inputs of the first, second, third, fourth, fifth and sixth analog memory elements, respectively; the outputs of the first, second and third analog memory elements are connected to the inverting inputs of the first, second and third differential amplifiers, the fourth outputs, the sixth and sixth analog memory elements are connected to the non-inverting inputs of the first, second, and third differential amplifiers, respectively, the outputs of which are connected respectively to the first, The second and -ipeTbHM outputs of the block, the fourth input of which is connected to the counting input of the trigger, the direct output of which is connected to the control inputs of the first, second and third analog keys, and the inverse one - to the control inputs of the fourth, fifth and sixth analog keys. FIG. 2 FIG. 0ut.5 l ..J ff3Ui.6 Phie. 7