SU1332316A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to computing and can be used in the construction of fast / 7y ' f Step fh (t) of operating analog-to-digital frequency conversion devices into code. The purpose of the invention is to increase the noise immunity of the multiplier. The proposed multiplier comprises a control block 1, a counter 2, a census node 3, a register 4, an adder 5, a counter 6, a delay element 7 and an output 8 with corresponding links. The device multiplies the input frequency by a factor, and the problem of suppressing noise is solved by static processing in real time of the current samples — code equivalents of the periods of the signal being converted. 2 Il. with S (L 00 so you oo sz

Description

The invention relates to computing and can be used in the construction of high-speed devices analog-to-digital frequency conversion in the code.

The purpose of the invention is to increase the noise immunity of the multiplier,

FIG. 1 is a functional diagram of the frequency multiplier; in fig. 2 - functional block diagram.

The frequency multiplier contains control block 1, first counter 2, census node 3, register 4, adder 5, second counter 6, delay element 7 and output 8, with the first input of control unit 1 connected to the multiplier information input, the second input of control unit 1 connected with the overflow output of the first counter 2, the bus multiplier start is connected to the third input of the control unit 1, the fourth input of which is connected to the bus multiplier stop, the first output of the control unit 1 is connected to the installation input of the first counter 2 in the single state, sec The output of control unit 1 is connected to the syncro input of register 4, the bit outputs of which are connected respectively to information inputs of adder 5, the inverse outputs of which are connected respectively to the installation inputs of the first and second counters 2 and 6, the third output of control unit 1 is connected to the enable input the first counter 2, the input of record 1 in the lower bit of which is connected to the fourth output of the control unit 1; the fifth output of which is connected to the input of the register write resolution 4; the sixth output of the control control unit 1 Inen with the control input of the rewriting node 3 and with the information recording input to the sign bit of the adder 5, the recording resolution of which is connected to the seventh output of the control unit 1, and the reset inputs of the adder 5 and the second counter 6 are connected to the eighth output of the control unit 1, nine the output of which is connected to the counting input of the second counter 6, the overflow output of which is connected, to the output 8 of the multiplier and through the delay element 7 to its own recording resolution input, the direct bit outputs of the first counter 2 are connected respectively but with the inputs of the first group of node 3 rewriting, inverse

0

the bit outputs of the first counter 2 are connected respectively to the inputs of the second group of the census node 3, the outputs of which are connected respectively to the information inputs of the register 4.

The control unit of the frequency multiplier contains the first trigger 9, the first element OR 10, the first element 11, the first delay element 12, the second element 13, the second trigger 14, the third element 15, the 16 clock pulse generator, the element NOT 17, even the fifth AND 18 element, first and second shift registers 19 and 20, counter 21, Permanent Memory Node (ROM) 22, AND 23 group of elements, second OR element 24, second support element 25, third OR element 26, third trigger 27, frequency divider 28 and the fourth and fifth elements OR 29 and 30, with the first input of the control unit 1 and connected to the first input of the first

5 And 11 elements, the second input of which is connected to the output of the first trigger 9, and the output of the first element AND And is connected to the first input of the second element And 13 and through the first delay element I2 to the input of the installation to 1 of the second trigger 14, the output of which is connected to the second input The second element And 13 and the first inputs of the third and fourth elements And 15 and 18, the second inputs of which are connected to the input

5 NE element 17 ns generator output 16 clock pulses, the second input of control unit 1 is connected to the first input of the fourth element OR 29 and to the installation input in I of the third trigger 27, the installation input in O of which is connected to the output of the fifth element OR 30, the first input p This element OR 30 is connected to the installation inputs of the counter 21, the first and second shift registers 19 and 20, and the second trigger 14, the installation input to 1 of the first trigger 9, the third input of the control unit 1, and the first input of the first element OR

0 10, the output of which is connected to the first output of the control unit 1, the second output of which is connected to the output of the second delay element 25, and the output of the second element I 13 is connected to the input

5 of synchronization of the first shift register 19, the extrinsic element of the third element 15 is connected to the control input of the first shift register 19, the first output of which is connected to the third output

0

five

31

control unit 1, the second input of the first element OR 10 is connected to the second output of the first shift register 19, the third output of which is connected to the counting input of counter 2 and the synchronization input of the second shift register 20, the control input of which is connected to the output of the HE element 17, the output the fourth element And 18 is connected to the input of a frequency divider 28, the output of which is connected to the second input of the fourth element OR 29, the output of which is connected to the fourth output of the control unit 1, the n bit outputs of the second shift register 20 are connected to the inputs the second element OR 24 and with the first inputs of elements AND 23 groups, the second inputs of which are connected respectively to the n output bits of the ROM 22, whose address inputs are connected respectively to the discharge outputs of the counter 21J (n + 1) -th discharge output of the second register The shift 20 is connected to the second input of the fifth element OR 30 and to the fifth output of the control unit 1, the sixth output of which is connected to the output of the third trigger 27, the output of the AND 23 group elements is connected to the inputs of the third element OR 26, the output of which is connected to the seventh output of the unit and 1 control, the eighth output of which is connected to the installation input 1 of the first trigger 9, the installation input O connected to the fourth input of the control unit 1, the ninth output of which is connected to the generator output 16 clock pulses, the output of the second element OR 24 connected to the input of the second delay element 25

Effective interference suppression is achieved on the basis of bandwidth reduction methods — signal averaging, integration, and aperiodic averaging. In this case, the specific content of the transformation depends on the operator W (p), which determines the form of the connection between the output and input signals. From the point of view of noise immunity, it is most expedient to assign to this operator a function of sliding integration of the input signal, when the input and output signals are related by

1 V

y (t) - x (g) ae,

 11 o

(one)

4: -T „

where T is the integration interval.

164

The interconnection of the output and input values in this case corresponds to the transfer function

1st

:R

RT.

(2)

Substituted in the expression, we teach the amplitude-phase characteristic

„(J,) .... (3)

five

0

five

50

50

§

From (3), using the Euler formula, we find the amplitude-frequency characteristic (AFC)

| "(H) | - about: 5yg--

Thus, as the analysis of the expression for the frequency response shows, in the case when the period of the original signal x (t) is a multiple of the interval T, the converter does not perceive the variable component x (t). This determines the intrinsic property of integrating converters to suppress periodic noise and reduce the level of high-frequency interference.

Thus, the task of suppressing the noise that causes the fluctuations of the fronts of the pulse signals is accomplished by statistical processing in real time of the current samples — code equivalents of -N periods of the conversion signal. J

In the proposed device, the averaging of current samples of code equivalents Nf. Is performed by implementing the expression

NT, K-1 + signj K (NT,), (5)

where Ny K and Nj K-1 - current average, respectively

on Km and (K-1) -th processing steps; - algorithm step; NT k is the code equivalent of the K-th period;

,. ,, + 1. if (Nr, K) -Nr -CK-l) 0; | -} if (N Kl-Nr K-13) 0.

If the step of the algorithm is changed; according to the law

, 2,3, ..., (6)

51332316

is optimal because the current average coincides with that defined as

live in this way

(with

Lcd i and n. to J.1 J

This algorithm is known as a discrete analogue of the integrator.

If jCK. in expression (5) takes constant values of p starting from the nth count, then the output signal is related to the input signal by the relation (1). In this case, the frequency response of this event is defined as (4), which determines the noise-resistant properties of the algorithm (5).

The frequency multiplier works as follows,

At the initial moment of time, the Start signal is provided to reset the triggers 9, 14 and 27, the counter 21, the shift registers 19 and 20 of the control unit 1. This signal also resets the adder 5 and the second counter 6 to the zero state. The trigger 9 of the control unit 1 is set to one. The signal then passes through the OR 10 element of the control unit 1 and enters the input of the installation of the counter 2 in a single state.

The impulse of the input sequence Fj, arriving at the first input of the control unit 1, passes through the open element 11 and through the control element 12 enters the S input of the trigger 14, which opens the element 15. Thus, the initial synchronization of the device operation with the input sequence is realized. Each pulse of the input sequence, starting from the second, through the open element I 13, records 1 to the low-order bit of the shift register 19, the pulses from the generator output 16 pulses (reference frequency) through the I element 15, after the trigger 14 is set to 1 State, begin to arrive at the control input of the register 19 shift. When this unit starts. successively advancing pulses of the reference frequency on the bits of the shift register 59, which ensures that its outputs form a sequence of control signals, the signal from the first output of the shift register 19, posting to the third output of the control unit 1, ensures that the contents of counter 2 are copied to register 4 (shift). The second control pulse from the first output of the control unit 1 provides, through the element OR 10, the setting of the counter 2 to one state. The third control pulse provides writing 1 to the low-order bit of the shift register 20 (at the input

synchronization) and increases the contents of the counter 21 (pulses) by one. Counter 21 completes the function of the count of samples, the outputs of which are connected to the address inputs

ROM 22, where the algorithm step values represented by binary codes are stored, Dn of the first reference, which follows from (6),, for the second reference, 5; for the third, 333, etc. Each of, K (l, m), is approximated by a binary number, i.e. is represented as the sum of the normalizing factors, multiples of the powers of two

, H - -1) j. but..

1G1

where a. - coefficient of fraction of binary discretes in the formation of a scientific research institute of a given value.

Thus, each sample determines the appropriate combination of units and the zero output of the ROM 22. In this case, the single outputs open

corresponding elements of the group of elements And. The unit, written in the low-order bit of the shift register 20, begins to move sequentially across all bits (the number of which

one more than the number of bit outputs of the ROM 22) pulses of the reference generator j arriving at the control input through the element NOT 17, which ensures the elimination of faults on the fronts

pulses with both shift registers. Each of the pulses, at vivihs at the output of the shift register 20, arrives at the second input of the corresponding element AND 23, -23 and simultaneously through the multi-input element OR 24 at the input of the delay element 25. In that case; if the i-th element of I 23- is open at the first input, then the pulse from the corresponding output of the register 20

the shift passes through the OR element 26 and goes from the seventh output of the control unit 1 to the control input of the sumator 5, ensuring that the current content is summed to its contents

register register 4. Delay element 25 provides a delay of pulses by a time sufficient for reliable census (summation) from register A to adder 5. Each pulse from the output of delay element 25 (second output of control unit 1) shifts the contents of register 4 by one bit d to the right, which ensures the division of the contents of register 4 into coefficients 2 °,, 2, ..., 2. After the register 20 of control block 1 generates n pulses, the contents of register 4 multiplied by the corresponding algorithm step are added to the contents of adder 5. The process of multiplying is to sequentially shift the contents of register 4 and choose to sum each individual quotient to adder 5

l

(NT.-NI.), for which a- 1. (n + +1) pulse of the register 20 of the control unit sets the zero state of the trigger 27 and translates the contents of the adder 5 into the counter 2 in the return code. In counter 2, the operation (N.-N-p.) And the determination of the sign of the difference are implemented. During the time interval equal to the current period of the input sequence, the open element AND 18, the frequency divider 28, and the OR element 29 are fed to the counter input 2 of the reference frequency FJ. The division factor of the divider 28 pulses is equal to the multiplication factor M of the device. If the case of NT T takes place - FJ NT, then the counter

m 1 3 111 2 is not overflowed and the trigger 27 blocks

Each control of its state does not change. The contents of counter 2 (pulses) are rewritten to register 4 through the census node 3 in the return code. In the case of e, if NT T, then by the end of the period IV, the counter 2 overflows, and the pulse formed at the output of its most significant bit arrives at the second input of the control unit 1, sets the trigger 27 to the opposite state and in addition, it passes through the OR element 29 and the fourth output of the control unit 1 to the counter input of counter 2. This provides for the elimination of the error that occurs when the return code is used instead of the additional code.

16, 8

Thus, at the time of the end of the next period T. of the input signal Fg, counter 2 records the difference IN module, and the difference sign is determined by the signal at the output of trigger 27. Then the contents of counter 2 are written to register 4, where multiplication I is multiplied by the corresponding value step algorithm j G The result of this operation is summed with the corresponding sign to the contents of the adder 5,

The described sequence of operations performed during the operation of the device provides for the calculation of the current average code equivalent of the input signal period in the following form: Nr, CK NTjK-ll + j K sign (NT,),

which coincides with the expression (5). Then, the averaged value of the code equivalent of the N period of the input signal is fed to counter 6, where its conversion is ensured. In this case, at the output of the multiplier, the pulse frequency is determined as

 f k b :: where is the averaged period of the signal being converted.

Thus, the pulse frequency of the output signal in the proposed device is proportional to the value of the frequency of the input signal, averaged over a given time interval

If the step of the algorithm after the j-ro sample (the period of the input signal Fg) is assumed to be constant, then the relationship between the input and output signals is determined by the expression (3). Consequently, the frequency response of the proposed device has zeros at certain points of the frequency axis, which determines the ability of the proposed structure to suppress periodic noise characterized by a line spectrum, as well as a reduction in the level of high-frequency noise in the high-frequency part of the spectrum of the useful signal.

Claims (1)

Invention Formula Frequency multiplier containing the first and second counters 913 recording, register, adder, delay element and control unit, the first input of which is connected to the information input of the multiplier S; the first input of the control unit is connected to the installation input of the first counter in one state; the second output of the control unit is connected to the synchronous input of the register; which are connected respectively to the information inputs of the adder, which is different in that, in order to increase the noise immunity of the multiplier, the forward bit outputs of the first counter are connected respectively to the inputs of the first g The groups of the census node, the inverse bit outputs of the first counter are connected respectively to the inputs of the second group of the census node, the outputs of which are connected respectively to the information inputs of the accumulator; the total outputs of the adder are connected to the installation inputs of the first and second counters; overflow output of the second counter is connected with the output of the multiplier and with the input of the delay element, the output of which is connected to the recording resolution enable input of the second counter, the third output of the control unit is connected to the input allowed write the first counter, the entry of the unit to the lower bit of which is connected to the fourth output of the control unit, the fifth output of which is connected to the write enable input of the register, the sixth output of the control unit is connected to the control input of the census node and The bits of the adder, the recording resolution of which is connected to the output of the control unit, and the reset input of the adder and the second counter are connected to the eighth output of the angler unit, the ninth output of which is soybean, with the counting input of the second the first counter is connected to the second input of the control unit, the third input of which is connected to the bus. The multiplier start, the bus stop of which is connected to the fourth input of the control unit, which contains the first, second and third triggers, first, second, third, fourth and fifth elements OR, first, second, third and fourth elements AND, first and second delay elements, clock pulse generator, NOT element, first and second -, 20 323 . -Q jc 35 45 50 55 30 40 1610 shift histories, a frequency divider counter, a permanent storage node, a group of elements AND, the third and fourth inputs of the control unit are connected respectively to the inputs of the settings in 1 and O of the first trigger, the installation input of which is connected to the first input of the first element OR, with the eighth output of the control unit, with the inputs of the settings in the zero state of the first and second registers of the shift, the inputs of the installations in O of the second trigger and the counter, the first input of the fifth OR element, the output of which is connected to the input of the installation in O of the third a trigger whose installation input l is connected to the second input of the control unit, combined with the first input of the fourth OR element, the output of which is connected to the fourth output of the control unit; the second input of the fourth OR element is connected to the output of the frequency divider, whose input is connected to the output of the fourth element And, the first input of which is connected to the first inputs of the second and third elements And and the output of the second trigger 5, the installation input into which is connected to the output of the first delay element, the input of which is connected to the second m input of the second element And the output of the first element And, the first input of which is connected to the output of the first trigger, the second input of the first element And connected to the first input of the control unit, the first output of which is connected to the output of the first OR element, the second input of which is connected to the second output of the first the shift register, the first output of which is connected to the third output of the control unit, the third output of the first shift register is connected to the counting input of the counter and the synchronization input of the second shift register, the synchronization input of the first A shift register is connected to the output of the second element I, the control input of the first shift register is connected to the output of the third element I, the second input of which is connected to the second input of the fourth element I, the ninth output of the control unit, the output of the clock generator and the input of the element HE 5 output which is connected to the control input of the second shift register, the output of the higher (n + 1) -th bit of which is connected to the second input the home of the fifth OR element and the fifth output of the control unit; the p outputs are connected to the first inputs of the group of elements AND and to the inputs of the second OR element, the output of which is connected to the second output of the control unit through the second delay element, the seventh output of which is element OR, inputs coReditor E, Papp 1 Compiled by V.V. Gusev I. Tehred Order 3833/44 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 133231612. Secondly, they are connected to the outputs of a group of elements And, the second inputs of which are connected respectively to the information outputs of the permanent memory node, whose address inputs are connected to the outputs of the counter, while the output of the third trigger is connected with the sixth output of the control unit. Proofreader M. Demchik