RU2562420C2 - Method for automatic control of output signal strength and system therefor - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: group of inventions relates to radio electronics and control systems and can be used to control the output signal strength of generators in a wide frequency range. A system for implementing the method consists of an analogue part and a digital part. The analogue part includes a strength control unit, a directional coupler, a diode detector and an amplifier. The digital part consists of a PLD, an ADC and a DAC.

EFFECT: enabling flexible adjustment of a control law in a controller and enabling the introduction of correcting parameters.

2 cl, 1 dwg, 1 tbl

Description

The invention relates to the field of electronics and control systems and is used to control the level of the output signal of the generators in a wide frequency range.

State of the art

To regulate the level of the output signal, both schemes with an analog controller implemented on the basis of an operational amplifier are used, as well as schemes with a digital controller implemented on a digital microcontroller based on software. A solution based on a digital controller has such an advantage as a software change in the coefficient of the controller when changing the control object, which does not require the use of additional external circuits. For a linear change in the level of the output signal, determined in dBm, with a linear change in the reference signal in the feedback circuit of the control system, logarithmic detectors are used, however, their frequency range does not cover the working range of the harmonic signal generators being developed.

A well-known analogue workstation system with similar capabilities is used in the Agilent PSG series generator. The system implements open loop, control signal hold, and regulator coefficient changes (Agilent Technologies PSG Signal Generators Service Guide, Part Number: E8251-90259, USA, December 2003).

The known system is analog, therefore, it has low extensibility and flexibility, in addition, the presence of many components increases the cost and complicates the development of the board, manual adjustment of the regulator parameters, fixed regulator coefficients.

A digital quadrature correction system for a vector generator is known, which contains a feedback loop consisting of a directional coupler, an envelope detector, an analog-to-digital converter (ADC), a processor, a digital-to-analog converter (DAC), and a controlled attenuator to adjust the signal level in front of the quadrature demodulator. Another chain digitizes the I-component of the signal of the modulating signal, and adjusts the level of the output signal using a controlled attenuator. Here, the digital control of the attenuator does not contain any additional modes and serves to adjust the output level. The calculation of the control signal is based on a comparison of the digitized signal with tabular values from the memory (US 6941118, IPC H03G3 / 20, publ. 19.04.2002).

SUMMARY OF THE INVENTION

The main technical problem to be solved with the help of the proposed solutions is the creation of a method and system for its implementation, allowing more flexible control of the control law in the controller, as well as making any correction parameters or correction chains in the digital part of the system.

In relation to the method, this task, in accordance with the invention, is solved by the features described in paragraph 1 of the claims. In relation to the system, this task, in accordance with the invention, is solved by the features described in paragraph 2 of the claims.

The method consists in comparing a digitized feedback loop signal with a digital setpoint signal.

 In accordance with the invention, the microwave signal is converted into a low-frequency signal, which is fed to the ADC, then the digitized signal is fed to a programmable logic integrated circuit (FPGA), which provides a linear change in the level of the output signal with a linear change in the set point, where it is compared with the set point, then, according to the implemented in FPGA control law, form the control signal and using the DAC convert the digital signal into analog.

 The system includes a series-connected directional coupler, diode detector, and ADC, forming a feedback loop.

 In accordance with the invention, the system is equipped with an FPGA, while the FPGA output is connected to the input of the DAC, the output of which is connected to the input of the level control unit, the output of which is connected to the input of the directional coupler, the output of which is connected to the input of the diode detector, the output of which is connected to the ADC input, the output which is connected to the input of the FPGA.

The drawing shows a structural level control system with digital control.

 The system consists of analog and digital parts 1 and 2. Analog part 1 includes a level 3 control unit, the output of which is connected to the input of the directional coupler 4, the output of which is connected to the input of the diode detector 5, the output of which is connected to the input of the amplifier 6. Digital part 2 consists of from FPGA 7, which is presented as a regulator 8 and a mismatch element 9, the ADC 10 and the DAC 11. The output of the mismatch element 9 is connected to the input of the controller 8, the output of which is connected to the DAC 11, the output of which is connected to the input of the level 3 control unit, and the output amplifier 6 is connected to the input of the ADC 10, the output of which is connected to the input of the mismatch element 8.

The implementation of the invention

The input of the analog part 1 of the system receives a microwave signal from the generator. Then this signal with the help of the control unit level 3 is converted into a signal of the desired level. Using a directional coupler 4, the high-frequency output signal is transmitted to the feedback circuit. Then, using the diode detector 5, the low-frequency envelope of the high-frequency signal is detected and transmitted to amplifier 6. Thus, the low-frequency signal is received at the ADC 10, where it is compared with a certain digitally set point. From the output of the mismatch element 9, an error signal is supplied to controller 8, which generates a control signal that is converted from digital to analog using the DAC 11. The computing unit in the digital part of the control circuit is FPGA 7, which, in addition to performing calculations, also controls the ADC 10 and DAC 11.

Since the level of the output signal, determined in dBm and in V, which are related by the ratio,

,

,

where U ₁ is the measured voltage, and U ₀ is the voltage taken as the reference voltage (at a reference power level of 1 mW at a nominal load of 50 Ohms), then a linear change in the setpoint will lead to a linear change in the level of the output signal defined in V, but non-linear, defined in dBm. To ensure a linear change in the level of the output signal determined in dBm, when the setpoint is changed linearly, the first software conversion implemented in FPGA 7 is applied. To obtain a dependence of the level of the output signal determined in dBm on the control signal determined in V, the feedback is opened. Experimentally remove the dependence, then fill in the next array of values. The experimental parameter measurements for the implementation of the first program transformation are presented in the table.

Setting value
Ref Desired desired power
P _desired Corresponding set point real power
P _real Found real setpoint value corresponding to the desired power
Ref _pre Ref (1) P _yellow (1) P _action (1) ... Ref (2) P _yellow (2) P _action (2) ... Ref (3) P _yellow (3) P _action (3) ...

Then, for each P _yellow (k), indices (i) and (i + 1) are found that satisfy the condition P _action (i) <P _yellow (k) <P _action (i + 1). After that, the value of Ref _prev (k) is calculated by linear interpolation according to the following formula:

.

.

, которой аппроксимирован участок между Ref(i) и Ref(i+1). Второе программное преобразование выполняется аналогичным образом и служит для преобразования полученных отсчетов АЦП к той же величине, к которой преобразовывается значение уставки. Коэффициенты для преобразования рассчитывают после экспериментального получения соответствия значений АЦП и установленного значения уставки.In this way, the converted values for a set of fixed setpoint values are found. Accordingly, using the algorithm of the first program conversion, the setpoint value is analyzed, compared with the available values in the FPGA memory, and if it lies between two values from the memory, the desired converted value is found by linear interpolation. An increase in the number of points increases the accuracy of the conversion, which requires more memory to store an array of values. To increase the speed of calculations, the memory does not store the values of Ref and Ref _prev , but the values of Ref and the coefficients k and b, which characterize the line

, which approximates the section between Ref (i) and Ref (i + 1). The second program conversion is performed in a similar way and serves to convert the obtained ADC samples to the same value to which the set value is converted. The coefficients for conversion are calculated after experimentally obtaining the correspondence of the ADC values and the set value of the set point.

The functionality of the control system also includes the ability to programmatically control the output of the DAC - it holds the current control signal, turns off the control signal for a time equal to the time of setting the new DAC value, as well as the mode of storing and restoring the control signal.

Claims (2)

1. A method of automatically adjusting the level of the output signal, which consists in comparing the digitized feedback loop signal with a digital setpoint signal, characterized in that the microwave signal is converted into a low-frequency signal, which is fed to an analog-to-digital converter (ADC), then the digitized signal is fed to a programmable logical integrated circuit (FPGA), with which the output signal level is linearly changed when the setpoint is changed linearly, where it is compared with the setpoint, then, according to the algorithm implemented in the FPGA a control signal is generated from the control and, using a digital-to-analog converter (DAC), the digital signal is converted into an analog signal. 2. The system of automatic control of the output signal level, including a series-connected directional coupler, a diode detector and an ADC forming a feedback loop, characterized in that the system is equipped with an FPGA, while the FPGA output is connected to the input of the DAC, the output of which is connected to the input of the level control unit which is connected in series with a directional coupler, a diode detector and an amplifier, the output of which is connected to the input of the ADC, the output of which is connected to the input of the FPGA, represented by an element A test, the output of which is connected to a regulator forming a control signal.