JP5106442B2 - Wireless transmitter using Cartesian loop - Google Patents

Description

  The present invention relates to a wireless transmission device using a Cartesian loop.

  In a wireless communication apparatus such as a portable wireless device, a transmission RF signal is amplified by a power amplifier in order to radiate a transmission RF (radio frequency) signal from an antenna on the transmission side. The power amplifier is required to maintain linearity so that the transmitted RF signal falls within the spectrum mask determined by the wireless system standard. Further, for example, the adjacent channel leakage power, which is one of the parameters defined in the wireless system standard, is mainly caused by the odd-order distortion of the power amplifier. Therefore, it is desirable to reduce the odd-order distortion.

  For example, a Cartesian loop is used to reduce the odd-order distortion and the like to improve the linearity of the power amplifier. The Cartesian loop is a feedback loop including a feedback path for demodulating a part of the power of the transmission RF signal by a quadrature demodulator to return it to a baseband I / Q signal and feeding back to the input of the quadrature modulator of the transmission unit. is there.

  More specifically, a part of the power of the transmission RF signal output from the power amplifier is guided to the feedback path of the Cartesian loop and input to the quadrature demodulator through the variable attenuator and the low noise amplifier. The feedback I / Q signal obtained by the quadrature demodulator is combined (added or subtracted) with the input I / Q signal. The combined I / Q signal is input to the quadrature modulator via the baseband amplifier. When the gain from the quadrature modulator to the quadrature demodulator is sufficiently larger than 1, the gain from the input end of the quadrature modulator to the output end of the power amplifier is determined by the attenuation amount of the feedback path of the Cartesian loop, and the transmission RF signal is linear. Depends on the linearity of the feedback path. Therefore, it is necessary to increase the linearity of the feedback path.

  On the other hand, since a portable wireless device operates using a built-in battery as a power source, a technique for reducing the power consumption of an IC is indispensable in order to reduce battery consumption and extend communication time. In the portable wireless device, the power consumption of the power amplifier of the transmission unit is the largest. The integration of radio units used in portable radio devices has progressed, and recently, it has become possible to manufacture from low frequency units to high frequency units using CMOS (complementary metal-oxide semiconductor) technology suitable for cost reduction. In general, when a power amplifier has a CMOS structure, the cost can be reduced, but the efficiency deteriorates. The Cartesian loop is a high linearization technique for the radio unit as described above, but may be considered as a technique for improving the efficiency of the power amplifier if the way of looking is changed. Therefore, the efficiency of the power amplifying unit or the radio unit can be improved by applying the Cartesian loop to the radio unit having the CMOS structure.

  Since the Cartesian loop has a feedback circuit, it is important how to ensure the stability of the operation. In order to ensure the stability of the Cartesian loop, in Patent Document 1, the phase of the feedback I / Q signal is detected with the Cartesian loop open, and the phase difference between the feedback I / Q signal and the input I / Q signal is detected. A method for controlling the phase of the local signal supplied to the quadrature demodulator in the feedback path has been proposed. However, Patent Document 1 does not assume that the power (transmission power) of the transmission RF signal is variable.

  When the Cartesian loop is used, the power consumption of the entire transmission device can be reduced even when the power consumption of the feedback circuit is taken into consideration when the output RF signal is high. On the other hand, at the time of low output of the transmission RF signal, the linearity of the power amplifier and the driver amplifier that drives the power amplifier is high, so that there is no need for high linearization by the Cartesian loop. If the Cartesian loop is working even at low output, the efficiency will drop due to the power consumption of the feedback circuit. Therefore, in order to efficiently perform transmission power control used in recent wireless systems, it is desirable to open and close the Cartesian loop according to the transmission power from the viewpoint of reducing power consumption.

Japanese Patent Laid-Open No. 10-136048

  When the Cartesian loop is opened and closed according to the transmission power, the transient response time from when the loop is closed until the transmission power reaches a predetermined value increases. For example, if the average output of the input I / Q signal before the loop is closed is set to 100 mV, the gain of the variable attenuator in the feedback circuit is set so that the average output of the feedback I / Q signal is 1000 mV. If this is the case, the transmission output when the loop is closed differs from the transmission power when the loop is open, so the time for the transmission power to converge after the loop is closed becomes long. When the operation of setting the transmission power by controlling the gain of the variable attenuator in the feedback path after the loop is closed, the convergence time of the transmission power becomes longer. In Patent Document 1, there is no concept of transmission power control, and therefore a method for shortening the convergence time of transmission power when the Cartesian loop is opened and closed is not disclosed.

  An object of the present invention is to shorten the transient response time until the transmission power reaches a predetermined value when the Cartesian loop is changed from the open state to the closed state.

  According to one aspect of the present invention, a combiner that combines an input I / Q signal to be transmitted and a feedback I / Q signal to generate a combined I / Q signal; and orthogonally modulates the combined I / Q signal; A quadrature modulator that generates a quadrature modulation signal; a power amplifier that amplifies the quadrature modulation signal and outputs a transmission RF signal; and a quadrature demodulation using a local signal for a feedback RF signal branched from the transmission RF signal A quadrature demodulator for generating the feedback I / Q signal; a switch for turning on / off the input of the feedback I / Q signal to the combiner; and a power capable of setting the power of the transmission RF signal An amplitude difference detector that detects an amplitude difference between the input I / Q signal and the feedback I / Q signal and generates an amplitude difference detection signal during a period in which the switch is off; and the switch In the off period, the input I / A phase difference detector for detecting a phase difference between a signal and the feedback I / Q signal to generate a phase difference detection signal; and normalizing the phase difference detection signal with the signal amplitude to obtain a normalized phase difference signal In order to generate, during the period when the signal amplitude of either the input I / Q signal or the feedback I / Q signal is larger than a reference value, the normalization is performed using the current value of the phase difference detection signal, A normalizer that performs the normalization using a value before the signal amplitude of the phase difference detection signal becomes smaller than the reference value when the signal amplitude becomes smaller than the reference value; the amplitude difference detection signal and the normalization A control signal that receives a phase difference signal and generates an amplitude control signal that minimizes the amplitude difference and a phase control signal that minimizes the phase difference under a state in which the power is set while the switch is off. A generator; and the switch And configured to generate at least one amplitude control signal that minimizes the amplitude difference and at least one phase control signal that minimizes the phase difference under a state in which the power is set during an off period. A control signal generator; a memory storing the amplitude control signal and the phase control signal; and adjusting an amplitude of the feedback RF signal according to the amplitude control signal stored in the memory during a period when the switch is on An amplitude adjuster that adjusts the phase of the local signal according to a phase control signal stored in the memory while the switch is on; and when the switch is off for a Cartesian loop A first loop gain is set, and a second loop gain higher than the first loop gain is set when the switch turns from off to on. Provided is a radio transmission apparatus using a Cartesian loop, which includes a gain setting unit for setting.

  According to another aspect of the present invention, a combiner that combines an input I / Q signal to be transmitted and a feedback I / Q signal to generate a combined I / Q signal; and orthogonally modulates the combined I / Q signal; A quadrature modulator that generates a quadrature modulation signal; a power amplifier that amplifies the quadrature modulation signal and outputs a transmission RF signal; and a quadrature demodulation using a local signal for the feedback RF signal branched from the transmission RF signal A quadrature demodulator that generates the feedback I / Q signal; a switch for turning on / off the input of the feedback I / Q signal to the combiner; and the power of the transmission RF signal can be set An amplitude difference detector that detects an amplitude difference between the input I / Q signal and the feedback I / Q signal and generates an amplitude difference detection signal in a period in which the switch is off; While the switch is off, the input I A phase difference detector for detecting a phase difference between a Q signal and the feedback I / Q signal to generate a phase difference detection signal; and normalizing the phase difference detection signal with the signal amplitude. To generate a normalized phase difference signal by filtering the phase difference detection signal with the low-pass filter. The low-pass filter is configured to change a cutoff frequency according to the signal amplitude. A normalizer that receives the amplitude difference detection signal and the normalized phase difference signal, and an amplitude control signal that minimizes the amplitude difference under a state in which the power is set while the switch is off; A control signal generator for generating a phase control signal for minimizing the phase difference; and at least one amplitude for minimizing the amplitude difference under a state in which the power is set during a period when the switch is off. A control signal generator configured to generate a control signal and at least one phase control signal that minimizes the phase difference; a memory storing the amplitude control signal and the phase control signal; An amplitude adjuster that adjusts the amplitude of the feedback RF signal in accordance with the amplitude control signal stored in the memory during the period; and the locality in accordance with the phase control signal stored in the memory during the switch on period A phase adjuster that adjusts the phase of the signal; and a Cartesian loop that sets a first loop gain when the switch is off and is higher than the first loop gain when the switch turns from off to on Provided is a radio transmission apparatus using a Cartesian loop, which includes a gain setting unit for setting a second loop gain.

  According to the present invention, it is possible to shorten the transient response time of the transmission power particularly when the Cartesian loop is changed from the open state to the closed state. Therefore, even in a wireless communication system that requires transmission power control, the Cartesian loop can be opened and closed according to the transmission power, so that power consumption can be reduced. Further, since the phase difference signal can be extracted with high accuracy, the time required for averaging can be reduced, and high-speed phase difference calibration becomes possible.

1 is a block diagram showing a wireless transmission device according to an embodiment of the present invention. The figure which shows the other example of the termination method of the output of a power amplifier Diagram explaining controller functions Block diagram showing a specific example of a controller The figure which shows the relationship between an input I / Q signal and a feedback I / Q signal Block diagram showing another specific example of the controller Flow chart showing processing procedure in calibration mode Flow chart showing processing procedure in transmission mode Schematic showing a feedback system for explaining the Cartesian loop Diagram showing transient response when Cartesian loop is closed and transient response when transmission power is changed while Cartesian loop is closed Flowchart showing the processing procedure in startup calibration mode Flowchart showing processing procedure in transmission mode after startup calibration mode FIG. 5 is a block diagram showing a part of a wireless transmission device using analog feedback according to another embodiment of the present invention. Circuit diagram showing a specific example of a variable attenuator Circuit diagram showing interface with process variation compensation Circuit diagram showing local signal supply path for quadrature demodulator Circuit diagram showing specific example of phase shifter Circuit diagram showing another specific example of phase shifter Circuit diagram showing amplitude / phase detection circuit Circuit diagram of difference detection circuit Circuit diagram showing specific examples of polarity reversing switch and baseband amplifier Circuit diagram showing another specific example of polarity reversing switch and baseband amplifier Block diagram showing some details of the phase comparator Block diagram showing a first example of an amplitude normalizer included in a phase comparator 24 is a circuit diagram showing a specific example of the divider in FIG. Block diagram showing a second example of an amplitude normalizer included in the phase comparator Block diagram showing a third example of an amplitude normalizer included in the phase comparator Block diagram showing a fourth example of an amplitude normalizer included in the phase comparator Block diagram showing a fifth example of an amplitude normalizer included in the phase comparator

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
A radio transmission apparatus according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, modulated input I / Q signals I and Q to be transmitted from a baseband processing unit (not shown) or a controller 40 are input to input terminals 11 and 12, respectively. The input I / Q signals I and Q are combined (added or subtracted) with feedback I / Q signals FI and FQ described later by the combiners 13 and 14 to generate a combined I / Q signal. The combined I / Q signal is amplified by the baseband amplifier 15 and input to the quadrature modulator 16. The baseband amplifier 15 is preferably a variable gain amplifier, and further includes a filter function for ensuring the stability of the wireless transmission device as necessary.

  The quadrature modulator 16 phase-shifts the original local signal having the frequency fLO from the mixers 17 and 18 and the local oscillator 20 to generate a quadrature local signal, that is, two local signals having phases different from each other by 90 °. Have In the mixers 17 and 18, each of the combined I / Q signals from the baseband amplifier 15 is multiplied by each of the orthogonal local signals. In the quadrature modulator 16, the output signals of the mixers 17 and 18 are further added to generate a quadrature modulation signal.

  The quadrature modulation signal output from the quadrature modulator 16 is input to the power amplifier 23 via the variable attenuator 21 and the driver amplifier 22, and is amplified to the required power level by the power amplifier 23 to generate a transmission RF signal. The The transmission RF signal is supplied to the antenna 25 through the power coupler 24 that is a power branching device, and is radiated from the antenna 25 to the space. Hereinafter, the power of the transmission RF signal is referred to as transmission power.

  The output terminal of the power amplifier 23 is appropriately terminated by the antenna switch 26 via a termination element, in this example, a resistor R. It is also possible to use another linear element instead of the resistor R as the termination element. In FIG. 1, the output terminal of the power amplifier 23 is terminated to the ground GND of the radio via a resistor R. However, when an isolator 37 is connected to the output terminal of the power amplifier 23 as shown in FIG. The output terminal of the isolator 37 can be terminated with a resistor R or the like. Hereinafter, for the sake of simplicity, the case where the output terminal of the power amplifier 23 is terminated as shown in FIG. 1 will be described as an example.

  In the power coupler 24, a part of the transmission power is branched and a feedback RF signal is generated. The feedback RF signal is input to the quadrature demodulator 30 via the variable attenuator 27 and the low noise amplifier 28. The variable attenuator 27 is used as an amplitude adjuster for adjusting the amplitude of the feedback RF signal.

  The quadrature demodulator 30 phase-shifts the original local signal of the frequency fLO1 supplied from the mixers 31 and 32 and the local oscillator 20 via the variable phase shifter 29 to obtain a quadrature local signal, that is, two local signals having phases different by 90 °. It has a 90 ° phase shifter 33 that generates a signal. The variable phase shifter 29 is used as a phase adjuster for adjusting the phase of the orthogonal local signal. In the mixers 31 and 32, feedback I / Q signals FI and FQ are generated by multiplying the input feedback RF signal and each of the orthogonal local signals.

  The feedback I / Q signals FI and FQ are fed back to the combiners 13 and 14 via the switch 34 having a polarity inversion function. The Cartesian loop is composed of a power coupler 24, a variable attenuator 27, a low noise amplifier 28, a phase demodulator 30, a feedback path by the synthesizers 13 and 14, and a synthesizer 13 and 14 to a baseband amplifier 15 to a quadrature modulator 16. A feedback loop including a transmission path by the power amplifier 23 is configured. The switch 34 is provided to open / close the Cartesian loop, specifically to turn on / off the input of feedback I / Q signals FI and FQ to the combiners 13 and 14. If the switch 34 is on, the Cartesian loop is closed, and if the switch 34 is off, the Cartesian loop is open.

Further, an amplitude difference detector 35 that detects an amplitude difference between the feedback I / Q signals FI and FQ and the input I / Q signals I and Q, and the feedback I / Q signals FI and FQ and the input I / Q signal I , Q is provided to detect a phase difference by comparing the phase with Q. The amplitude difference detector 35 outputs an amplitude difference detection signal V ^D A indicating the amplitude difference between the feedback I / Q signals FI and FQ and the input I / Q signals I and Q, and the phase comparator 36 provides feedback. A phase difference detection signal V ^D θ mainly representing a phase difference between the I / Q signals FI and FQ and the input I / Q signals I and Q is output. In order to distinguish from a normalized phase difference signal CPHS described later, V ^D θ will be referred to as a composite phase difference detection signal.

  The amplitude difference detector 35 and the phase comparator 36 will be described in detail later. The phase comparator 36 includes a phase difference detector, an amplitude normalizer, and a limiter as will be described later.

  When calibration is performed, the switch 34 is turned off, that is, the Cartesian loop is opened. Hereinafter, the state in which the switch 34 is off is referred to as a calibration mode. When transmitting a signal, the switch 34 is turned on, that is, the Cartesian loop is closed. Thereby, feedback by the Cartesian loop is performed. This state is referred to as a transmission mode. For example, as shown in FIG. 3, the controller 40 is configured to mainly control the Cartesian loop. FIG. 2 shows that the various control signals shown in FIG.

That is, the amplitude control signal VA from the controller 40 to the variable attenuator 27, the phase control signal Vθ to the variable phase shifter 29, the variable phase shifter 29, the switch 34, the amplitude difference detector 35, and the phase comparator 36. The polarity switching signal p / m is output. The amplitude difference detection signal V ^D A from the amplitude difference detector 35 and the composite phase difference detection signal V ^D θ from the phase comparator 36 are input to the controller 40. Further, the controller 40 also outputs input I / Q signals I and Q and a control signal AS to the antenna switch 26. If the types of signals used as the input I / Q signals I and Q can be controlled by the control from the controller 40, the controller 40 may not necessarily output I and Q.

(Specific example 1 of the controller 40)
FIG. 4 is a specific example of the controller 40, and includes a control signal generator 41, a digital-analog converter (DAC) 42, an analog-digital converter (ADC) 43, and a memory 44. The digital value control signal generated by the control signal generator 41 is converted into an analog signal by the DAC 42, whereby an amplitude control signal VA and a phase control signal Vθ are generated. The amplitude control signal VA is supplied to the variable attenuator 27, and the phase control signal Vθ is supplied to the variable phase shifter 29.

On the other hand, the amplitude difference detection signal V ^D A from the amplitude difference detector 35 and the composite phase difference detection signal V ^D θ from the phase comparator 36 are taken into the ADC 43 and converted from an analog signal to a digital value. The memory 44 is connected to the control signal generator 41 and the ADC 43 and stores the amplitude difference detection signal and the composite phase difference detection signal converted into digital values by the ADC 43, or stores the stored amplitude difference detection signal and the composite phase difference detection signal. Is output to the control signal generator 41.

(Specific example 2 of the controller 40)
According to another specific example of the controller 40, the ADC 43 is removed as shown in FIG. 5. Instead, the ADC 43 is built in the amplitude difference detector 35 and the phase comparator 36. Here, the ADC 43 is shared by the amplitude difference detector 35 and the phase comparator 36, but may be incorporated in the amplitude difference detector 35 and the phase comparator 36, respectively. According to the example of FIG. 5, the digital value amplitude difference detection signal and the composite phase difference detection signal are output from the amplitude difference detector 35 and the phase comparator 36 and are directly taken into the memory 44.

  Although not shown in FIGS. 4 and 5, the controller 40 further includes a mode setting unit 45, a loop gain setting unit 46, and transmission power for selectively setting the calibration mode and the transmission mode as shown in FIG. A setting unit 47 is provided.

  In this embodiment, in order to shorten the response time due to the opening and closing of the Cartesian loop, it is aimed to minimize the difference in signal amplitude between the respective parts before and after the feedback. That is, the signal amplitude after feedback by the Cartesian loop is estimated, and the signal amplitude is set before closing the Cartesian loop and applying feedback. In order to achieve such processing, the amplitude and phase are adjusted before applying feedback by the Cartesian loop in the following procedure.

(Calibration mode)
Hereinafter, a processing procedure in the calibration mode will be described with reference to FIG. The procedure of FIG. 6 is controlled by the controller 40.

  When the calibration mode is started, the Cartesian loop is opened by turning off the switch 34 (step S101). At this time, the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is terminated by the resistor R using the antenna switch 26 so that the transmission RF signal is not output from the antenna 25. The antenna switch 26 is supplied with a control signal AS for controlling whether to terminate the output terminal of the power amplifier 23 or the output terminal of the isolator 37 from the controller 40.

  In the controller 40, the desired transmission power (Pi) set by the power setting unit 45 is recognized. The desired transmission power Pi is set by setting the attenuation of the transmission variable attenuator 21 in accordance with Pi when the Cartesian loop is open by the controller 40 (step S102). At this time, if the transmission power is the maximum output, the transmission RF signal is distorted, but there is no particular problem even if the distortion is large in the calibration mode.

  A feedback RF signal that is a part of the power of the transmission RF signal is input to the quadrature demodulator 30 via the power coupler 24, the variable attenuator 27, and the low noise amplifier 28, and feedback I / Q signals FI and FQ are generated. . The amplitude difference detector 35 detects the amplitude difference ΔA between the feedback I / Q signals FI and FQ and the input I / Q signals I and Q, and the controller 40 supplies the variable attenuator 27 so that the amplitude difference ΔA is minimized. Amplitude control signal VA is set.

Here, the amplitudes of the input I / Q signals I and Q are defined by the root of I ² + Q ² , and the amplitudes of the feedback I / Q signals FI and FQ are defined by the root of FI ² + FQ ² . Here, for simplicity, the amplitudes of the input I / Q signals I and Q are I ² + Q ² , and the amplitudes of the feedback I / Q signals FI and FQ are FI ² + FQ ² .

In order to make the amplitudes of the feedback I / Q signals FI and FQ equal to the amplitudes of the input I / Q signals I and Q, the amplitude difference detection signal V ^DA output from the amplitude difference detector 35 approaches 0. In addition, the attenuation amount of the variable attenuator 27 is controlled by the controller 40. Here, V ^D A is expressed by the following formula (1).

The amplitude difference detection signal V ^D A may be calculated by multiplying the right side of Equation (1) by a constant. Formula (1) is a case where the constant multiplied by the right side is 1.

As shown in FIGS. 4 and 5, when the amplitude control signal VA supplied from the controller 40 to the variable attenuator 27 is an analog signal generated by the DAC 42, the control signal generator 41 is generated when the amplitude control signal VA is generated. The digital value input to the DAC 42 is sequentially increased or decreased. As a result, an amplitude control signal VA that monotonously increases or decreases (this is referred to as an amplitude calibration control signal) is generated, and the amplitude of the feedback RF signal is adjusted by the amplitude calibration control signal (step S103). Accordingly, the amplitude difference detector 35 detects the amplitude difference between the feedback I / Q signal and the input I / Q signal, and outputs the amplitude difference detection signal V ^D A. The amplitude calibration control signal closest to the zero cross point of the amplitude difference detection signal V ^D A, that is, when V ^D A switches from positive to negative or from negative to positive, gives a desired amplitude adjustment amount. As a result, the amplitude of the transmission RF signal and the amplitude of the feedback RF signal become substantially equal. In other words, the loop gain described later is approximately 1. The amplitude calibration control signal closest to the zero cross point of the amplitude difference detection signal V ^D A is used as the amplitude control signal VA that minimizes the amplitude difference between the feedback I / Q signal and the input I / Q signal.

  The amplitude control signal VA thus generated is converted into a digital value by the ADC 43, and stored in the memory 44 for use in the next phase adjustment and in the subsequent transmission mode (step S104). The digital value stored in the memory 44 is read out at the time of the next phase adjustment, and is set in the variable attenuator 27 through the control signal generator 41 and the DAC 42.

  After the amplitude control signal VA is stored in the memory 42 in step S104, the variable phase shifter 29 is controlled by the phase control signal Vθ output from the controller 40 based on the phase difference θ detected by the phase comparator 36. Thereby, the phase of the local signal supplied to the quadrature demodulator 30, in other words, the phase of the feedback I / Q signal is adjusted (step S105).

FIG. 7 shows the input I / Q signals I and Q and the feedback I / Q signals FI and FQ on the IQ plane. It is assumed that I ² + Q ² = FI ² + FQ ² by the attenuation amount control of the previous variable attenuator 27. Since the phase difference between the vector (I, Q) and the vector (FI, FQ) is θ,

It becomes.

When the phase difference detection signal PHS representing the phase difference θ between the input I / Q signals I and Q and the feedback I / Q signals FI and FQ is FI × Q−FQ × I, the PHS is as follows.

On the other hand, in order to detect that the phase difference θ is shifted by 0 or π, the following code detection signal PL is defined.

When FI ² + FQ ² >> 0, when the phase difference detection signal PHS is near 0, the phase difference θ is near 0 or near π. In order to determine this difference, the value of PL in equation (5) is referred to. When θ is near 0, PL is positive, and when θ is near π, PL is negative.

  In order to detect θ = 0 °, the phase control signal Vθ is sequentially increased, and the values of the phase difference detection signal PHS and the sign detection signal PL are detected. When the phase control signal Vθ supplied from the controller 40 to the variable phase shifter 29 is an analog signal output from the DAC 42, the digital value input from the generator 41 to the DAC 42 when the phase control signal Vθ is generated is Increased or decreased sequentially. As a result, a monotonously increasing or monotonically decreasing phase control signal Vθ (this is referred to as a phase calibration control signal) is generated, and in this process, the phase calibration control signal that makes the phase difference detection signal PHS substantially 0 ° is fed back to the feedback I / Q. It is obtained as a phase control signal Vθ that minimizes the phase difference θ between the signal and the input I / Q signal. Further, the polarity of the feedback I / Q signals FI and FQ fed back to the combiners 13 and 14 is controlled by the switch 34 in accordance with the sign of the sign detection signal PL at this time. In FIG. 1, the polarity of the feedback I / Q signals FI and FQ can be set by the polarity switching signal p / m output from the controller 40. If the sign detection signal PL is positive, the polarity of the feedback I / Q signals FI and FQ is set to be positive, and if PL is negative, the polarity of the feedback I / Q signals FI and FQ is set to be negative.

  The phase control signal Vθ, which is a phase calibration control signal in the vicinity of θ = 0 obtained by the above operation, is converted into a digital value by the ADC 43 and stored in the memory 44 as a digital value for use in a later transmission mode (step S106), the calibration mode ends.

Here, FI ² + FQ ² >> 0 is assumed. However, if FI ² + FQ ² >> 0 is not satisfied, the value of the phase difference detection signal PHS is close to 0 even if it is not close to θ = 0 °. Therefore, if the calibration is performed using the modulation signal, that is, the input I / Q signals I and Q without using the tone signal having a constant amplitude, the detection error of the phase difference θ increases. However, since FI ² + FQ ² is positive, the polarity can be accurately determined. In order to reduce the detection error of the phase difference θ, normalization is performed by dividing the phase difference detection signal PHS by, for example, the amplitude FI ² + FQ ² of the input I / Q signal, so that sin θ that does not depend on the amplitude signal of the transmission wave The normalized phase difference signal CPHS, which is a signal of That is, the normalized phase difference signal CPHS is

Wherein _{A 1} is a coefficient, in represented.

Using the normalized phase difference signal CPHS shown in Expression (6), for example, the value of the phase control signal Vθ that becomes close to θ = 0 ° according to the successive approximation method is stored in the memory 44. This is the calibration mode. The composite phase difference detection signal V ^D θ means a pair of the standardized phase difference signal CPHS and the code detection signal PL.

  To summarize the operation of the calibration mode described above, in a state where the Cartesian loop is open, first, the variable attenuator 27 is set so that a predetermined loop gain (here, loop gain 1) is obtained in the vicinity of a desired transmission power (Pi). Is adjusted. Next, the phase control signal Vθ given to the variable phase shifter 29 is adjusted so that the phase difference between the feedback I / Q signal and the input I / Q signal is 180 °. By performing the phase adjustment after the amplitude adjustment, the phase adjustment can be performed with high accuracy.

(Transmission mode)
Next, a processing procedure in the transmission mode will be described with reference to FIG. The procedure of FIG. 7 is also controlled by the controller 40. When the transmission mode starts, the amplitude control signal VA and the phase control signal Vθ are loaded from the memory 44 and set in the variable attenuator 27 and the variable phase shifter 29 (step S201). Next, the Cartesian loop is closed by turning on the switch 34 (step S202). However, at this time, the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is terminated via the resistor R as necessary.

  Thereafter, the loop gain is increased (step S203), and transmission is performed (step S204). At the same time as the Cartesian loop is closed in step S201, the switch 26 is switched to stop terminating the output terminal of the power amplifier 23 or the output terminal of the isolator 37, and set to connect to the antenna 25 instead. Alternatively, considering the transient response time, the termination of the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is stopped after the Cartesian loop is closed and delayed by the transient response time.

Next, the significance of the loop gain increase process in step S203 will be described. The Cartesian loop is a two-dimensional loop of I and Q. For simplicity, it is considered as a one-dimensional loop, and a one-dimensional feedback system as shown in FIG. 9 is assumed. In general, in the feedback system, if the gain (bare gain) of the amplification stage is G, the feedback rate is β, the input is I / Q, and the output is Out, the following relationship is established.

  The gain after feedback is represented by G / (1 + Gβ). Gβ is called the loop gain. Since the denominator becomes 0 when 1 + Gβ = 0, the feedback system becomes unstable. 1 + Gβ = 0 is a state when Gβ is 1 and the phase is rotated 180 ° when the feedback signal is subtracted from the input signal. Even in the Cartesian loop, it is necessary to apply feedback under the condition that there is no frequency at which such a state exists. In this embodiment, when the Cartesian loop is closed, 1 + Gβ = 2 is obtained, and not only the gain is halved but also the improvement in distortion cannot be expected.

  On the other hand, when the above-described calibration mode is completed and the mode is changed to the transmission mode and the Cartesian loop is closed and feedback is performed, a state equivalent to the state of Gβ = 1 shown in FIG. 9 is obtained. Therefore, in the procedure of FIG. 8, after loading the amplitude control signal VA and the phase control signal Vθ corresponding to the transmission power set in advance in step S201, the Cartesian loop is closed in step S202, and the loop gain Gβ is set in the next step S203. It is larger than 1 and the influence of G is reduced. Specifically, the switch 34 is turned on to change from the Cartesian loop open state to the Cartesian loop closed state with a predetermined polarity, and then the loop gain Gβ is increased.

  The adjustment target for changing the loop gain Gβ is G corresponding to the gain from the baseband amplifier 15 to the power amplifier 23, and it is desirable not to change β. This is because β corresponds to the gain when the Cartesian loop is applied, and changing this changes the gain to be set. In the present embodiment, in order to increase the gain G, the gain of the baseband amplifier 15 is increased by the loop gain setting unit 46 as shown in FIG. Here, since the loop gain Gβ when the Cartesian loop is open is 1, the gain change of the baseband amplifier 15 becomes the entire loop gain.

  Assuming that the loop gain is sufficiently larger than 1, the desired transmission output is determined by the attenuation amount (amplitude adjustment amount) of the variable attenuator 27 in the feedback path set when the Cartesian loop is opened in the calibration mode. By setting the amplitude adjustment amount, the amplitudes of the feedback I / Q signals FI and FQ become equal to the amplitudes of the input I / Q signals I and Q. Therefore, the input terminals 11 and 12 to the output terminal of the power amplifier 23 are used. The gain (the gain of the transmission output with respect to the input I / Q signals I and Q) is equal to the gain of the feedback path of the Cartesian loop (the reciprocal of the attenuation). Therefore, it is not necessary to adjust the transmission output after the Cartesian loop is closed.

  When the processing of step S203 is performed, the amplitude of the feedback I / Q signal is set to substantially the same amplitude as when the Cartesian loop is open, so that the transient response time when the Cartesian loop is closed is further shortened.

  FIG. 10 shows a transient response (T1) of the transmission power when the Cartesian loop is closed without performing the process as described in FIGS. 6 and 8, and when the transmission power is changed while the Cartesian loop is closed. The transmission power transient response (T2) when the transmission power is set after the Cartesian loop is closed is shown. According to the present embodiment, these transient responses can be improved.

(Transmission end processing)
Next, processing at the end of transmission will be described. At the end of transmission, the transmission baseband signals I and Q are ramped down to reduce transmission power. When the transmission power drops to a predetermined level, the Cartesian loop is opened by turning off the switch 34. Next, the operation of the Cartesian loop is stopped, and the loop gain increment is restored. For example, the loop gain can be returned to the original 1 by returning the gain of the baseband amplifier 15 to the setting before the feedback by the Cartesian loop.

(Transmission power change processing)
Next, processing when changing transmission power will be described. When the transmission power level is set to be smaller than a certain level, linearization by the Cartesian loop is not required, so the operation of the Cartesian loop is stopped. In this case, the same sequence as that when the transmission is stopped is taken.

  Alternatively, in the first step, the switch 34 is turned off to open the Cartesian loop, and the gain G is lowered. That is, the loop gain increment performed to reduce the gain deviation is restored. As an example, the gain of the baseband amplifier 15 is restored. Next, in the second step, the Cartesian loop is stopped.

  When the transmission power level is changed but Cartesian loop operation is required, the following is performed. After performing the procedure up to the first step, the procedure for the calibration mode described in FIG. 6 is followed to set the transmission power simulating the gain change in a state where the Cartesian loop is open, and the phase adjustment is performed. . Thereafter, the mode shifts to the transmission mode. Alternatively, β may be lowered to a predetermined level while maintaining the transmission mode, and the gain G of the amplification stage may be increased by the amount β is lowered.

  According to the calibration mode shown in FIG. 6, the amplitude and phase are adjusted immediately before the transmission operation shown in FIG. Therefore, it is assumed that the test is performed in an open loop in order to always capture the amplitude control signal and the phase control signal before applying the Cartesian loop or changing the transmission power.

  On the other hand, the other calibration modes described below are aimed at further shortening the calibration time before transmission, and the calibration mode is installed when the wireless transmission device is started or the wireless transmission device is mounted. It is assumed to be performed at the time of shipping inspection of an integrated circuit (IC). Therefore, although the calibration mode described below is referred to as start-up calibration for convenience, it is not necessarily limited to being performed at start-up.

(Startup calibration mode)
FIG. 11 shows a processing procedure in the startup calibration mode. 11 is different from FIG. 6 in that the transmission output is changed stepwise, and the amplitude control signal VA and the phase control signal Vθ at each transmission output are adjusted and stored.

  First, when the calibration mode is started, the Cartesian loop is opened by turning off the switch 34 (step S111). At this time, the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is terminated by the resistor R using the antenna switch 26 so that the transmission RF signal is not output from the antenna 25.

  Next, after setting i = 1 in step S112, the transmission power Pi is set (step S113). Initially, Pi = 1 is set. Thereafter, similarly to steps S103 to S106 of FIG. 6, the amplitude adjustment of the feedback RF signal (step S114), the storage of the amplitude control signal VA (step S115), and the phase adjustment of the feedback I / Q signal (local signal) (steps) S116) and storage of the phase control signal Vθ (step S117).

  Until it is determined in step S118 that i has reached I, i is incremented by 1 in step S119, and the processes in steps S113 to S117 are repeated. At this time, in the transmission power setting step S103, every time i is incremented by 1, the transmission power increases in 1 dB steps, for example. Thus, the amplitude control signal VA and the phase control signal Vθ adjusted for each transmission output are stored in the memory 44, and the start-up calibration mode ends.

(Transmission mode)
Next, a process when a Cartesian loop is applied during transmission after the start-up calibration described with reference to FIG. 11 is performed will be described with reference to FIG. First, the switch 34 is turned off and the operation starts with the Cartesian loop open, and a desired transmission power Pi is set (step S211).

  In steps S115 and S117 of FIG. 11, the amplitude control signal VA and the phase control signal Vθ at each transmission power Pi (i = 1 to I) are stored in the memory 44. Therefore, the amplitude control signal VA and the phase control signal Vθ corresponding to the transmission power set in step S211 are loaded from the memory 44 and set in the variable attenuator 27 and the variable phase shifter 29 (step S212). However, at this time, the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is terminated via the resistor R.

  Thereafter, after a predetermined time has elapsed, the switch 34 is turned on to close the Cartesian loop (step S213). At this time, termination of the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is stopped.

  Next, as in step S203 of FIG. 8, for example, the gain of the baseband amplifier 15 is set high to increase the loop gain (step S214), and transmission is started (step S215).

  Since the transmission end process and the transmission power change process are the same as described above, description thereof will be omitted. However, when the transmission power is changed and the operation of the Cartesian loop is required, the switch 34 is turned off as the first step, the Cartesian loop is opened, and the gain G is lowered as the second step. That is, the loop gain increment is restored. Since the amplitude control signal VA and the phase control signal Vθ are already stored in the memory 44, after the Cartesian loop is operated according to the procedure up to the second step, transmission may be performed according to the procedure of FIG. 12 at a predetermined transmission power. . Alternatively, β may be lowered to a predetermined level while maintaining the transmission mode, and the gain G of the amplification stage may be increased by the amount β is lowered.

In the start-up calibration mode described with reference to FIG. 11, first, an initial value is given to the digital value of the control signal generated by the control signal generator 41 in the controller 40 shown in FIG. 4 or FIG. In this state, the amplitude difference detection signal V ^D A and the composite phase difference detection signal V ^D θ obtained by the amplitude difference detector 35 and the phase comparator 36 are stored in the memory 44 as digital values via the ADC 43.

Next, the digital value of the control signal is incremented by, for example, one step, and the amplitude difference detection signal V ^D A and the composite phase difference detection signal V ^D θ obtained by the amplitude difference detector 35 and the phase comparator 36 at that time are similarly changed. It is stored in the memory 44 as a digital value. Similar processing is repeated a predetermined number of times (N times). Thus among the digital values of the stored in the memory 44 the amplitude difference detection signal V ^D A, or V ^D A shown in Equation (1) becomes 0, or the value closest to this is selected, this control signal generation The amplitude control signal VA is generated by being taken into the device 41.

On the other hand, among the digital values of the composite phase difference detection signal V ^D θ stored in the memory 44, the code detection signal CPHS shown in the equation (6) becomes a predetermined code, or the PHS shown in the equation (4) is 0. Or a value closest to this is selected, and this is taken into the control signal generator 41 to generate the phase control signal Vθ. Of the digital values of the amplitude difference detection signal V ^D A and the composite phase difference detection signal V ^D θ stored in the memory 44, unnecessary information, for example, information other than the digital value of the selected detection signal may be discarded.

Since the above-described method is based on feedback performed through the controller 40, it is referred to as an adjustment method using digital feedback. Here, it is assumed that V ^D A, PHS, and CPHS shown in equations (1), (4), and (6) are obtained as analog signals, but I, Q, FI, and FQ are shown in FIG. 5, for example. Alternatively, V ^D A, PHS, and CPHS may be obtained by digital calculation after being converted into digital values by the ADC 43.

  As described above, in the first embodiment, the amplitude control signal and the phase control signal that minimize the amplitude and phase errors are obtained under the condition that the Cartesian loop is open and the desired transmission power is set. Is generated and stored in the memory 44. At the time of transmission, the amplitude control signal and the phase control signal are loaded from the memory 44, and the variable attenuator 27 for adjusting the amplitude of the feedback RF signal and the variable shift for adjusting the phase of the local signal used for orthogonal demodulation in the feedback circuit. Set in phaser 29. Therefore, since the difference in transmission power between when the Cartesian loop is open and when it is closed can be reduced, the transient response time of the transmission power when the Cartesian loop is changed from the open state to the closed state is effectively shortened.

(Second Embodiment)
In the first embodiment, feedback control is performed via the controller 40 in the amplitude adjustment and phase adjustment methods in the calibration mode by digital feedback. However, it is also possible to generate the amplitude control signal and the phase control signal necessary in the transmission mode only by analog processing without using the controller 40 in the calibration mode. However, since the control signal obtained by analog processing is an analog signal, it is necessary to capture the analog control signal into the controller 40 for the later transmission mode, convert it to a digital value by the ADC 43, and store it in the memory 44.

  Hereinafter, a method of generating an amplitude control signal and a phase control signal by analog feedback as a second embodiment of the present invention will be described with reference to FIG. FIG. 13 shows a part in common with FIG. 1 and switches 51 and 52 in the newly added control signal feedback loop. In the calibration mode, the amplitude control signal VA and the phase control signal Vθ are generated as follows.

  First, a method for generating the amplitude control signal VA by analog feedback will be described. The switch 34 in the feedback circuit of the Cartesian loop is turned off, and the output terminal of the power amplifier 23 or the output terminal of the isolator 37 is terminated, and the variable attenuator 27 in the feedback path of the Cartesian loop includes the power amplifier 23. A small amount of power branched from the transmitted RF signal is input as a feedback RF signal. It is also assumed that the Cartesian loop feedback circuit has already been powered on. When adjusting the amplitude of the feedback RF signal, the switch 51 is turned on and the switch 52 is turned off. It is assumed that a predetermined reference control signal is applied to the variable phase shifter 29 when the switch 52 is off.

In the amplitude difference detector 35 and the phase comparator 36, the processing of the expression (1) is performed by analog processing on the input I / Q signals I and Q and the feedback I / Q signals FI and FQ as in the first embodiment. Done. As a result, the analog amplitude difference detection signal V ^D A (or a signal that is a constant multiple of V ^D A) is input to the variable attenuator 27 as an amplitude control signal VA (referred to as an amplitude calibration control signal). That is, the stable point of VA can be approximated to the point of FI = I and FQ = Q by the feedback loop of the variable attenuator 27, the low noise amplifier 28, the quadrature demodulator 30 and the amplitude difference detector 35.

For example, if the signal amplitude of the input terminal RXIN of the variable attenuator 27 is large and the amplitude of the vector of (FI, FQ) is sufficiently larger than the amplitude of the vector of (I, Q), V ^D A becomes a large positive value, and this V ^D A is fed back to the amplitude control signal VA to the variable attenuator 27. Here, it is assumed that the variable attenuator 27 is designed so that the amount of attenuation increases as the amplitude control signal VA increases. Since a large V ^DA is input as the amplitude adjuster VA, the amount of attenuation of the variable attenuator 27 increases. As a result, the amplitude mM becomes smaller and converges at a value almost equal to the amplitude M. The converged amplitude mM value is captured as a digital value via the ADC 43 in the controller 40 and stored in the memory 44. Thereafter, the switch 51 is turned off, and the amplitude control signal VA is input from the controller 40 to the variable attenuator 27. This will be described later.

  Next, a method for similarly generating the phase control signal Vθ by analog feedback will be described. At the time of phase adjustment, the switch 51 is turned off and the switch 52 is turned on. When the switch 52 is turned on, a phase control loop including the variable phase shifter 29, the quadrature demodulator 30 and the phase difference adjuster 36 is formed.

  In this phase control loop, the phase difference θ between the vector of (FI, FQ) and the vector of (I, Q) is detected by equation (4). If the vector of (FI, FQ) and the vector of (I, Q) are in phase or out of phase, sin θ = 0 is satisfied, and convergence occurs at that point. However, since it cannot be distinguished whether θ is 0 ° or π, the distinction is made by the value of cos θ in the equation (5). If cos θ is positive, it is determined to be 0 °, that is, in-phase, and if it is negative, it is determined to be π, that is, opposite phase. The value of Vθ and the value of cos θ obtained in this way are taken in the controller 40 via the ADC 43 and stored in the memory 44.

  When the Cartesian loop is closed, the switch 34 is turned on and the polarity of connection is selected by the switch 34 in accordance with the polarity of cos θ. On the other hand, regarding the phase control signal Vθ, after the switch 52 is turned off, the same voltage as the voltage detected by the ADC 43 is generated as the phase control signal Vθ via the control signal generator 41 and the DAC 42.

  The values of the amplitude control signal VA and the phase control signal Vθ thus stored in the memory 44 are used in the transmission mode. The amplitude control signal VA stored in the memory 44 is also used when adjusting the phase control signal Vθ during calibration.

  Here, the controller 40 will be described. As shown in FIG. 13, the DAC 42 of the controller 40 is connected to the variable attenuator 27 and the variable phase shifter 29 via the switches 53 and 54, and the ADC 43 is connected to the amplitude difference detector 35 and the switches 51 and 52. The phase comparator 36 is connected. When the switch 51 is turned on, the amplitude control signal VA is taken into the memory 44 via the ADC 43 of the controller 40, and when the switch 52 is turned on, the phase control signal Vθ is taken into the memory 44 via the ADC 43. . At the start of the transmission mode, the amplitude control signal VA is loaded into the variable attenuator 27 by turning on the switch 53, and the phase control signal Vθ is changed via the DAC 43 by turning on the switch 54. 29 is loaded.

Next, specific examples of each component in the Cartesian loop in the first and second embodiments will be described.
(Specific example of variable attenuator)
FIG. 14 shows a specific example of a variable attenuator. In FIG. 14, a block surrounded by a broken line is a dummy attenuator, and a block indicated by ATT is an attenuator having the same circuit as the dummy attenuator. The dummy attenuator is a variable attenuator including MOSFETs M1-M5 and resistors R1, R2. Since the attenuator ATT has the same configuration as the dummy attenuator, it is assumed that MOSFETs M1-M5 and resistors R1, R2 exist.

  The MOSFETs M1, M2, and M3 form a path that shunts the signal to the ground GND, and controls the amount of the signal that flows to the ground GND. On the other hand, the MOSFETs M4 and M5 form a through path and control the amount of signal transmitted to the next stage circuit. The resistor R1 is used to transmit a direct current component to the gate terminals of M4 and M5.

  One ends of resistors RB and RT are connected to the + input terminal of the operational amplifier OP1, the other end of RB is connected to the power supply VDD, and the other end of RT is connected to the ground GND. One end of the other resistor RB is connected to VDD, and the other end is connected to the drain terminal of the MOSFET M5 of the dummy attenuator. One end of the other resistor R is connected to GND, and the other end is connected to the source terminal of MOSFET M4 of the dummy attenuator. The common terminal of the two resistors R1 of the dummy attenuator is connected to the output terminal of the operational amplifier OP1 and the common terminal of the resistor R1 of the attenuator ATT. The gain control signal VC1 is supplied to the gate terminals of the MOSFETs M1, M2, and M3 in the dummy attenuator and the attenuator ATT.

  According to the configuration of FIG. 14, the gain control signal VC1 and the gain (= OUT / IN) of the attenuator ATT exhibit the characteristic of dB linearity (linear-in-dB). “A DC-10 GHz Linear-in-dB Attenuator in 0.13um CMOS Technology,” IEEE 2004 CICC, pp.609-612.

(Threshold variation compensation interface)
In the variable attenuator shown in FIG. 14, when the threshold variation (Vth fluctuation) due to the process variation of the MOSFET occurs, the resistance of the MOSFET changes even if the gain control signal VC1 is constant. This is because the output resistance of the MOSFET depends on a value obtained by subtracting the threshold voltage Vth from the gate-source voltage VGS. Also, in the variable phase shifter to be described later, the threshold value variation of the MOSFET may become a problem.

  FIG. 15 shows an example of a circuit that compensates for such a threshold variation of the MOSFET. The threshold value variation compensating circuit of FIG. 15 is, for example, one or both of the input side of the amplitude control signal VA of the variable attenuator 27 in FIG. 13 and the input side of the phase control signal Vθ of the variable phase shifter 29 in FIG. Inserted as an interface.

  The circuit of FIG. 15 basically compensates for variations in threshold voltage of MOSFET M1 using reference voltage Iref × Rref generated by reference current Iref and reference resistor Rref and control current Icnt (Icnt1, Icnt2). Composed. Here, the control current Icnt represents the amplitude control signal VA or the phase control signal Vθ as a current signal.

  When the switch SWA1 is ON and the switch SWA2 is OFF, only Icnt1 out of the two control currents Icnt1 and Icnt2 flows through the switch SWA1 to the MOSFET M1. The reference voltage Iref × Rref is applied to the non-inverting input terminal of the operational amplifier OP1, the output terminal of OP1 is connected to the gate terminal of the MOSFET M1, and the drain terminal of M1 is connected to the inverting input terminal of OP1. By such a feedback system, the drain voltage of MOSFET M1 is controlled to be equal to the reference voltage Iref × Rref. Therefore, if the threshold voltage Vth of the MOSFET M1 increases, the gate-source voltage VGS of the M1 automatically increases by the increase of Vth, and the threshold variation is compensated.

Next, the reason why the two switches SWA1 and SWA2 and the two control currents Icnt1 and Icnt2 are used will be described. According to the second embodiment shown in FIG. 13, in the calibration mode and the phase adjustment mode, the amplitude difference detection signal V ^DA from the amplitude difference detector 35 is given to the variable attenuator 27 as the amplitude control signal VA, In the calibration mode, the composite phase difference detection signal V ^D θ from the phase comparator 36 is given to the variable phase shifter 29 as the phase control signal Vθ. On the other hand, in the transmission mode, the digital value stored in the memory 44 from the controller 40 is output via the DAC 42 to the amplitude control signal VA and the phase control signal Vθ, and is supplied to the variable attenuator 27 and the variable phase shifter 29.

  As described above, particularly in the case of the second embodiment shown in FIG. 13, the control signal path to the variable attenuator 27 and the variable phase shifter 29 is different between the calibration mode and the transmission mode. When the threshold value variation interface of FIG. 15 is used, two control signal paths can be formed for the variable attenuator 27 and the variable phase shifter 29, respectively.

  In FIG. 13, switches 51 and 52 are provided, but these can be substituted by, for example, the switch SWA1 of FIG. On the other hand, on / off of SWA2 in FIG. 15 corresponds to turning on / off the transmission of the amplitude control signal VA and the phase control signal Vθ from the controller 40 to the variable attenuator 27 and the variable phase shifter 29, for example.

Therefore, by turning SWA1 on and SWA2 off in the calibration mode, the variable attenuator 27 is supplied with the amplitude difference detection signal V ^DA from the amplitude difference detector 35 as the amplitude control signal VA, and the variable phase shift. The complex phase difference detection signal V ^D θ from the phase comparator 36 is supplied to the comparator 29 as the phase control signal Vθ. On the other hand, in the transmission mode, when SWA1 is turned off and SWA2 is turned on, the amplitude control signal VA from the controller 40 is given to the variable attenuator 27, and the phase control from the controller 40 is given to the variable phase shifter 29. The signal Vθ is given.

(Local signal supply path for quadrature demodulator)
As shown in FIGS. 1 and 13, the local signals from the local oscillator 20 are supplied to the mixers 31 and 32 of the quadrature demodulator 30 via the variable phase shifter 29 and the 90 ° phase shifter 33. FIG. 16 shows a local signal supply path for the quadrature demodulator 30 and shows portions corresponding to the variable phase shifter 29 and the 90 ° phase shifter 33 in detail.

  In FIG. 16, the local signal LO from the local oscillator 20 is input to the cascaded phase shifters PS1 and PS2. The amount of phase shift of the phase shifters PS1 and PS2 varies depending on the phase control signal VPSC. The relationship between the phase control signal VPSC and the phase control signal Vθ in FIG. 1 will be described later. The local signal output from the phase shifters PS1 and PS2 is input to the flip-flop FF via the buffer circuit CKBUF.

  In the flip-flop FF, the input local signal is divided by two, and two local signals having a phase difference of 90 ° are generated. The two local signals output from the flip-flop FF are supplied to the mixers 31 and 32 in the quadrature demodulator 30 through the I local buffer ICKBBUF and the Q local buffer QCKBUF, respectively. Since the frequency of the LO signal is halved at the output of the flip-flop FF, the local oscillator 20 needs to generate a local signal having a frequency twice that of the local signal required by the quadrature demodulator 30. On the other hand, instead of the flip-flop FF, for example, a 90 ° phase shifter by RC-CR using a differentiator and an integrator may be used. In this case, the frequency of the local signal at the input / output of the 90 ° phase shifter is May be equal.

  The phase shifters PS1 and PS2 receive the polarity switching signal Pmθ, and the polarity, that is, the phase of the local signal input by the Pmθ can be changed by 180 °. As described above, assuming that the flip-flop FF that performs frequency division by 2 is used as the 90 ° phase shifter subsequent to the phase shifters PS1 and PS2, the mixer 31, The phase of the local signal supplied to 32 can be changed by 90 °. Such phase adjustment of the local signal by Pmθ is effective when, for example, the variable range of the phase shifters PS1 and PS2 decreases due to a process error.

(Specific example of phase shifter 1)
FIG. 17 shows a specific circuit example of the phase shifters PS1 and PS2 in FIG. The phase shifter shown in FIG. 17 has MOSFETs M1 to M5 and capacitors C1 to C4, and phase-shifts the differential signals input to the input terminals + VIN and −VIN and outputs them from the output terminals + VOUT and −VOUT. A phase shift circuit is formed by C1, M3, C2, C3, M4, and C4. The current source I1 is a phase shift circuit by a common-mode level setting circuit composed of a differential pair of M1 and M2 connected to a common source terminal and M5, M6, R1 and R2 connected to drain terminals of M1 and M2. Drive circuit is formed.

  The MOSFETs M3 and M4 operate as variable resistors whose resistance values are changed by the phase control signal VPSC. In order to use the linear region of the MOSFET similarly to the attenuator in the variable resistor, the drain-source voltage VDS, the gate-source voltage VGS, and the threshold voltage Vth are VDS <VGS-Vth in M3 and M4. It is set to satisfy the system. In order to widen the control range by the phase control signal VPSC, it is desirable that the potential of the drain terminal of the MOSFET M4 and the source terminal of the M3 are close to the power supply potential or the GND potential. For this reason, the DC potential of the drain terminal of M4 is blocked by the capacitor C3, and the DC potential of the source terminal of M3 is blocked by the capacitor C2.

  On the other hand, the capacitor C4 forms a CR circuit together with the resistance of the MOSFET M4, and the capacitor C1 forms a CR circuit together with the MOSFET M3. A CR bridge circuit is formed by these two CR circuits. Therefore, when the resistance values of M4 and M3 are changed by the phase control signal VPSC, the phase of the local signal is changed.

  In order to explain the operation of this phase shifter, it will be described below how the output phase changes depending on whether the resistances of the MOSFETs M3 and M4 are large or small. When the resistances of M3 and M4 are large, that is, when VPSC is near Vth, the signal of the drain of M2 is transmitted to terminal + VOUT via C4 due to the large resistance of M4. Further, since the resistance of M3 is large, the signal of the drain of M1 is transmitted to the terminal -VOUT.

  On the other hand, when the resistances of M3 and M4 are small, that is, when VPSC is close to VDD, the signal of the drain of M1 is transmitted to terminal + VOUT through C3 due to the small resistance of M4. Further, since the resistance of M3 is small, the signal of the drain of M2 is transmitted to terminal -VOUT via C2. Thus, by making the resistances of M3 and M4 variable, the phase of the output signal from the terminals + VOUT and -VOUT changes by 180 ° at the maximum.

When the values of the capacitors C1 and C4 are C and the resistance values (ON resistances) of the MOSFETs M3 and M4 are RON, the phase shift characteristic by the CR bridge circuit is expressed by the following equation.

Here, θ represents the phase difference between the drain terminal voltage of M2 and M1 and the voltage between the output terminals + VOUT and −VOUT. Since M3 and M4 operate in the linear region, assuming that the proportionality constant is A, it can be approximated as R _ON = A / (V _PSC −Vth) as described in FIG. Therefore, equation (8) can be modified as follows.

If V _PSC is smaller than Vth, the MOSFET is completely turned off, and the phase θ cannot be controlled by V _PSC . In order to avoid this, the threshold compensation circuit shown in FIG. 15 may be applied to the attenuator ATT shown in FIG. That is, when the control currents Icnt1 and Icnt2 become larger than 0, the output of OP1, that is, the gate potential of M1, is automatically set to a value larger than Vth in order to pass a current through M1. Here, the amplitude control signal and the phase control signal are defined by voltage and current, but the conversion can be performed according to the equation V = IR. For example, here, the control currents Icnt1 and Icnt2 are equivalent to the phase control signal Vθ.

(Specific example of phase shifter 2)
18 is a circuit diagram in which a polarity inversion function provided in the phase shifter PS1 in FIG. 16 is added to the phase shifter in FIG. In the phase shifter of FIG. 18, in addition to the first differential pair of MOSFETs M1 and M2 shown in FIG. 17, a second differential pair of MOSFETs M7 and M8 is added. The tail current supplied from the current source I1 to the first differential pair is switched by the polarity switching signal pmθ, and the tail current supplied from the current source I2 to the second differential pair is inverted by the polarity switching signal pmθ / Switched by.

Whether the first differential pair of M1 and M2 operates or whether the second differential pair of M7 and M8 operates is determined by the polarity switching signals pmθ and pmθ /. As shown in FIG. 18, the gate terminals of M1 and M7 are connected in common to + V _IN , and the gate terminals of M2 and M8 are connected in common to −V _IN , but the drain terminal which is the output is M1 and M8, M2, and M7 are connected in common. That is, in the first differential pair and the second differential pair, the connection of the drain terminal that is an output has an opposite relationship. Accordingly, the polarity of the output signal of the phase shifter can be inverted by selectively operating the first differential pair and the second differential pair by the polarity switching signals pmθ and pmθ /.

(Amplitude / phase detection circuit)
Next, specific examples of the amplitude difference detector 35 and the phase comparator 36 in FIGS. 1 and 13 will be described. When the amplitude difference detector 35 and the phase comparator 36 are realized by analog circuits, for example, an amplitude / phase detection circuit as shown in FIG. 19 can be used. FIG. 19 is a circuit that receives the inputs A, B, C, and D of amplitude or phase detection targets and obtains a detection output OUT.

The amplitude difference detection is performed according to the equation (1) as described above, for example. In equation (1), (FI ² + FQ ² ) represents an output OUT (referred to as OUT1) when inputs A and C are set as FI and FQ is input into B and D. Similarly, (I ² + Q ² ) in the expression (1) represents an output OUT (referred to as OUT2) when the inputs A and C are defined as I and Q is input as B and D. By detecting the difference corresponding to OUT1-OUT2, the amplitude difference detection signal V ^DA according to the equation (1) can be obtained by an analog circuit.

  FIG. 20 shows an example of a difference detection circuit that detects the OUT1-OUT2. OUT1 is given as input IN1, and OUT2 is given as input IN2. The differential detection circuit of FIG. 20 includes a first differential amplifier including a differential pair of MOSFETs M3 and M4 and a common current source I1, and a second differential amplifier including a differential pair of MOSFETs M5 and M6 and a common current source I2. , And MOSFETs M1 and M2 provided in common to the first and second differential amplifiers and a load circuit including resistors R1 and R2. The input of the first differential amplifier is IN1, and the input of the second differential amplifier is IN2.

  The outputs of the first differential amplifier and the second differential amplifier are connected to the common load circuit with opposite polarities. With the difference detection circuit of FIG. 20, a signal corresponding to IN1-IN2, that is, OUT1-OUT2, is obtained at the output OUT. Therefore, the amplitude difference detector 35 can be realized by combining the circuit of FIG. 20 with the circuit of FIG.

  Since the phase difference detection signal PHS and the code detection signal PL are calculated using, for example, the equations (4) and (5) as described above, they can be realized by the circuit of FIG. That is, when I is input to input A, FI is input to input C, Q is input to input B, and FQ is input to input D, the calculation of equation (4) can be realized. When I is input to input A, FQ is input to input C, Q is input to input B, and FI is input to input D, the calculation of equation (5) can be realized.

  In order to obtain the necessary amplitude control signal VA and phase control signal Vθ by performing feedback with an analog circuit, it is possible to apply feedback without changing the voltage signal. However, after the voltage signal is converted into current once, the feedback is applied. May be. When the feedback is applied after the voltage signal is changed to the current signal, it is desirable to use the threshold value variation compensating circuit shown in FIG.

(Polarity reversing switch and baseband amplifier)
FIG. 21 shows a specific circuit example of the switch 34 and the baseband amplifier 15 shown in FIGS. 1 and 13. In FIG. 21, the switch 34 is divided into two blocks 34-1 and 34-2. Here, VIN represents the input I / Q signals I and Q, and the feedback signal VF corresponds to the feedback I / QFI and FQ. When one of the switch A and the switch B is turned on and the other is turned off, the feedback I / Q signal (VF) is captured with the polarity changed. On the other hand, the input I / Q signal VIN is taken in as it is because it is not necessary to switch the polarity. The gain is given by -R2 / R1.

  The baseband amplifier 15 is configured to change the gain between the calibration mode in which the Cartesian loop is opened and the case in which the Cartesian loop is closed. The baseband amplifier 15 includes two stages of operational amplifiers OP1 and OP2 connected in cascade, and gain switching circuits 38-1 and 38-2 inserted between OP1 and OP2. The gain of the second operational amplifier OP2 including the feedback resistor is represented by -R5 / R3 or -R5 / R4. In this example, the gain switching circuits 38-1 and 38-2 can switch the gain in two stages by switching the two resistors R3 and R4 with the switch C.

  For example, assume that R3 = 10 × R4 = R5, R3 is selected in the calibration mode, and R4 is selected in the transmission mode. In the calibration mode, the baseband amplifier 15 functions as an amplifier having a gain −R5 / R3 = −1. The feedback V-ATT is set so that the loop gain becomes 1 in this state. When the calibration mode is changed to the transmission mode, the resistance R3 is switched to R4, so that the gain is −R5 / R4 = −10, which is increased by 20 dB from that in the calibration mode. That is, in the transmission mode, the loop gain is 20 dB, so that the linearity can be improved.

  Since the gain switching circuits 38-1 and 38-2 in FIG. 21 select the resistors R3 and R4 by the switch C, a transient response occurs at the time of gain switching. When the time of transient response is limited due to wireless specifications, it is desirable to change the gain continuously rather than abruptly.

  In the baseband amplifier 15 in FIG. 22, the gain switching circuits 38-1 and 38-2 in FIG. 21 are replaced with a variable resistance circuit 39 including MOSFETs M1 and M2. A gain control voltage VCNT corresponding to a gain setting signal is supplied from the controller 40 to the gate terminals of M1 and M2. As the resistances of the MOSFETs M1 and M2 are changed by the gain control voltage VCNT, the gain of the baseband amplifier 15 is continuously changed. In the calibration mode, the resistance values of M1 and M2 are set to the same value as R5. At the time of transition from the calibration mode to the transmission mode, the gain control voltage VCNT is set so that the resistance values of M1 and M2 gradually transition from R5 to about R5 / 10. This eliminates a steep gain change in the baseband amplifier 15 and may shorten the time for the gain to converge to a predetermined value.

(I / Q imbalance compensation)
When the quadrature modulator or the quadrature demodulator is realized by an analog circuit, an amplitude error or a phase error between the I component (in-phase component) and the Q component (quadrature component) occurs due to imperfection of the analog circuit. Such an amplitude or phase error between IQ components is generally called I / Q imbalance. The Cartesian loop can also be applied to compensation for I / Q imbalance as follows.

  In the embodiments so far, the example in which the distortion generated in the transmission unit is compensated using the linearity of the feedback circuit of the Cartesian loop has been described. Similarly, if the I / Q imbalance of the quadrature demodulator 30 in the feedback circuit is small, the I / Q imbalance of the quadrature modulator 16 of the transmission system can also be compensated using a Cartesian loop.

  Specifically, an I / Q imbalance compensation technique of a quadrature demodulator that has been conventionally performed in a wireless receiver is applied to the quadrature demodulator 30 in the Cartesian loop. For example, in order to compensate for the amplitude error in the I / Q imbalance, the value of the resistor R1 that receives the feedback signal VF in FIG. 21 may be adjusted as necessary. When an I / Q imbalance due to a phase shift error of the 90 ° phase shifter 33 for the local signal occurs, the phase difference between the two local signals output from the 90 ° phase shifter 33 is 90 °. Make adjustments so that The phase difference may be adjusted using, for example, the phase shifter shown in FIG. In this way, by applying the I / Q imbalance compensation to the quadrature demodulator 30 in the feedback circuit of the Cartesian loop, it is possible to correct the error of the transmission unit system by the Cartesian loop.

(About the phase comparator 36)
Next, the phase comparator 36 will be described in more detail. The phase comparator 36 outputs a composite phase difference detection signal V ^D θ. As described above, the composite phase difference detection signal V ^D θ includes the normalized phase difference signal CPHS and the code detection signal PL. FIG. 23 shows a portion of the phase comparator 36 that generates the normalized phase difference signal CPHS.

  In FIG. 23, the phase difference detector 51 detects the phase difference θ between the input I / Q signals I and Q and the feedback I / Q signals FI and FQ according to the equation (4), and generates the phase difference detection signal PHS. . The phase difference detector 51 is realized by, for example, an amplitude / phase detection circuit shown in FIG.

  When the method of generating the amplitude control signal and the phase control signal by the analog feedback shown in FIG. 13 is used, the phase difference detection signal PHS shown in the equation (4) is a function of the phase and the amplitude, so that it is not normally controlled. . Therefore, as shown in FIG. 23, an amplitude normalizer 52 is connected to the subsequent stage of the phase difference detector 51, and the normalized phase difference signal CPHS in which the amplitude of the phase difference detection signal PHS is normalized by the amplitude normalizer 52 is transferred. Input to phase shifter 29.

In order to normalize the phase difference detection signal PHS by amplitude, as can be seen from the equation (4), the phase difference detection signal PHS is divided by the value of the following equation (10) (in other words, the phase difference detection signal PHS is expressed by the equation (Reciprocal of (10)).

Equation (10) represents the magnitude of the vectors of the feedback I / Q signals FI and FQ. In this example, the phase difference detection signal PHS is normalized by dividing the phase difference detection signal PHS by the square of the vector magnitude of the feedback I / Q signals FI and FQ, but the phase difference detection signal PHS is input to the input I / Q. Normalization may be performed by dividing by the square of the magnitude of the vectors of the signals I and Q. Hereinafter, the square of the magnitude of the vectors of the feedback I / Q signals FI and FQ or the square of the magnitude of the vectors of the input I / Q signals I and Q is referred to as I / QI / Q signal amplitude, and A ² ( t).

  However, in this amplitude normalization method, when the I / Q signal amplitude as shown in Expression (10) is close to 0, the phase difference detection signal PHS must be amplified with an amplification factor close to infinity by an analog multiplier. In other words, it is difficult to realize the amplitude normalizer 52 with a realistic circuit.

  Hereinafter, the configuration of the amplitude normalizer 52 that overcomes such difficulties will be described with reference to FIGS. 24 and 26 to 29 show various examples of the amplitude normalizer 52 together with waveform examples of input / output signals and intermediate processing signals.

(First Example of Amplitude Normalizer 52)
24 includes a divider 53, a comparator 54, and a sample and hold circuit 55. According to the comparison result signal from the comparator 54, the divider 53 and the sample and hold circuit 55 cause the phase difference detection signal PHS. Is used to generate a normalized phase difference signal CPHS.

The divider 53 can normalize the amplitude of the phase difference detection signal PHS in a region below a certain gain, but can amplify only to a finite gain. Therefore, when the value of the I / Q signal amplitude A ² (t) as shown in the equation (10) is near 0, the output signal of the divider 53 diverges as shown in FIG. End up. Therefore, normalization cannot be performed normally only by the divider 53. Therefore, in the example of FIG. 24, the output signal of the divider 53 is sampled and held by the sample and hold circuit 55 as follows.

The sample hold circuit 55 is controlled by the comparator 54. The comparator 54 has a reference value input terminal and an I / Q signal amplitude input terminal. When the I / Q signal amplitude A ² (t) is larger than the reference value (reference voltage) V _REF , comparison is performed. HIGH is output as a result signal, otherwise LOW is output as a comparison result signal.

  The sample hold circuit 55 outputs the division signal output from the divider 53 during the period when the comparison result signal from the comparator 54 is HIGH, that is, the division signal corresponding to the current value of the phase difference detection signal PHS as it is as the normalized phase difference. Output as signal CPHS. In this way, during the period when the comparison result signal from the comparator 54 is HIGH, the sample and hold circuit 55 does not perform the sample and hold operation, but tracks the division signal output from the divider 52 and outputs the normalized phase difference signal CPHS. To do.

When the comparison result signal from the comparator 55 becomes LOW, the sample hold circuit 55 performs a sample hold operation. That is, the sample-and-hold circuit 55 samples the division signal from the divider 53 at the timing immediately before the comparison result signal becomes LOW, and holds it for LOW thereafter, and the sampled and held division signal is used as the normalized phase difference signal CPHS. Continue to output. Here, the reference value V _REF is set to a value equal to or greater than the I / Q signal amplitude that can be normally normalized by the divider 53, for example.

  By adopting such a configuration, the amplitude normalizer 53 can be realized by a realistic analog circuit.

Next, a specific example of the divider 53 in FIG. 23 will be described. FIG. 25 is a circuit diagram showing a specific example of the divider 53. The phase difference detection signal PHS is expressed by differential current signals I ₁ + bI _M sin θ and I ₁ −bI _M sin θ. Here, I _M = I ² + Q ² = FI ² + FQ ² , I ₁ represents a direct current, and b represents a constant. On the other hand, the amplitude difference detection signal V ^D A is represented by differential current signals I ₂ + (1/2) aI _M and I ₂ + (1/2) aI _M. Here, I ₂ is a direct current, and a is a constant.

The differential current signals I ₂ + (1/2) aI _M and I ₂ + (1/2) aI _{M that} are amplitude difference detection signals V ^D A are MOSFETs: a first current mirror by M1-M4, and MOSFETs: The current signal aI _M is received by the second current mirror by M5-M6 and flows to the common source terminal of the first differential pair by MOSFET: M7-M8.

On the other hand, differential current signals I ₁ + bI _M sin θ and I ₁ -bI _M sin θ, which are phase difference detection signals PHS, are generated by a third current mirror using MOSFETs M14-M13 and a fourth current mirror using MOSFETs M16-M15. Received and input to the common source terminal of the second differential pair by MOSFET: M9-M10 and the third differential pair by MOSFET: M11-M12, respectively. MOSFET: When M7-M12 is operated in the weak inversion region,

Satisfied. The difference between I + and I− which are output signals of the divider 53 in FIG.

Thus, a signal without the influence of the component of I _M is obtained. Since the output signal of the divider 53 in FIG. 25 is a current signal, it is converted to a voltage signal by a current-voltage converter such as a resistor (not shown) and then input to the sample and hold circuit 55.

(Second Example of Amplitude Normalizer 52)
26 differs from FIG. 24 in that the phase difference detection signal PHS is directly input to the sample and hold circuit 55 without using the divider 53. In the amplitude normalizer 52 of FIG. 26, the phase difference detection signal PHS is output as it is as the normalized phase difference signal CPHS only when the I / Q signal amplitude A ² (t) is larger than the reference value V _REF, thereby increasing the amplitude. Standardization is performed. Thus, the amplitude of the phase difference detection signal PHS can be normalized with a simple configuration that does not require a divider using an analog amplifier.

(Third example of the amplitude normalizer 52)
In the amplitude normalizer 52 of FIG. 27, the I / Q signal amplitude A ² (t) is input to the two comparators 56 and 57 and compared with the two reference values V _{REF, low} and V _{REF, high} . Comparison result signals from the comparator 56 and the comparator 57 are input to the exclusive OR circuit 58. The output signal of the exclusive OR circuit 58 outputs HIGH when the I / Q signal amplitude A ² (t) is between two reference values V _{REF, low} and V _{REF, high} , otherwise Outputs LOW. However, the two reference values satisfy the relationship of V _{REF, low} <V _{REF, high} . The sample hold circuit 55 is controlled by the output signal of the exclusive OR circuit 58.

That is, the amplitude normalizer 52 of FIG. 27 performs (a) I / Q signal amplitude A ² (t) according to the comparison result signal from the comparator 56 and the comparator 57 input via the exclusive OR circuit 58. Is larger than the reference value V _{REF, low} and smaller than the reference value V _{REF, high} , the current value of the phase difference detection signal PHS is output as the normalized phase difference signal CPHS, and (b) I / Q signal amplitude If A ² (t) is less than the reference value V _{REF, low} or greater than the reference value V _{REF, high} , the I / Q signal amplitude A ² (t) is less than the reference value V _{REF, low} or the reference The value of the phase difference detection signal PHS sampled and held by the sample hold circuit 55 immediately before it becomes larger than the value V _{REF, high} is output as the normalized phase difference signal CPHS.

  As described above, according to the amplitude normalizer 52 of FIG. 27, it is possible to generate a signal whose amplitude is equivalently normalized without using a divider by an analog amplifier.

(Fourth example of the amplitude normalizer 52)
In the amplitude normalizer 52 of FIG. 28, the amplitude of the phase difference detection signal PHS is normalized by the low-pass filter 60 having the variable resistor 61 and the capacitor 62 to generate a normalized phase difference signal CPHS. The variable resistor 61 is realized by NMOSFET, for example, and in that case, the gate terminal is used as a control terminal of the variable resistor 61. The control terminal of the variable resistor 61 is supplied with the I / Q signal amplitude A ² (t) as a control voltage. The resistance value of the variable resistor 61 decreases monotonously with respect to the control voltage. That is, the resistance value of the variable resistor 61 is low when the I / Q signal amplitude A ² (t) is large, and is high when the I / Q signal amplitude A ² (t) is small.

The phase difference detection signal PHS is input to the low pass filter 60. At this time, the resistance value of the variable resistor 61 is controlled by the I / Q signal amplitude A ² (t) as described above, so that the cutoff frequency of the low-pass filter 60 becomes the I / Q signal amplitude A ² (t ) Increases when it is large, and decreases when I / Q signal amplitude A ² (t) is small. Therefore, when the I / Q signal amplitude A ² (t) is large, the attenuation amount of the phase difference detection signal PHS decreases, and when the I / Q signal amplitude A ² (t) is small, the attenuation amount of the phase difference detection signal PHS increases. To do.

As described above, according to the fourth example of the amplitude normalizer 52, the phase difference detection signal PHS can be output only when the I / Q signal amplitude A ² (t) is large as in the second example. This makes it possible to normalize the amplitude of the phase difference detection signal PHS.

  Note that the amplitude normalizer 52 of the fourth example shown in FIG. 28 can also be used as a loop filter of the phase calibration loop.

(Fifth example of the amplitude normalizer 52)
FIG. 29 shows a fifth example of the amplitude normalizer 52. In FIG. 29, the low-pass filter 60 is provided with two variable resistors 61A and 62B. The variable resistor 61A is realized by, for example, an NMOSFET similarly to the variable resistor 61 in FIG. 28, and the variable resistor 61B is realized by, for example, a PMOSFET. Here, for simplicity, NMOSFET and PMOSFET are used for the variable resistors 61A and 61B, respectively, but this is only an example, and variable resistors of other configurations may be used.

The resistance value of the variable resistor 61A monotonously decreases as the I / Q signal amplitude A ² (t) increases, similarly to the variable resistor 61 of FIG. That is, the resistance value of the variable resistor 61A decreases when the I / Q signal amplitude A ² (t) is large, and increases when the I / Q signal amplitude A ² (t) is small. On the other hand, the resistance value of the variable resistor 61B increases monotonously as the I / Q signal amplitude A ² (t) increases. That is, the resistance value of the variable resistor 61B becomes high when I / Q signal amplitude A ² (t) is large, low when I / Q signal amplitude A ² (t) is small.

In such a composite variable resistor in which the variable resistors 61A and 61B are connected in series, the resistance value increases when the I / Q signal amplitude A ² (t) is small and large, and the I / Q signal amplitude A ² When (t) is medium, that is, the I / Q signal amplitude A ² (t) approaches the reference value, the resistance value decreases. Since the composite variable resistor performs the above-described operation, the low-pass filter 60 of FIG. 29 has a low cutoff frequency when the I / Q signal amplitude A ² (t) is small and large, and the I / Q signal amplitude A ² The cutoff frequency is high when (t) is medium. That is, when the I / Q signal amplitude A ² (t) is small and large, the amount of attenuation of the phase difference detection signal PHS increases, and when the I / Q signal amplitude A ² (t) is medium, the phase difference detection signal PHS. Is attenuated, the amplitude of the phase difference detection signal PHS is normalized, and a normalized phase difference signal CPHS is generated.

  As described above, according to the fifth example of the amplitude normalizer 52, the phase difference detection signal PHS can be equivalently normalized similarly to the third example.

  Note that the amplitude normalizer 52 of the fifth example can also be used as a loop filter of the phase calibration loop.

  In each of the above-described embodiments, as shown in FIG. 1, the quadrature modulator 16 and the quadrature demodulator 30 share the local oscillator 20, but it is not always necessary to share the two local oscillators (not shown). ) May be used.

  The resistor R is provided to prevent a signal from being radiated from the antenna 25 in a state where the Cartesian loop is closed. Therefore, the antenna switch 26 and the resistor R may not be provided in some cases, for example, a signal may be radiated from the antenna 25.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 11, 12 ... Transmission RF signal input terminal 13, 14 ... Synthesizer 15 ... Baseband amplifier 16 ... Quadrature modulator 20 ... Local oscillator 21 ... Variable attenuator 22 ... Driver amplifier 23 ... Power amplifier 24 ... Power coupler (branch switch)
25 ... Antenna 26 ... Antenna switch 27 ... Variable attenuator (amplitude adjuster)
28 ... Low noise amplifier 29 ... Variable phase shifter (phase adjuster)
30 ... Quadrature demodulator 34 ... Switch with polarity inversion function 35 ... Amplitude difference detector 36 ... Phase comparator 37 ... Isolator 40 ... Controller 41 ... Control signal generator 42 ... Digital-analog converter 43 ... Analog-digital converter 44 ... Memory 45 ... Mode setting unit 46 ... Loop gain setting unit 47 ... Transmission power setting unit 51 ... Phase difference detector 52 ... Amplitude normalizer 53 ... Divisor 54 ... Comparator 55 ... Sample hold circuit 56 ... First comparator 57 ... Second comparator 58 ... Exclusive OR circuit 60 ... Low-pass filter 61 ... Variable resistor 61A ... First variable resistor 61B ... Second variable resistor 62 ... Capacitor

Claims (15)

In a wireless transmission device using a Cartesian loop,
A combiner that combines the input I / Q signal to be transmitted and the feedback I / Q signal to generate a combined I / Q signal;
A quadrature modulator that quadrature modulates the combined I / Q signal to generate a quadrature modulated signal;
A power amplifier that amplifies the quadrature modulation signal and outputs a transmission RF signal;
A quadrature demodulator that performs quadrature demodulation on a feedback RF signal branched from the transmission RF signal using a local signal to generate the feedback I / Q signal;
A switch for turning on / off the input of the feedback I / Q signal to the combiner;
A power setting unit capable of setting at least one power of the transmission RF signal;
An amplitude difference detector that detects an amplitude difference between the input I / Q signal and the feedback I / Q signal to generate an amplitude difference detection signal during a period when the switch is off;
A phase difference detector that detects a phase difference between the input I / Q signal and the feedback I / Q signal to generate a phase difference detection signal during a period when the switch is off;
In order to normalize the phase difference detection signal with the signal amplitude to generate a normalized phase difference signal, a period in which the signal amplitude of either the input I / Q signal or the feedback I / Q signal is larger than a reference value is The normalization is performed using the current value of the phase difference detection signal, and when the signal amplitude becomes smaller than the reference value, the value before the signal amplitude of the phase difference detection signal becomes smaller than the reference value is used. A normalizer for performing the normalization;
Receiving the amplitude difference detection signal and the normalized phase difference signal, and minimizing the amplitude control signal and the phase difference to minimize the amplitude difference under a state in which the power is set while the switch is off A control signal generator for generating a phase control signal to perform;
A memory for storing the amplitude control signal and the phase control signal;
An amplitude adjuster that adjusts the amplitude of the feedback RF signal according to an amplitude control signal stored in the memory during a period in which the switch is on;
A phase adjuster that adjusts the phase of the local signal according to a phase control signal stored in the memory during a period when the switch is on; and, for the Cartesian loop, a first loop gain when the switch is off And a gain setting unit that sets a second loop gain higher than the first loop gain when the switch turns from OFF to ON.   The normalizer includes a divider that divides the phase difference detection signal by the signal amplitude to generate a division signal, a comparator that compares the signal amplitude and the reference value to obtain a comparison result signal, and Controlled by a comparison result signal, and (a) outputs a division signal corresponding to a current value of the phase difference detection signal as the normalized phase difference signal during a period when the signal amplitude is larger than the reference value; The radio transmission apparatus according to claim 1, further comprising: a sample and hold circuit that samples and holds the divided signal and outputs the normalized phase difference signal when a signal amplitude becomes smaller than the reference value.   The normalizer compares the signal amplitude with the reference value to obtain a comparison result signal, and is controlled by the comparison result signal. (A) The period when the signal amplitude is larger than the reference value is The current value of the phase difference detection signal is output as the normalized phase difference signal. (B) When the signal amplitude is smaller than the reference value, the phase difference detection signal is sampled and held and the normalized phase difference signal is output. The wireless transmission apparatus according to claim 1, further comprising a sample and hold circuit.   The normalizer includes a first comparator that compares the signal amplitude with a first reference value to obtain a first comparison result signal, and a second reference with the signal amplitude greater than the first reference value. A second comparator for obtaining a second comparison result signal by comparing with the value, and controlled by the first comparison result signal and the second comparison result signal, and (a) the signal amplitude is the first comparison result signal During a period greater than a reference value and less than the second reference value, the current value of the phase difference detection signal is output as the normalized phase difference signal, and (b) the signal amplitude is less than the first reference value. 2. The radio transmission apparatus according to claim 1, further comprising: a sample hold circuit that samples and holds the phase difference detection signal and outputs the normalized phase difference signal when the second reference value is exceeded.   The radio transmission apparatus according to claim 1, wherein the signal amplitude is a magnitude of a vector of the input I / Q signal.   The radio transmission apparatus according to claim 1, wherein the signal amplitude is a magnitude of a vector of the feedback I / Q signal. A variable-gain baseband amplifier that is provided in front of the quadrature modulator and amplifies the combined I / Q signal;
A gain setting unit that sets a first gain for the baseband amplifier when the switch is off, and sets a second gain higher than the first gain when the switch turns from off to on; The wireless transmission device according to claim 1, further comprising: In a wireless transmission device using a Cartesian loop,
A combiner that combines the input I / Q signal to be transmitted and the feedback I / Q signal to generate a combined I / Q signal;
A quadrature modulator that quadrature modulates the combined I / Q signal to generate a quadrature modulated signal;
A power amplifier that amplifies the quadrature modulation signal and outputs a transmission RF signal;
A quadrature demodulator that performs quadrature demodulation on a feedback RF signal branched from the transmission RF signal using a local signal to generate the feedback I / Q signal;
A switch for turning on / off the input of the feedback I / Q signal to the combiner;
A power setting unit capable of setting at least one power of the transmission RF signal;
An amplitude difference detector that detects an amplitude difference between the input I / Q signal and the feedback I / Q signal to generate an amplitude difference detection signal during a period when the switch is off;
A phase difference detector that detects a phase difference between the input I / Q signal and the feedback I / Q signal to generate a phase difference detection signal during a period when the switch is off;
A low-pass filter configured to change a cut-off frequency according to the signal amplitude in order to normalize the phase difference detection signal with the signal amplitude to generate a normalized phase difference signal; A normalizer for filtering the phase difference detection signal to generate the normalized phase difference signal;
Receiving the amplitude difference detection signal and the normalized phase difference signal, and minimizing the amplitude control signal and the phase difference to minimize the amplitude difference under a state in which the power is set while the switch is off A control signal generator for generating a phase control signal to perform;
A memory for storing the amplitude control signal and the phase control signal;
An amplitude adjuster that adjusts the amplitude of the feedback RF signal according to an amplitude control signal stored in the memory during a period in which the switch is on;
A phase adjuster that adjusts the phase of the local signal according to a phase control signal stored in the memory during a period when the switch is on; and, for the Cartesian loop, a first loop gain when the switch is off And a gain setting unit that sets a second loop gain higher than the first loop gain when the switch turns from OFF to ON.   The wireless transmission device according to claim 8, wherein the low-pass filter is configured such that the cutoff frequency increases as the signal amplitude increases.   The wireless transmission according to claim 8, wherein the low-pass filter includes a variable resistor that is controlled so that a resistance value monotonously decreases as the signal amplitude increases, and a capacitor connected to the variable resistor. apparatus.   The radio transmission device according to claim 8, wherein the low-pass filter is configured such that the cutoff frequency increases as the signal amplitude approaches a reference value.   The low-pass filter is connected in series with a first variable resistor that is controlled so that a resistance value monotonously decreases as the signal amplitude increases, and the signal amplitude And a capacitor connected to a series circuit of the first variable resistor and the second variable resistor. The wireless transmission device according to claim 8, further comprising:   The radio transmission apparatus according to claim 8, wherein the signal amplitude is a magnitude of a vector of the input I / Q signal.   The radio transmission apparatus according to claim 8, wherein the signal amplitude is a magnitude of a vector of the feedback I / Q signal. A variable-gain baseband amplifier that is provided in front of the quadrature modulator and amplifies the combined I / Q signal;
A gain setting unit that sets a first gain for the baseband amplifier when the switch is off, and sets a second gain higher than the first gain when the switch turns from off to on; The wireless transmission device according to claim 8, further comprising:

Images