MXPA06008172A - Multi-terminal devices having logic functionality - Google Patents

Abstract

A multi-terminal logic device. The device includes a phase change material having crystalline and amorphous states in electrical communication with three or more electrical terminals. The phase change material is able to undergo reversible transformations between amorphous and crystalline states in response to applied electrical energy where the amorphous and crystalline states show measurably distinct electrical resistances. Electrical energy in the form of current or voltage pulses applied between a pair of terminals influences the structural state and measured electrical resistance between the terminals. In the instant devices, independent input signals are provided between different pairs of terminals and the output is measured as the resistance between yet another pair of terminals. Logic functionality is achieved through relationships between the applied input signals and the measured output resistance where the relationship is governed by the effect of the input signals on the structural state and electrical resistance of the phase change material. Logic values may be associated with the crystalline and amorphous states of the phase change material or the measured resistance between a pair of terminals.

Description

MULTI-TERMINAL DEVICES THAT HAVE LOGICAL FUNCTIONALITY FIELD OF THE INVENTION The present invention is concerned with electronic devices useful in information processing. More specifically, the present invention is concerned with electronic devices having logical functionality by controlling the relative proportions of the crystalline and amorphous phases of a phase change material obtained by the application of appropriate input signals. More specifically, the present invention is concerned with chalcogenide devices having three or more terminals wherein the application of input signals through different pairs of terminals alters the structural state and strength of a chalcogenide material in such a way that the ratio between the input signals and a measured output resistor is made up of truth tables of logical functions.

BACKGROUND OF THE INVENTION There is a continuing need to improve the performance of computers to meet the needs of new and more sophisticated calculation applications. Applications such as pattern classification, pattern association, associative memory functions, speech and character recognition are still largely not prone to solution or implementation by current computers as there are many tasks that are easily and intuitively performed by humans and other organisms biological The desire to expand the frontiers of computer science has forced consideration of the factors that contribute to the limitations of current computers. Silicon is the heart of today's computer. The advances in the power of calculation and speed over the years has been largely a consequence of better understanding of the fundamental properties of silicon and use of those properties for practical effect. The initial advance was predicated on the construction of basic electronic components such as transistors and silicon diodes and later progress followed the development of integrated circuits. The most recent advances represent a configuration of these trends and currently emphasize the miniaturization and integration of an even larger number of microelectronic devices on a single chip. The smaller devices lead to higher memory storage densities, more highly integrated circuits and reduced interaction times between devices on the same chip. Since future improvements in computing power and functionality are currently predicated on further improvements in silicon technology, there has been much recent discussion about the prognosis of continued miniaturization of silicon-based electronic devices. A growing consensus is emerging that believes that the computer industry is rapidly approaching silicon performance limits. The element size in today's manufacturing technology is 0.18 microns and it is expected that it can be reduced to approximately 0.10 microns in the future. However, it is considered that the additional decreases in the element size is problematic due to I that smaller sizes of approximately 0.10 microns lead to a change in the fundamental behavior of silicon. More specifically, as the dimensions of silicon devices decrease to tenths of a nanometer and less, silicon enters the regime of quantum behavior and no longer functions according to the classical physics that governs macroscopic objects. In the quantum regime, energy states are quantified instead of continuous and phenomena such as quantum filtration lead to the delocalization of electrons through many devices. The consequences of quantum leakage include current leakage as electrons escape from a device to neighboring devices and loss of device independence as the state of a device influences the state of neighboring devices. In addition to the fundamental changes in the behavior of siliconFurther reductions in the dimensions of the silicon devices also pose formidable technological challenges. New and expensive innovations in manufacturing methods such as photolithography will be necessary to obtain smaller element sizes. One strategy for advancing the capabilities of computers is to identify materials other than silicon that can be used as the active medium in data processing and / or storage applications. Such alternative means of calculation could be used independently or in combination with silicon to form the basis of a new calculation industry that seeks to offer better performance and more convenient manufacturing than is possible with silicon. The use of chalcogenide phase change materials as an active material for data processing and storage has recently been proposed. In U.S. Patent Application Serial No. 10 / 144,319 (application 319), the disclosure of which is incorporated herein by reference, Ovshinsky et al. describes a principle of operation of phase change materials in calculation applications. Phase change materials can not only function in the binary mode characteristics of conventional silicon computers but also offer opportunities for non-binary data storage and processing. Non-binary storage provides high densities of information storage, while non-binary processing provides increased parallelism of operation. Reference x319 also describes representative algorithms that use a non-binary calculation method for mathematical operations such as addition, subtraction, multiplication, and division. Patent application Serial No. 10 / 155,527 (the application? 527) of Ovshinsky et al., The disclosure of which is incorporated herein by reference, describes additional mathematical operations based on a means of calculating change of phase, in which factorization is included, operation of modular and parallel arithmetic. In the US patent application Serial No. 10 / 189,749 (the application? 749), the disclosure of which is incorporated herein by reference, Ovshinsky considers the architecture of calculation systems based on devices that use a material of phase change as the active calculation means. More specifically, Ovshinsky considers networks of phase change calculation devices and demonstrates functionality that closely parallels that of biological neural networks. Important aspects of this functionality include the cumulative response of the phase change calculation devices to input signals from a variety of sources, the ability to weight the input signals and a stable, reproducible material transformation that mimics the triggering of a biological neuron.

This functionality enables a new concept in intelligent calculation that includes learning, adaptability and plasticity. In the silicates of US Pat. Nos. 10 / 384,994 (the application? 994); 10 / 426,321 (the application 321); and 10 / 657,285 (application? 285), the disclosures' of which are incorporated herein by reference, Ovshinsky et al. Further develop the notion of phase change calculation by discussing additional computing and storage devices. The application? 994 discusses a multi-terminal phase change device wherein a control signal provided in an electrical terminal modulates the current, threshold voltage or signal transmitted between other electrical terminals by means of the injection of charge carriers. The application 321 describes a related multi-terminal device that uses a field effect terminal to modulate the current, threshold voltage or signal transmitted between other terminals. The devices described in the? 994 and? 321 applications can be • configured to provide functionality analogous to that of the transistor that is so vital to silicon-based computers. The application? 285 presents a multi-bit storage device having multiple terminals and using a phase change material. Previous work by Ovshinsky et al. It provides a concept, principles of operation and some basic devices to enable a calculation paradigm based entirely or in part on chalcogenide phase change materials or other phase change materials. In order to additionally perform chalcogenide counting as a viable or alternative complement to silicon-based technologies it is desirable to expand the range of devices and functionality available from the chalcogenide phase change materials. Of greater interest are the devices and systems capable of performing processing, storage or memory functions and logical functions.

BRIEF DESCRIPTION OF THE INVENTION The present invention provides electronic devices that have logic functionality based on phase change materials and methods for putting them into operation. The present devices include a phase change material as the working substance together with three or more electrical terminals in electrical communication with each other. The phase change material is capable of being reversibly transformed between a plurality of structural states that include a crystalline state, a partially state -crystalline and an amorphous state and shows an electrical resistance that can vary in a range of multiple orders of magnitude. The optical functionality is obtained by applying input signals to the electrical terminals by selectively programming specific portions of the phase change material to predetermined structural states having desired resistance such that the resistance pattern between pre-selected pairs of the three or more terminals conform to the truth table of a logical operation. In one embodiment of the present invention, a Y.X device is provided. In another embodiment of the present invention, an O element is provided. For a better understanding of the present invention, together with other objects and additional objects thereof, reference is made to the following description, taken in conjunction with the appended figures and claims.

BRIEF DESCRIPTION OF THE FIGURES Figure 1 shows the representative dependence of the electrical resistance of a chalcogenide material as a function of energy or current. Figure 2 shows a modality of a three-terminal device according to the present invention. Figure 3 is a schematic view of a chalcogenide storage device. of three terminals.

Figure 4A is a schematic illustration of the placement of terminals in relation to crystalline and amorphous regions of a phase change material in the pore region of a two-terminal device. Figure 4B is a schematic illustration of the placement of terminals in relation to the crystalline and amorphous regions of a phase change material in the pore region of a two-terminal device. Figure 4C is a schematic illustration of the placement of terminals in relation to the crystalline and amorphous regions of a phase change material in the pore region of a two-terminal device. Figure 5A is a schematic illustration of a crystalline route according to the present invention. Figure 5B is a schematic illustration of a crystalline route according to the present invention. Figure 5C is a schematic illustration of a crystalline route according to the present invention. Figure 6A is a schematic illustration of a three terminal embodiment of the present invention having a uniform or homogeneous phase change material in the pore region. Figure 6B is a schematic illustration of a three-terminal embodiment of the present invention having a non-uniform or inhomogeneous phase change material in the pore region. Figure 6C is a schematic illustration of a three-terminal embodiment of the present invention having a non-uniform or inhomogeneous phase change material in the pore region. Figure 6D is a schematic illustration of a three-terminal embodiment of the present invention having a non-uniform or inhomogeneous phase change material in the pore region. Figure 7 is an embodiment of a three-terminal device according to the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED MODALITIES The present invention generally provides elements or logic devices in a non-silicon-based calculation technology and methods of programming or operating non-silicon-based devices to obtain logical functionality. The present devices and elements include a phase change material and three or more electrical terminals which electrical communication therewith. The application of electrical signals to or through one or more electrical terminals program the resistance of the phase change material, in whole or in part, with variations or differences in electrical resistance between different pairs of terminals that provide a basis for logical functionality such as it is described later in the present. The phase change materials suitable for use in the present logic devices are materials capable of being transformed between two or more detectably distinct structural states. The different structural states can be distinguished on the basis, for example, of the crystal structure, atomic arrangement, order or disorder, fractional crystallinity, relative proportions of two or more - different structural states, a physical property (for example, electrical, optical, magnetic, mechanical) or chemical, etc. In a preferred embodiment, the transformations between structural states are reversible, such that the original state of a transformed material can be restored subsequent to a structural transformation. In a preferred embodiment, chalcogenide materials are used as the phase change material in the present invention. Calcgenide materials have previously been used in optical and electrical memory and in switching applications and some representative compositions and properties have been discussed in U.S. Patent Nos. 5,543,737; 5,694,146, 5,757,446; 5,166,758; 5,296,716; 5,534,711; 5,536,947; 5,596,522; and 6,087,674 ~; the disclosures of which are incorporated herein by reference, as well as in various journal articles that include "Reversible Electrical Switching Phenomena in Disordered Structures," Physical Review Letters, vol. 21, pages 1450-1453 (1969) by S.R. Ovshinsky; "Amorphous Semiconductors for Switching, Memory, and Imaging Applications"; IEEE Transactions on Electron Devices, Vol. ED-20, pages 91-105 (1973) by S.R. Ovshinsky and H. Fritzsche; the disclosures of which are incorporated herein by reference. General characteristics and comments about phase change chalcogenide materials are reviewed in the context of the present invention in the following discussion. Representative chalcogenide materials suitable for use in the present invention are those that include one or more elements of column VI of the periodic table (the chalcogen elements) and optionally one or more chemical modifiers of columns III, IV or V. One or more than S, Se, and Te are the most common chalcogen elements included in the chalcogenide data storage material of the present memory devices. Suitable modifiers include one or more of trivalent and tetravalent modifying elements such as As, Ge, Ga, Si, Sn, Pb, Al, Sb, In, and Bi. Transition metals such as Cu, Ni, Zn, Ag, and Cd can also be used as modifiers. A preferred chalcogenide composition includes one or more chalcogenide elements together with one or more trivalent or tetravalent modifiers and / or one or more transition metal modifiers. Materials that include Ge, Sb, and / or Te, such as Ge2Sb2Te5, are examples of chalcogenide materials according to the present invention. The chalcogen elements are characterized by divalent linkage and the presence of electrons from solitary pairs. The divalent bond leads to the formation of chain and ring structures after the combination of the chalcogen elements to form chalcogenide materials and the unit paired electrons provide an electron source to form a conductive filament in switching applications. The conductive filament can also contribute to or help to drive the phase changes that occur between different structural states. Trivalent metal modifiers, tetravalent and transitional can enter the chain and ring structures of the chalcogen elements and provide branching and crosslinking points. The structural rigidity of the. Chalcogenide materials depend on the extent of crosslinking and influence their ability to undergo crystallization or other structural transformations or rearrangements. An important aspect of the chalcogenide materials in the context of the present invention is their ability to undergo a reversible phase transformation between two or more structural states. Chalcogenide materials have structural states that include a crystalline state, one or more partially crystalline states and an amorphous state. The crystalline state may be a single crystalline state or a polycrystalline state. As used herein, a partially crystalline state refers to a structural state of a volume of chalcogenide material that includes an amorphous portion and a crystalline portion.

Preferably, there are a plurality of partially crystalline states for the phase change material that can be distinguished based on the relative proportion of the amorphous and crystalline portions. Fractional crystallinity is a way to characterize the structural states of a chalcogenide phase change material. The fractional crystallinity of the crystalline state is 100%, the fractional crystallinity of the amorphous state is 0% and the partially crystalline states have fractional crystallinities that vary continuously between 0% (the amorphous limit) and 100% (the crystalline limit). Thus, the phase change chalcogenide materials are capable of being reversibly transformed between a plurality of structural states that vary inclusively between fractional crystallinities of 0% and 100%. The ability and ease of a chalcogenide material to undergo structural transformations between structural states having several fractional crystallinities depends on the composition and structural characteristics of the chalcogenide material. The more highly crosslinked chalcogenide materials are structurally stiffer and generally include a higher concentration of modifiers. The more highly crosslinked chalcogenide materials are more difficult to crystallize due to the atomic rearrangements or rearrangements required for nuclear and to grow a crystalline phase are inhibited due to the stiffness of the structure. The more lightly crosslinked chalcogenide materials more readily suffer full or partial crystallization. Transformations between the structural states of a chalcogenide material are induced by providing energy to the chalcogenide material. Energy in various forms can influence the fractional crystallinity of a chalcogenide material and hence induce structural transformations. The appropriate forms of energy include electric power. thermal energy, optical energy or other forms of energy that induce electrical, thermal or optical effects in a chalcogenide material (e.g., particle beam energy) or combinations of the above forms of energy. The continuous and reversible variability of the fractional crystallinity is obtainable by controlling the energy environment of a chalcogenide material. A crystalline state can be transformed to a partially crystalline state or an amorphous state, a partially crystalline state can be transformed to a crystalline or amorphous state and an amorphous state can be transformed to a partially crystalline or crystalline state by means of appropriate control of the environment of energy from a chalcogenide material. Some considerations associated with the use of thermal, electrical and optical energy to induce structural transformations are presented in the following discussion. The use of thermal energy to induce structural transformations takes advantage of the thermodynamics and kinetics associated with the transitions from crystalline to amorphous or amorphous to crystalline phase. An amorphous phase may be formed, for example, from a partially crystalline or crystalline state by heating a chalcogenide material above its. melting temperature and cooling at a sufficient rate to inhibit the formation of crystalline phases. A crystalline phase can be formed from an amorphous or partially crystalline state, for example by heating a chalcogenide material above the crystallization temperature for a period of time sufficient to effect the nucleation and / or growth of crystalline domains. The crystallization temperature is lower than the melting temperature and corresponds to the minimum temperature at which crystallization may occur. The driving force for crystallization is commonly thermodynamic in that the free energy of a crystalline or partially crystalline state is lower than the free energy of an amorphous state, such that the overall energy of a chalcogenide material decreases as the fractional crystallinity increases. The formation (nucleation and growth) of a crystalline state or crystalline domain within a partially crystalline state is kinetically inhibited, however, such that heating below the melting point promotes crystallization by providing energy that facilitates atmospheric rearrangements necessary to form a crystalline phase or domain. The fractional crystallinity of a partially crystalline state can be controlled by controlling the temperature or heating time of crystalline or partially crystalline state or al. control the temperature or cooling rate of an amorphous or partially crystalline state. The use of electrical energy to induce structural transformations depends on the application of electrical impulses (current or voltage) to a chalcogenide material. The mechanism of electrically induced structural transformations can be electronic in nature, possibly with a concurrent or consistent thermal contribution. By controlling the magnitude and / or duration of the electrical impulses applied to a chalcogenide material it is possible to continuously vary the fractional crystallinity. The influence of electrical energy on the structure of a chalcogenide material is often illustrated in terms of the variation of the electrical resistance of a chalcogenide material with the amount of electric power provided or the magnitude of the voltage current or impulse applied to it. a chalcogenide material. A representative illustration of the electrical resistance (R) of a chalcogenide material as a function of electric power or current pulse magnitude (energy / current) is presented in Figure 1 herein. Figure 1 shows the variation of the electrical resistance of a chalcogenide material with the electric power or current pulse magnitude and can be referred to in general as a resistance graph. The resistance graph includes two response regimes characteristic of a chalcogenide material to electrical energy. The regimes are demarcated approximately with the vertical dashed line 10 shown in Figure 1. The regime to the left of line 10 can be termed as the chalcogenide material accumulation regime. The accumulation regime is distinguished by an almost constant or gradually variable electrical resistance with the increased electrical energy that culminates in an abrupt decrease in resistance beyond a threshold energy. Thus, the accumulation regime extends, in the direction of increased energy, from the leftmost point 20 of the resistance graph, through a plateau-region (generally illustrated by the number 30) corresponding to the interval of points in which the resistance variation is small or gradual to the point or state of attachment 40 that follows an abrupt decrease in electrical resistance. The plateau 30 can be horizontal or gradually inclined. The left side of the resistance graph is termed as - the accumulation regime because the structural state of the decarcogenide material evolves continuously as energy is applied with the fractional crystallinity of the structural state that correlates with the total accumulation of Energy. The leftmost point 20 corresponds to the structural state in the accumulation regime that has the lowest fractional crystallinity. This state may be fully amorphous or may contain some initial crystalline content. As energy is added, the fractional crystallinity increases and the chalcogenide material is transformed in the increased energy direction between a plurality of partially crystalline states along the 30th plateau. Selected accumulation states (structural states in the region) of accumulation) are marked with squares in Figure 1. After the accumulation of an amount of energy threshold, the fractional crystallinity of the chalcogenide material is increased sufficiently to effect a setting transformation characterized by a spectacular decrease of the electrical resistance and stabilization of the set state 40. The structural states in the accumulation regime can be referred to as states of material accumulation of chalcogenide. The structural transformations in the accumulation regime are unidirectional in the sense that they advance in the direction of increased energy within the plateau region 30 and are reversible only by first driving the chalcogenide material through the setting point 40 and refracting as it is described, for example, in patent applications? 527 and? 749. 'While not wishing to be bound by theory, it is believed that the addition of energy to a chalcogenide material in the accumulation regime leads to an increase in fractional crystallinity through the nucleation of new crystalline domains, growth of domains existing crystals or a combination thereof. It is believed that the elective resistance varies only gradually along the plateau 30 despite the increase in fractional crystallinity due to the formation or growth of crystalline domains in relative isolation from one another to prevent the formation of an adjacent crystalline network comprising the material of chalcogenide. This type of crystallization can be referred to as sub-percolation crystallization. The setting transformation coincides with a percolation threshold in which a contiguous interconnected crystal lattice is formed within the chalcogenide material. Such a network can form, for example when the crystalline domains are sufficiently large in size to collide or overlap with neighboring domains. Since the crystalline phase of the chalcogenide materials is more conductive and less resistive than the amorphous phase, the percolation threshold corresponds to the formation of a contiguous low-resistance conductive path through the chalcogenide material. As a result, the percolation threshold is marked by a dramatic increase in the strength of the chalcogenide material. The furthest point of the accumulation regime may be an amorphous state or a partially crystalline state that lacks an adjoining crystal lattice. Sub-percolation crystallization begins with an initial amorphous or partially crystalline state and proceeds through a plurality of partially crystalline states having incrementally higher fractional crystallinities until the percolation threshold and setting transformation occurs. An additional discussion of the behavior of chalcogenide materials in the accumulation regime is provided in patent applications? 319, '527 and 749 and in U.S. Patent Nos. 5,912,839 and 6,141,241; the disclosures of which are incorporated herein by reference. The regime to the right of line 10 of Figure 1 can be referred to as the gray-scale or gray-scale region regime. The grayscale regime extends from setting state 40 through a plurality of intermediate states (generally illustrated with the number 50) to a reset point or state 60. The various points in the gray scale regime can be called gray-scale states of the chalcogenide material. The selected gray scale states are marked with circles in Figure 1. Structural transformations in the gray scale regime can be induced by applying an electric current or impulse. voltage to a chalcogenide material. In Figure 1, an electric current pulse is indicated. In the gray scale regime, the resistance of the chalcogenide material varies with the magnitude of the applied electrical impulse. The resistance of a particular state in the gray scale regime is characteristic of the structural state of the chalcogenide material and the structural state of a chalcogenide material is determined by the magnitude of the current pulse applied in the gray scale region. The fractional crystallinity of the chalcogenide material decreases as the magnitude of the current pulse increases. The fractional crystallinity is higher for gray scale states or near the setting point 40 and decreases progressively as it approaches the state of restoration 60. The chalcogenide material is transformed from a structural state having an adjacent crystalline lattice in the setting state 40 to a structural state that is amorphous or substantially amorphous or partially crystalline without an adjacent crystal lattice in the reset state 60. The current pulse application having increased magnitude has the effect of converting portions of the preferred network to an amorphous phase and leads to a disruption or interruption of crystal paths of high contiguous conductivity in the chalcogenide material. As a result, the strength of the chalcogenide material increases as the magnitude of an applied current pulse increases in the gray scale region. In contrast to the accumulation region, the structural transformations that occur in the gray scale region are reversible and bidirectional. The response of a chalcogenide material to a current pulse is determined by the magnitude of the current pulse in relation to the magnitude of the current pulse associated with the initial state of the chalcogenide material at the time when the current pulse is applied. As indicated hereinabove, each state in the gray scale region can be identified by its resistance and a current pulse magnitude where the application of that magnitude of current pulse induces changes in the fractional crystallinity produced by the current. particular resistance value of the state. The application of a subsequent current pulse can increase or decrease the fractional crystallinity in relation to the fractional crystallinity of the initial state of the chalcogenide material. If the subsequent current pulse has a magnitude higher than the impulse used to establish the initial state, the fractional crystallinity of the chalcogenide material decreases and the structural state is transformed from the initial state in the direction of the state of restoration throughout the Gray scale resistance curve. Subsequently, if the subsequent current pulse has a magnitude lower than the impulse used to establish the initial state, the fractional crystallinity of the chalcogenide material is increased and the structural state is transformed from the initial state in the direction of the set state to the length of the gray scale resistance curve. An additional discussion of the properties of chalcogenide materials in the grayscale region can be found for example in U.S. Patent Nos. 5,296,716 and 5,414,271; the disclosures of which are incorporated herein by reference. An example of a device structure according to the present invention is shown in Figure 2. Figure 2 shows a cross-sectional view of a structure of a three-terminal device. The three terminals are marked T (l), T (2) and T (3). A plurality of these devices was formed on a 6-inch (6-inch) silicon wafer. The devices and layers on the platelet were formed using conventional ion bombardment, chemical vapor deposition, acid attack and lithography techniques. The structure includes a silicon wafer substrate 310, a thermal oxide layer 320, a lower terminal 330 which includes a conductive layer 340 formed from Ti or a combination of Ti and TiN and a carbon barrier layer 350, a SiOx / SiNx 360 insulating region, an intermediate terminal 370 formed of TiW, a pore filled with a chalcogenide material 380, an upper terminal 390 including a carbon 400 barrier layer and a conductive layer 410 including Ti and TiN, and a layer of Al 420. In this example the chalcogenide material 380 has the approximate composition Ge2Te2Sbs and is referred to as GST in Figure 2. Barrier layers inhibit diffusion and electromigration of material to the chalcogenide region and improve life of device cycle. Typical layer thicknesses are as follows: conductive layer 340 • (100 nm), barrier layer 350 (30 nm), intermediate terminal 370 (10-40 nm), barrier layer 400 (100 nm) and conductive layer 410 ( 100 nm). The pore region occupied by the chalcogenide material in the device of this example is cylindrical with a height of approximately 0.1 microns and a diameter of approximately 1 miera. Terminals 330, 370 and 390 are in electrical communication with the chalcogenide. The intermediate terminal 370 circumscribes the chalcogenide material 380. The terminals are separated by an insulating material in such a way that the electrical communication between the terminals occurs through the chalcogenide material. A schematic illustration of the central portion of a three-terminal device in accordance with the present invention is shown in Figure 3. The three-terminal device includes a pore 205 filled with a chalcogenide material 210 that is in contact with an electrical terminal. upper 240, a lower electrical terminal 250 and an intermediate electrical terminal 260. An insulating or dielectric material or materials 270 separates electrical terminals 240, 250 and 260. The pore may be cylindrical or non-cylindrical in shape. If the pore 205 is cylindrical, the intermediate terminal 260 is preferably ring-shaped. If the pore 205 is not cylindrical, the intermediate terminal 260 is preferably circumferential in shape. The presence of three terminals in the device of Figure 3 provides flexibility and selectivity to control the structural state of the chalcogenide material 210 or portions thereof in the pore of the device. The application of an appropriate electrical signal (eg, current pulse, voltage pulse) between a pair of terminals influences the structural state of the chalcogenide material in the vicinity of those terminals and can thereby influence the resistance between those terminals. The operating structural states can be selected from the accumulation states or the gray scale states or a combination thereof. Since the device includes three terminals and since the structural transformations of the chalcogenide material can be effected by providing electrical power through any pair of terminals selected from the three terminals, the three-terminal device provides multiple options for transformation of the structural state or strength of the chalcogenide material and allows to influence all selected regions or regions of the chalcogenide material in the pore 205 of the device. In the request 285, the three-terminal multi-bit chalcogenide storage device is described in which the application of electrical signals to different pairs of terminals effects structural transformations in different portions of the chalcogenide material within a pore. In the multi-bit storage device of the request 285, the selection of terminals provides the selective programming of specific and distinct portions within a continuous volume of chalcogenide material wherein each selectively-programmed portion is influenced by a particular pair of terminals and provides the storage of a binary bit or a non-binary bit. The different structural states correspond to interpretively different information content and can be characterized for example by fractional crystallinity of the chalcogenide material wherein the fractional crystallinity in a portion or region of a pore can differ from the fractional crystallinity in other portions or regions of a fraction. pore. In the logic devices of the present invention, particular pairs of terminals also influence the structural state of specific regions or portions of chalcogenide material within a pore. In the present logic devices, however, the fractional crystallinity per se in the separately programmable regions within a pore is not necessarily determinative of the operation, performance or function of the device. Of generally greater importance in the strength of the chalcogenide material and more specifically, the measured strength of the chalcogenide material between particular pairs of terminals. As more fully described hereinafter, the measured relative resistances between different pairs of terminals and the measured resistance pattern between the set of different pairs of terminals in a device can be used to provide logical functionality. The resistance measured between a pair of electrical terminals may depend not only on the strength of the chalcogenide material but also on the special arrangement and distribution of crystalline or amorphous regions within the chalcogenide material and the size and position of one or both terminals of the chalcogenide. a torque in relation to the volume of chalcogenide material influenced by a signal placed between the terminals. As discussed hereinabove, the crystalline phase of a chalcogenide phase change material has a lower resistance than the amorphous phase. Thus, the resistance measured between a pair of terminals is lower when it is possible for the current to pass fully through crystalline regions when it flows between terminals in a resistance measurement. The path traveled by an electric current as it flows from one terminal to another in a resistance measurement can be referred to herein as a current conducting path, current path, current flow path, current path, path current, etc. The resistance measured between a pair of electrical terminals depends on the resistance of chalcogenide material along the current path. Since the current path need not necessarily extend over the entire volume or cross-section of a pore, the resistance measured between terminals may differ from the strength of the chalcogenide material located in the pore. • The current path from one terminal to another in a resistance measurement extends along a continuous path that begins at one terminal and ends at the other terminal. The current path may or may not be a straight line path connecting the terminal. A circuit or bifurcated current path is also possible. The current flow occurs preferably along directions of low electrical resistance and to the extent possible given the magnitude and / or current density, the current flows through regions of low resistance of a material while avoiding high regions. resistance. Thus, in a phase change material that includes crystalline and amorphous regions, the current flow occurs preferably through the crystalline regions. If a continuous crystalline path extends from one terminal to the other in a resistance measurement is available, the current flow occurs preferably through this route while little or no current flows through amorphous regions. If such circumstances are present, the resistance measured between the terminals will correspond closely to the resistance of the crystalline state of the phase change material, even if amorphous regions are present. If a continuous crystalline path is not present or if the magnitude of the current or current density is high enough to saturate a crystalline path, the current flow occurs in amorphous regions and a correspondingly higher measured resistance is obtained. As the volume fraction of amorphous regions increases in a pore, the availability of a continuous crystalline path decreases and current flows incrementally through amorphous regions leading to an increasingly higher measured resistance. Based on the above considerations, both the volume fraction and crystallinity and the arrangement of crystalline regions within a chalcogenide material contained in the pore of a device. influence the resistance measured between a pair of terminals. The availability of a continuous crystalline path between a pair of terminals facilitates the reduction of the resistance measured between the terminals, while the lack of a continuous crystalline route restricts the current to flow at least partially through one or more regions. amorphous, leading by this to a higher measured resistance. For a particular volume fraction of crystalline regions, therefore, the arrangement or connectivity of crystalline regions is a contributing factor to the resistance measured between a pair of terminals. An arrangement that provides a continuous growing path extending between the terminals, for example, leads to a lower measured resistance than an arrangement in which the crystalline regions are disconnected, separated or otherwise isolated in whole or in part from each other. . The ability to control the arrangement and / or conductivity of the crystalline and amorphous regions together thus provides a degree of freedom in controlling the resistance measured between a pair of terminals. An additional factor influencing the measured resistance is the size or position of one or more electrical terminals in relation to the crystalline and amorphous regions of a phase change material contained in the pore of a device. If the size or cross section of a terminal is at least as large as the pore size or cross-section, the terminal fully overlaps the pore and is in electrical communication with the full cross section of the phase change material contained in the pore. pore and has direct access to any contiguous crystal path that may exist in the pore. In the situation where a contiguous crystal path is present, the current has the ability to flow directly from the terminal to its path without the need to flow through an amorphous region. The measured resistance can thus be closely approximated to that of the crystalline phase of the phase change material although amorphous regions may be present in the pore. Conversely, if the size or cross section of a terminal is smaller than the size or cross section of the pore, such that the terminal does not fully overlap the pore, the position of. The terminal in relation to any continuous crystalline path that may be present determines the access of the current flowing through the terminal to that path. If the terminal is superimposed on an entry point to the continuous crystalline path, the current can flow directly from the terminal to that path. If not, the current must flow through an amorphous region before finding the continuous crystal path and the measured resistance increases accordingly. An example of the importance of the position of electrical terminals in relation to crystalline and amorphous regions of a chalcogenide material of the pore can be described using the schematic illustrations provided in Figures 4A-4C. Figures 4A-4C show a pore 100 filled with a chalcogenide material having an amorphous region 110 and crystalline region 120 together with electrical terminals 130 and 140. The size of the electrical terminals 130 and 140 is smaller than the cross section of the pore 100, such that the terminals overlap only a portion of the cross section of the chalcogenide material occupying the pore. The position of terminals 130 and 140 varies in the different examples shown in Figures 4A-4C. In Figure 4A, the electrical terminals 130 and 140 both directly contact the regions 120 such that the resistance measured across the terminals 130 and 140 substantially corresponds to the resistance of the crystalline phase. In Figure 4A, the high resistance of the amorphous region 110 inhibits the transfer or leakage of current from the crystalline region 120 to the amorphous region 110. In Figure 4B, the electrical terminals 130 and 140 are contacted directly with the environment. amorphous region 110. If the current path occurs only in the amorphous region 110, the resistance measured across terminals 130 and 140 of the example shown in Figure 4B would correspond substantially to the resistance of the amorphous phase. A lower measured resistance is of the units 130 and 140 would result if the current flowed first from the amorphous region 110 to the crystalline region 120 and then back to the amorphous region 110. Regardless of the current path, however, the The current must flow at least partially through the amorphous phase and thus a measured resistance that is greater than that of the crystalline phase of the phase change material is "resulted." In Figure 4C, the terminal 130 is in contact. direct with the amorphous region 110 and the terminal 140 is in direct contact with the crystalline region 120. In this example, the current flow is expected to occur extensively in the crystalline region 120, but the current path should include, however, necessarily at least a portion of the amorphous region 110. The resistance measured in the example of 33 Figure 4C is expected to be intermediate between the resistances of the examples of Figures 4A and 4B. The principles summarized in the schematic examples illustrated in Figures 4A-4C apply in general independently of the particular shapes of the crystalline and amorphous regions. The low resistance measured between a pair of terminals is expected where there is a continuous crystalline path that electrically connects those terminals. The trajectory or crystalline route can be straight, in hooks, curve, arched, bifurcated, formed irregularly, etc. Figures 5A-5C show examples of more complex shapes of a continuous crystal path. The examples shown in Figures 5A-5C include pores 500 which include amorphous regions 510 and crystalline regions 520. Figure 5A shows a curved crystalline path. Figure 5B shows a bifurcated crystal path and Figure 5C shows a more complex crystal lattice. In each of these examples, the resistance measured through the pore is lower for a pair of electrical terminals, one of which is located somewhere where the upper part of the porq and one of which is located in the background of the pore, when both terminals are in direct electrical communication with the continuous crystalline trajectory ß, in such a way that the current flows through the crystal path without flowing substantially through the amorphous region. A higher measured resistance occurs when one or both terminals overlap, either fully or partially, an amorphous region, such that current flows through a portion of an amorphous region within the pore. The logic devices of the present invention include three or more terminals in electrical communication with a phase change material located in the pore of a device. Devices having three or more terminals provide a plurality of ways to select pairs of terminals and provide a plurality of resistances measured between a pair of terminals of the device. Within a given device having a particular crystalline volume fraction and a particular arrangement of amorphous and crystalline regions, therefore, it may be possible to measure different resistance values between different selected pairs of terminals. In the logic devices of the present invention, the resistance ratio measured between different pairs of terminals in a multi-terminal device (that is, three or more terminals) supports a logical functionality. Consider for example the three-terminal device illustrated schematically in Figure 6A. The device includes a pore 600 filled with a phase change material 610 having electrical terminals 605, 615 and 625 in electrical communication therewith. In this device, resistance measurements in pairs can be made between terminals 605 and 615, terminals 615 and 605 and 625 and terminals 615 and 625. Depending on the arrangement of crystalline and amorphous regions within phase change material 610, it can result in different resistances measured between different pairs of terminals. An important consideration is whether a continuous crystal path is present between a particular pair of terminals and how many pairs of terminals in a multi-terminal device are directly connected by a crystal path. For purposes of illustration, a binary logic system having the logical values "0" and "1" may be considered in which the different logical values correspond to resistance measures detectably different between a pair of electrical terminals. For practical convenience, it is preferable to have a wide difference between the measured resistances of the two logical states, such that the logical states can be distinguished and discriminated more easily. A method to obtain this objective is to associate a logical value to the situation where a continuous crystal path is present between one pair of terminals and the other logical value to the situation where a continuous crystal path is not present between a pair of terminals. In the last situation, in order for the current to flow between the terminals, it is necessary that it flows at least partly through an amorphous region. As a result, the measured resistance will be increased in relation to the first situation where the current flow occurs substantially within a continuous crystalline region. In a binary logic mode, a reference resistance can be defined and the resistance measured above the reference resistance can be assigned a logical value while the resistance measured below the reference resistance can be assigned to the other logical value A resistance above a reference value can be referred to as a high resistance or high logic state and can be associated for example with a logical value "l'X Similarly, a resistance less than a reference value can be termed as a low resistance or low logic state and can be associated for example with a logical value "O'X In another embodiment, the definition of a reference resistance is not necessary and the high and low logic values can be assigned to measured resistance states that have high and low resistance, respectively, wherein the measured high and low resistance states correspond to current paths between a pair of terminals that detectably differ in the degree to which current flows through one or more amorphous regions. The presence of differences in the resistances measured between different pairs of terminals in a multi-terminal device depends on the relative amounts and spatial distribution of crystalline and amorphous regions. In the embodiment shown in Figure 6A, for example, if the chalcogenide material 610 is uniformly or homogeneously amorphous or crystalline, the resistances measured between the three pairs of terminals would be substantially identical. Small variations in measured resistance can occur due for example to differences in the spatial separation of different pairs of terminals, differences in terminal sizes of different terminals, differences in the contact area of different terminals, etc., however, such differences They are secondary in comparison to any differences in the degree to which the current path is. crystalline or amorphous between different pairs of terminals. Where the structural state of the chalcogenide is non-homogeneous or non-uniform, it becomes possible to observe appreciable differences in the resistance measured between different pairs of terminals. Figure 6B shows an example of a modality of the three-terminal device shown in Figure 6A having inhomogeneous distribution or non-uniform distribution of crystalline and amorphous regions. The device of Figure 6B includes electrical terminals 605, 615 and 625 in electrical communication with a phase change material contained in the pore 600, wherein the phase change material includes an amorphous region 620 and a crystalline region 630. In this device, any current flowing to or from the terminal 625 must necessarily pass through a substantial distance within the amorphous region 620 thereby leading to a high measured resistance value. The resistance measured between terminals 625 and 605 to terminals 625 and 615 are therefore high compared to the resistance measured between terminals 605 and 615 for which a continuous crystal path is available for current flow. The measurement resistance values will generally be present between a pair of terminals when one or both of the terminals are surrounded by an amorphous region, so that no direct contact with a crystalline region is possible. The terminal 625 shown in Figure 6B is an example of a terminal surrounded by an amorphous region, Figure 6C shows another example where the terminal 625 is surrounded by an amorphous region. Figure 6C shows a three terminal device having terminals 605, 615 and 625 in electrical communication with a pore 600 containing a phase change material having an amorphous region 635 and crystalline region 640. The pattern of resistances between the pairs of terminals in Figure 6C corresponds to that of Figure 6B . That is, the measured resistances between terminals 625 and 605 are high, while the resistance measured between terminals 615 and 605 is low. The example of Figure 6C shows that the -amorphic region does not need to be spread across the entire diameter or cross-section of the pore to create a high-resistance driving path-between a pair of terminals. High values of measurement resistance can also result when each terminal of a pair is in direct contact with a crystalline region if an intermediate amorphous region extends through the full diameter or section. Cross section of the pore is present between the terminals. An example of such a situation is illustrated in Figure 6D which shows a three terminal device having electrical terminals 605, 615 and 625 in electrical communication with a pore 600 containing a material with phase change having amorphous regions 645 and crystalline regions 650 and 655. Note that terminal 625 is in contact with crystalline region 650. In the example of Figure 6D, however, the current flowing between terminal 625 and either terminal 605 or terminal 615 it necessarily flows through the amorphous region 645, with the result that the measurement resistances between terminal 625 and terminal 605 or terminal 615 are high. The measurement resistance between terminals 605 and 615, in contrast, remains low since a continuous crystal path extends between this pair of terminals. In the examples of Figures 6B, 6C, 6D, it can be said that amorphous regions 620, 635 and 645 resistively shield terminal 625 of terminals 615 and 615. Resistive shielding occurs when an amorphous region is of such size and / or form to prevent the flow of current to or from a terminal through a crystalline conductive path. Instead, the flow of current to or from a resistively shielded terminal necessarily occurs at least partly through an amorphous region, such that the measured resistance between an armored terminal and at least one other terminal is more high that if there was a continuous crystal current path available. A particular terminal can be resistively shielded from some terminals, but not all terminals of a multi-terminal device. In the examples shown in Figures 6B, 6C and 6D for example, the terminal 625 is resistively shielded from each of the terminals 605 and 615 and each of the terminals 605 and 615 is resistively shielded from the 625 terminal. , terminals 605 and 615 are not resistively shielded from each other, since a continuous crystal path is available for the current flow between these terminals. Amorphous regions such as regions 620, 635 and 645 in the examples of cracks 6B, 6C and 6D can be referred to herein as resistively armored amorphous regions since they are used to resistively shield a terminal from other terminals. A resistively shielded amorphous region may have an arbitrary shape, provided that the shape is such that a continuous crystal path between at least one pair of terminals is not available or the shape is such that the measurement resistance between at least one pair of terminals is higher than it would be if the resistively armored amorphous region was absent. Note that a resistively shielded amorphous region does not prevent current from flowing between a resistively shielded terminal and other terminals, but rather acts to increase the measured resistance between a resistively shielded terminal and at least one other terminal in a multiple device. terminals, in relation to a situation where the amorphously resisting amorphous region is absent. A resistively resistive amorphous region may or may not completely surround a terminal and may or may not extend through a full cross-sectional dimension of a pore. In the logic devices of the present invention, one has the ability to selectively control the formation of amorphous regions in the pore region of the phase change device by means of the application of appropriate input signals and are able to direct the placement of one or more resistively shielded amorphous regions, such that the measurement resistance between particular pairs of terminals can be made selectively high. Amorphously shielding resistive regions can also be selectively separated by means of selective crystallization in the application of appropriate input signals. In a binary logic system, a high measurement resistance resulting from the proper placement of a resistively armored amorphous region may correspond to a logical value, while a low measured resistance resulting from the absence of a resistively armored resistive region may correspond to the other logical value By reading the relative resistances (ie, high vs. low) between different pairs of terminals, a binary logic functionality can be defined and the application of the devices of the present invention as logic devices can be obtained in a manner that is now described. As indicated hereinabove, the device shown in Figure 2 and the schematic illustration of the central portion of a three-terminal device as shown in Figure 3 are representative of three-terminal devices according to the present invention. A further example of a device according to the present invention is shown in Figure 7, which shows a cross-sectional view of a three-terminal device structure. A plurality of these devices was formed on a 15-centimeter (6-inch) silicon wafer. The devices and layers of the platelet were formed using conventional ion bombardment, chemical vapor deposition, acid attack and lithography techniques. The structure includes a silicon wafer substrate 705, a lower wafer 715 including a conductive layer 720 formed of a combination of Ti and TiN and a carbon barrier layer 725, insulating SiN? 730, an intermediate terminal 735 formed from TiW, a pore 740 containing a chalcogenide material 745 extending beyond the pore diameter, an upper terminal 750 which includes a carbon 755 barrier layer and a conductive layer 760 including Ti and TiN and a Ti layer 765. Terminals 750, 735 and 715 may be referred to herein as upper, intermediate and lower terminals, respectively. In this example, the chalcogenide material 745 has the approximate composition of GeTe2Sb5. The pore region occupied by the chalcogenide material in the device of Figure 7 has a diameter of approximately 500 nanometers. Terminals 715, 765 and 750 are in electrical communication with the chalcogenide. The intermediate terminal 765 circumscribes the pore 740. The terminals are separated by an insulating material, in such a way that the electrical communication between the terminals. occurs mainly through the chalcogenide material. The device shown in figure 7 differs from the. device shown in Figure 2 mainly in the contact area between the phase change material and the upper terminal. In the device of Figure 2, an additional polishing step has been included in manufacturing the device to separate those portions of the phase change material that extend beyond the pore diameter. In the device of Figure 7, the phase change material that resides beyond the pore diameter is not removed. As a result, the contact area between the upper terminal and the phase change material in the device of figure 7 is greater than that of the device shown in figure 2. The device shown in figure 7 has been experimented to demonstrate the formation selective of resistively armored amorphous regions. An initial state was selected in which the chalcogenide material 745 was in a mainly crystalline state, in which a continuous crystalline path was present between each of the three pairs of terminals present. One or more amorphous regions may be present in the initial state, but no resistively shielding region is present. In this initial state, the resistances were measured through the different pairs of terminals with the following results: 8.5 KO (resistance measured between terminals 715 and 750), 14 KO (resistance measured between terminals 715 and 735) and 4 KO (resistance measurement between terminals 735 and 750). In accordance with the present invention, amorphous regions in general and resistively amorphous regions in particular, can be selectively formed or erased in a phase change material or chalcogenide material contained within the pore of a device by providing an electrical signal appropriate between pairs of electrical terminals. Electrical signals may be in the form of current or voltage and may be persistent or pulsed. Electrical signals that lead to a change in the crystalline volume fraction or alteration of the structural state of a phase change material in the pore of a device can be referred to hereinbelow as programming signals. The programming signals alter the crystalline volume fraction or structural state by inducing the formation of new amorphous regions, the enlargement or reduction of existing amorphous regions and / or the deletion (ie, removal / crystallization) of existing amorphous regions. In a preferred unit, the programming signals create or destroy the resistively armored amorphous regions by transforming the crystalline regions or influencing the size and / or collectivity of existing amorphous regions. The size and / or collectivity can be increased to promote the formation of resistively armored amorphous regions from crystalline regions or amorphous non-resistively armored regions. Similarly, the existing resistively shielded amorphous regions can be erased in whole or in part or disconnected to form non-resistively amorphous regions and / or crystalline regions.

EXAMPLE 1 The selective formation of resistively armored amorphous regions has been demonstrated using the device shown in Figure 7 by means of the application of appropriate programming signals. Current pulses were used as programming signals in this demonstration. In a first experiment, the device was in the initial state described hereinabove and a current pulse was subsequently applied between terminals 735 and 750. The current pulse had an amplitude of about 2-5 milliamperes and a duration of approximately 100 nanoseconds After applying the current pulse, the resistances between the different pairs of terminals were measured. The following results were obtained: 8.0 KO (measured resistance between terminals 715 and 750, compared to 8.5 KO in the initial state), 50 KO (measured resistance between terminals 715 and 735, compared to 14 KO in the initial state) and 34 KO (measured resistance between terminals 735 and 750, compared to 4 KO in the initial state). The results indicate that the resistance measured between the intermediate terminal 735 and either the terminal 715 or 750 increases dramatically, while the resistance between the terminals 715 and 750 is essentially unchanged. From the point of view of the logic applications of the present invention, the results show that the programming pulse used in this experiment has the effect of resistively shielding the intermediate terminal 735 of the other terminals. The resistive shield is a consequence of the selective formation of a resistively resistive amorphous region or regions in the vicinity of the intermediate terminal 735. The programming pulse applied in this example can thus be referred to as the shield pulse with respect to the terminal 735. that the shielding corresponds to the formation of a resistively armored amorphous region or regions, a shielding pulse may also be referred to herein as a depreciation pulse. A depreciation pulse, more generally in the context of the present invention, is an input signal that acts to increase the volume fraction of amorphous regions and / or the arrangement of amorphous regions between a pair of input terminals.

EXEMPL02 The resistive shield of the lower terminal 715 was demonstrated in an additional experiment using the device shown in Fig. 7. The device-was once again initialized to a state in which the phase change material was sufficiently crystalline to provide trajectories continuous crystals between each of the three pairs of terminals in the device. The resistances measured between the terminals in this initial state were: 8 KO (measured resistance between terminals 715 and 750), 14 KO (measured resistance between terminals 715 and 735) and 6 KO (measured resistance between terminals 735 and 750). A programming pulse that has an amplitude of approximately 2-5 milliamps and duration of approximately 100 nanoseconds was then applied between terminals 715 and 735. The resistances between the three pairs of terminals were subsequently measured with the following results: 1500 KO (resistance measurement between terminals 715 and 750), 1200 KO (resistance measured between terminals 715 and 735) and 8.5 KO (resistance measured between terminals 735 750). The results indicate that the resistance measured between the lower terminal 715 and either the terminal 735 or 750 increases dramatically, while the resistance between the terminals 735 and 750 is essentially unchanged. From the point of view of the logical applications of the present invention, the results show that the programming pulse used in this experiment has the effect of resistively shielding the inner terminal 715 of the other terminals. The resistive shielding is a consequence of the selective formation of a resistively armored amorphous region or regions in the vicinity of the lower terminal 715. The programming pulse applied in this example can thus be termed as a shield pulse or amorphization pulse with respect to terminal 715.

EXAMPLE 3 The two preceding examples demonstrate the selective formation of amorphous regions in the vicinity of terminals 715 and 735 through the use of appropriate amorphization pulses. In this example, additional experiments have been accomplished to demonstrate the removal or disruption of amorphous regions by means of selective crystallization. Selective crystallization can be effected by applying a crystallization signal (eg current or voltage) that is pulsed or persistent and that leads to a sufficient conversion of a resistively armored amorphous region to a crystalline phase to allow current flow emanating ao of a terminal occurs substantially through a crystalline route. By means of the application of a crystallization signal, a resistively shielded terminal can be transformed to a non-resistively shielded terminal. More generally, in the context of the present invention, a crystallization signal is a signal that acts to increase the crystalline volume fraction and / or arrangement of crystalline regions between a pair of input terminals. In this example, the device shown in Figure 7 is used in an initial state, in which the intermediate terminal 735 is resistively shielded. The resistances between the terminals in the initial state are as follows: 10 KO (resistance measured between terminals 715 and 750), 55 KO (resistance measured between terminals 715 and 775) and 67 KO (measured resistance between terminals 735 7'50). The high resistance measured between the intermediate terminal 735 and the terminals 715 and 750 demonstrates the presence of a resistively armored amorphous region in the vicinity of the intermediate terminal 775, while the low resistance measured between the upper and lower terminals 750 and 715 makes The flow of current occurring substantially through a crystalline path without significant interference of the resistively armored amorphous region or regions in the presence of the intermediate terminal 735 or other resistively armored amorphous regions is evident. A crystallization current pulse having an amplitude of about 1-2.5 milliamperes and a duration of about 600 nanoseconds was subsequently applied between the intermediate terminal 735 and the lower terminal 715. After application of the crystallization pulse, the resistance between the terminals was measured with the following results: 8 KO (measured resistance between terminals 715 and 750), 14 KO (measured resistance between terminals 715 and 735) and 6 KO (measured resistance between terminals 735 and 750). The measured resistance flowing to or from the intermediate terminal 735 has decreased considerably and demonstrates the selective crystallization induced by the crystallization pulse of this example. The resistance measured between the upper and lower terminals 715 and 750 is still low and is not significantly influenced by the crystallization pulse.

EXAMPLE 4 In this example, the device shown in the figure 7 is used in an initial state in which the lower terminal 715 is resistively shielded. The resistances between the terminals in the initial state are as follows: 1300 KO (measured resistance between terminals 715 and 750), 1700 KO (resistance measured between terminals 715 and 735) and 5.5 KO (resistance measured between terminals 735 and 750). The high resistance measured between terminal 715 and terminals 735 and 750 makes the presence of a resistively resistive amorphous region in the vicinity of the lower terminal evident. 715, while the low resistance measured between the upper and intermediate terminals 750 and 735 makes evident the current flow that occurs substantially through a crystalline path without significant interference of the resistively armored amorphous region or regions in the presence of the lower terminal 715 or other amorphously resisting armor regions. A current pulse crystallization having an amplitude of about 1-2.5 milliampers and a duration of about 600 nanoseconds was subsequently applied between the intermediate terminal 735 and the lower terminal 715. After the 'application of the crystallization pulse, the resistance between the terminals was measured with the following results: 30 KO (measured resistance between terminals 715 and 750), 34 KO (measured resistance between terminals 715 and 735) and 6.5 KO (measured resistance between terminals 735 and 750). The measured resistance flowing to or from the lower terminal 715 has decreased considerably and attests to the selective crystallization induced by the crystallization pulse of this example. The resistance measured between the upper and intermediate terminals 750 and 735 is still low and is not significantly influenced by the crystallization pulse.

EXAMPLE 5 The above examples have demonstrated the ability to utilize the amorphization and crystallization signals to selectively form or disrupt resistively armored amorphous regions in the vicinity of selected terminals of a multi-terminal caliber device to thereby selectively influence the pattern of 'Resistances between different pairs of terminals in a device with multiple terminals. In this example, the logical functionality of a three-terminal chalcogenide device is demonstrated based on the ability of the input signals to increase or decrease the resistance between particular pairs of terminals by means of amorphization or selective crystallization of the material. of intermediate chalcogenide. The device indicated in Figure 7 is a representative device according to the present invention and can be used to illustrate logical functionality. In this example, the use of the device shown in Figure 7 is considered to carry out the logical function of O. "In the logical function OR, 2 inputs are provided to a device and are processed to provide an output according to the following true table: Input 1 Input 2 Output 0 0 0 0 1 1 .1 0 1 1 1 1 where the inputs and outputs correspond to binary states 0 and 1. In a conventional logic device, states 0 and 1 commonly correspond to low and high voltages, respectively. In the logic devices of the present invention, the resistance measured between pairs of terminals can be associated with the states 0 and 1 used to define truth tables for logic operations. In one embodiment of the present invention, states 0 and 1 correspond to low and high resistances, respectively and in another embodiment, states 0 and 1 correspond to high and low resistances, respectively. In this example, the logical function of O is illustrated and it is chosen that the low and high resistances of measurements correspond to logical values 0 and 1, respectively. In order to comply with the logic truth table, two independent inputs and one independent output are required. In the logic devices of the present invention, the signals applied through two different pairs of terminals correspond to the required inputs and the measurement resistance between a third pair of terminals corresponds to the output. Since the device of the figure 7 includes three terminals, three independent pairs of ar. terminals are present to provide three independent measured resistances and / or means to provide signals that can be associated with logical inputs and outputs. For purposes of this example, it is chosen that the lower terminal 715 and upper terminal 750 are a pair of terminals corresponding to an input terminal and the intermediate terminal 735 and upper terminal 750 are a pair of terminals corresponding to a second input. The resistance measured between the lower terminal 715- and the. Intermediate terminal 735 corresponds to the output. The choice of terminals associated with the inputs and outputs made in this example is used for illustrative purposes only; other schemes for assigning particular pairs of terminals to inputs and outputs are possible and are within the scope of the present invention. The input signals of the logic device of this example are provided in the form of current pulses applied between a first pair of terminals (terminals 715 and 750) and a second pair of terminals (terminals 735 and 750). In this example, input signals are provided in the form of crystallization and amorphization pulses, respectively. As described hereinabove, a crystallization pulse applied between a pair of terminals alters the structural state of the phase change material between a pair of terminals, in such a way as to promote the formation of a substantially crystalline path for the flow of current between the terminals. A crystallization pulse can thus provide a low measurement resistance between a pair of terminals in the devices of the present invention and in the context of this example, constitutes an input signal corresponding to a logical value of 0. Similarly, a amorphization pulse, between a pair of terminals alters the structural state of the phase change material between a pair of terminals in such a manner to promote the formation of amorphous regions and / or amorphous regions resistively shielded in the path for the flow of current between the terminals. A amorphization pulse can thus provide a high resistance measured between a pair of terminals and in the context of this example, - it constitutes an input signal corresponding to a logical value of 1. In a preferred embodiment of the present invention, the signals input act independently and do not interfere, so that the portion of the phase change material influenced by an input signal provided between a pair of input terminals does not materially alter the phase change material influenced by an input signal provided between a different pair of input terminals. Interference and overlap of the region of influence of signals applied between different pairs of terminals has been discussed in US Patent Application Serial No. 10 / 657,285. In this preferred embodiment, in addition to providing logical functionality, the devices of the present invention can also provide non-volatile storage of the input signals. A crystallization pulse, for example, between a pair of input terminals would promote the formation of a continuous crystal path between terminals and would facilitate a low resistance measured between the input terminals thereby providing storage of the input value 0. Similarly, the apiication of a depreciation signal between a pair of terminals provides for the storage of an input value 1. The non-volatile storage of input values may be comprised in where the input signals interfere with each other, as in where the portions of materials of phase change influenced by input signals applied between different terminals overlap or where the thermal energy or electrical energy emanating from one region is triggered to or otherwise influences another region as described in US Patent Application No. of series 10 / 657,285. Depending on the extent of interference, the interference can lead to alterations in the structural state or resistance measured between a pair of terminals when a last signal is applied to a different pair of terminals. In such circumstances, storage of the above input value may be volatile, rather than non-volatile, if the reference extent is sufficient to materially alter the structural state or measured resistance between the terminals to which the previous signal was applied. Independently of any overlap or interference of the input signals, the logic outputs of the devices of the present invention are faithfully shaped according to the truth tables described in the examples herein at the input signals. Modes in which the input signals interfere or are not both within the scope of the present invention, as modes in which the input signals are stored non-volatile or not. Factors such as pulse amplitude, pulse voltage, pulse duration, device dimensions, selection of phase change material, etc., can be used to influence whether the signals or no signal is provided through different pairs of terminals. input interfere and if so, the extent of the interference. See US patent application Serial No. 107657,285 for additional information. The output of the logic device of this example corresponds to the resistance measured between the lower terminal 715 and the intermediate terminal 735 and is obtained immediately after the application of one or more input signals between one or more other pairs of terminals in the device. A high measured resistance corresponds to an output value of 1, whereas a low measured resistance corresponds to an output value of 0. As described hereinabove, the measured resistance is mainly influenced by the relative proportion and spatial arrangement and / or contiguity of crystalline and amorphous regions in the path of current between the lower terminal 715 and the intermediate terminal 735. The presence of resistively armored amorphous regions promotes high resistance and manifestation of an output value of 1. The presence of a continuous crystalline path that is not saturated or otherwise limited by the current used in the resistance measurement promotes low measured resistance and manifestation of an output value of O. Alternatively, the output can be defined as the measured current flowing between a pair of output terminals. The current output naturally follows the resistance since a low resistance leads to a higher current for a given voltage than the high resistance. Thus, the current level (high vs. low) can also be used as an output signal in terms of measurement resistance. Since the resistance of a phase change material varies with the composition of the phase change material, the resistance measured for a particular volume fraction and arrangement of crystalline and / or amorphous regions in a logic device according to the present invention varies with the phase change material used in the device. The determination of whether a particular measured resistance is high or low and consequently if a particular output is 1 or 0, may depend on the choice of the phase change material used in the device. In one embodiment of the present invention, specific resistance values can be assigned to high and low resistance output states. -In another mode, a reference resistance can be selected where the measured output resistors exceed the reference resistance corresponding to high resistance and an output 'of 1 and where the measured output resistances are less than the' reference resistance they correspond to low resistance and an output of 0. Since the measured resistance between the amorphous and crystalline phases commonly differ by at least a factor of two and often by an order of magnitude or more, it is straightforward to establish a reference resistance that delineates way «Does not ambiguous the high and low output values. The practical ease with which even small differences in resistances can be reliably measured further facilitates and makes flexible the choice of a reference resistor. A summary of the operation characteristics of this embodiment of the logic device of the present invention is presented in the table below. Input 1 is the input signal applied between terminals 715 and 750, input 2 is the input signal applied between terminals 725 and 750 and the output is the resistance measured between terminals 735 and 750 after the application of the two entrance signs. The inputs are listed as crystallization pulses or depreciations where the pulse amplitude and durations are comparable with those described in Examples 1-4 hereinabove.

In this example, the outputs are determined with respect to a resistance of 20 KO. Any resistance between 14 and 50 KO will serve as an appropriate reference resistance in this example. The "examination of the relationship between the inputs and outputs shows that the device in this example performs the logical operation 0.

EXAMPLE 6 This example describes a device that carries out the logical operation of Y. The device of this example corresponds to that described in example 5 described hereinabove, but the procedure for associating logical values with the resistance differs. In Example 5 above, -the logical value is 0 is assigned to a crystallization input signal the logical value of 1 is assigned to a depreciation input signal and the output values of 0 and 1 'are assigned to low and high output resistances, respectively. 5 In this example, a different assignment of logical values is performed. Specifically, the logical value of 0 is assigned to a crystallization input signal and the output values of 0 and 1 are assigned to high and low resistance outputs respectively. As in example 5 above, the device input signals in the form of current pulses applied between a first pair of terminals (terminals 715 and 750) and a second pair of terminals (terminals 735 and 750) and the output corresponds to the resistance measured between the lower terminal 715 and the intermediate terminal 735. Using as input signals the pulses described in example 5, a reference resistance between 14 and 50 KO and the alternative assignment of logical values described for this example, the following table of output characteristics is obtained: -OR Thus, this example shows the logic according to the functionality Y. Although the above illustrative examples have emphasized devices having three terminals in electrical communication with a phase change material, it is evident that the principles of operation and logical functionality extend analogously to multiple terminal devices in general. Two or more input signals can be applied to different pairs of input terminals and one or more output signals can be obtained by measuring the resistance between different pairs of output terminals. Logical functionality can similarly be defined in terms of the relationship between the types of input signals (eg crystallization or low or high depreciation, 0 or 1 etc.) applied, the number of each type of input signal and the signal or exit signs. As in the three terminal embodiments illustrated above, truth tables can be developed for logical operations of multiple terminal devices.

The disclosure and discussion summarized hereinabove are illustrative and are not intended to limit the practice of the present illustration. While what is believed to be preferred embodiments of the present invention has been described.Those skilled in the art will recognize that other and additional changes and modifications may be made therein without departing from the spirit of the invention and are intended to claim all such changes and modifications as fall within the full scope of the invention. In the following claims, which include all equivalents in combination with the above disclosure and knowledge commonly available to persons skilled in the art, which define the scope of the present invention.

Claims (30)

1. CLAIMS 1. An electronic device, characterized in that it comprises: a phase change material; a first terminal in electrical communication with the phase change material; a second terminal in electrical communication with the phase change material. a third terminal in electrical communication with the phase change material; wherein the electrical resistance measured between the first and second terminals differs from the electrical resistance measured between the first and third terminals. The device according to claim 1, characterized in that the phase change material in a chalcogenide material. 3. The device according to claim 1, characterized in that the phase change material is transformable between a crystalline phase and an amorphous phase, the crystalline phase and the amorphous phase have different electrical resistances. 4. The device according to claim 1, characterized in that the phase change material comprises S, Se or Te. 5. The device according to claim 4, characterized by the phase change material further comprises Ge or Sb. 6. The device according to claim 4, characterized in that the phase change material further comprises As or Yes. The device according to claim 4, characterized by the phase change material further comprises an element selected from the group consisting of Al, In, Bi, Pb, Sn, P and 0. 8. The device in accordance with Claim 1, characterized in that the difference phase in measured electrical resistances is at least a factor of two. 9. The device according to claim 1, characterized in that the difference in measured electrical resistances is at least an order of magnitude. The device according to claim 1, characterized in that the electrical resistance measured between the first and second terminals differs from the electrical resistance measured between the second and third terminals. 11. The device according to claim 1, characterized in that the device is a logical device. 12. The device according to claim 11, characterized in that the logic device is a device 0. 13. The device according to claim 11, characterized in that the logic device is a device of Y. 14. The device according to claim 1, characterized in that the phase change material includes a crystalline region and an amorphous region. The device according to claim 1, characterized in that the phase change material includes an amorphous region resistively shielding one of the terminals. 16. The device according to claim 15, characterized in that the resistively resistive amorphous region is in physical contact with the resistively shielded terminal. The device according to claim 16, characterized in that the resistively resistive amorphous region substantially covers the resistively shielded terminal. 18. The device according to claim 1, characterized in that the phase change material includes a continuous crystal path of at least one pair of terminals. 19. A method for putting into operation an electronic device, the device comprises a phase change material and three or more terminals in electrical communication with it, the method is characterized in that it comprises the steps of: applying a first signal between a first pair of the terminals of the device and apply a second signal between a second pair of the terminals of the device. 20. The method of compliance with the claim 19, characterized in that one of the first and second signals is a depreciation signal. 21. The method of compliance with claim 20, characterized in that the amortization signal forms an amorphously resisting armor region. The stuffed according to claim 19, characterized in that one of the first and second signals is a crystallization signal. 23. The method of compliance of the claim 22, characterized in that the crystallization signal overcomes a resistively armored amorphous region.
2. 2 . The method of compliance with claim 19, characterized in that the first and second signals are electrical signals. 25. The conformity method 24, characterized in that the electrical signals are current pulses. 26. The method according to claim 19, characterized in that the first signal modifies the measurement resistance between the first pair of terminals. 27. The method according to claim 26, characterized in that the first signal does not substantially change the measurement resistance between the second pair of terminals. 28. The method of compliance with the claim 26, characterized in that the second signal modifies the measured resistance between the second pair of terminals. 29. The method according to claim 19, characterized in that it further comprises the step of measuring the resistance between a third pair of the terminals. 30. The. method according to claim 19, characterized in that it further comprises the step of measuring the current between a third pair of terminals.