KR20240019674A - Memory device including switching material and phase change material - Google Patents

Abstract

A memory device according to an embodiment includes a memory cell including a selection layer and a phase change material layer, and a control unit, the selection layer including a switching material, and the phase change material layer including a phase change material. , the control unit may apply a write pulse to the selection layer and the phase change material layer, and control the polarity, peak value, and shape of the write pulse.

Description

Memory device including switching material and phase change material}

The present disclosure relates to memory devices including switching materials and phase change materials.

Recently, with the miniaturization and increased performance of electronic devices, there is a demand for memory devices that can store information in various electronic devices such as computers and portable communication devices. These memory devices include PRAM (Phase-change Random Access Memory), RRAM (Resistive Random Access Memory), and MRAM (Magnetic Memory), which can store data using the characteristic of switching between different resistance states depending on the applied voltage or current. There are memory devices such as Random Access Memory), etc. These memory devices may include ovonic threshold switch (OTS) materials using chalcogenide materials and phase change materials (PCM). However, OTS and PCM, which are made of amorphous chalcogenide materials, experience a characteristic shift over time, which reduces the read window margin, making it difficult to implement a multi-level cell.

The present disclosure provides a memory device with a high read window margin.

The present disclosure provides a memory device that enables segmentation of states to implement multi-level.

According to one embodiment, a memory device includes a memory cell including a selection layer and a phase change material layer connected in series with each other, and a control unit, wherein the selection layer includes a switching material, and the phase change material layer includes a phase change material layer. The control unit may apply a write pulse to the selection layer and the phase change material layer and control the polarity, peak value, and shape of the write pulse.

The controller may control the resistance of the phase change material by controlling the length of the fall time of the writing pulse.

The control unit applies a first write pulse to the memory cell, and the first write pulse may be a rectangular reset pulse with a negative polarity and a first peak value.

The memory cell may have a first logic state in which both the switching material and the phase change material have the highest resistance when the first write pulse is applied.

The control unit applies a second write pulse to the memory cell, and the second write pulse may be a rectangular reset pulse with a negative polarity and a second peak value that is smaller than the first peak value.

The memory cell may have a second logic state in which both the switching material and the phase change material have high resistance when the second write pulse is applied.

The control unit applies a third write pulse to the memory cell, and the third write pulse may be a rectangular reset pulse with positive polarity and a second peak value smaller than the first peak value.

When the third write pulse is applied, the memory cell may have a third logic state in which the switching material has low resistance and the phase change material has the highest resistance.

The control unit applies a fourth write pulse to the memory cell, and the fourth write pulse may be a trapezoidal set pulse with a negative polarity and a second peak value smaller than the first peak value.

When the fourth write pulse is applied, the memory cell may have a fourth logic state in which the switching material has high resistance and the phase change material has low resistance.

The controller applies a fifth write pulse to the memory cell, and the fifth write pulse has a positive polarity, a second peak value smaller than the first peak value, and a trapezoidal shape with a second fall time length. It can be a set pulse.

When the fifth write pulse is applied, the memory cell may have a fifth logic state in which both the switching material and the phase change material have low resistance.

The control unit applies a sixth write pulse to the memory cell, wherein the sixth write pulse has a positive polarity, a second peak value smaller than the first peak value, and a first fall time length longer than the second fall time length. It may be a trapezoidal set pulse with a falling time length.

When the sixth write pulse is applied, the memory cell may have a sixth logic state in which the switching material has low resistance and the phase change material has the lowest resistance.

The selection layer includes at least one of a first element containing germanium (Ge), a second element containing arsenic (As) or antimony (Sb), tellurium (Te), selenium (Se), or sulfur (S). A third element including one, and indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen (N), and silicon. It may include a switching material made of a chalcogenide material containing a fourth element including at least one of (Si), calcium (Ca), and phosphorus (P).

The selection layer may include a switching material that exhibits ovonic threshold switching material characteristics.

The switching material may have resistance that changes depending on the polarity of the applied write pulse.

The switching material may have resistance that changes depending on the peak value of the applied write pulse.

The phase change material layer includes a first element containing germanium (Ge), a second element containing arsenic (As) or antimony (Sb), tellurium (Te), selenium (Se), or sulfur (S). A third element containing at least one of, and indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), and nitrogen (N) , may include a phase change material made of a chalcogenide material containing a fourth element including at least one of silicon (Si), calcium (Ca), and phosphorus (P).

The phase change material may have resistance that changes depending on the type of applied write pulse.

The phase change material may have resistance that changes depending on the length of the fall time of the applied write pulse.

According to one embodiment, the memory device includes a selection layer including a switching material, a phase change material layer connected in series with the selection layer, and the selection layer and the phase change material layer having a first polarity and a third fall time. It may include a control unit capable of applying a seventh write pulse having a length, and an eighth write pulse having a second polarity opposite to the first polarity and a second falling time length different from the third falling time length. there is.

The seventh write pulse may have a first peak value, and the eighth write pulse may have a second peak value different from the first peak value.

According to the disclosed embodiment, the memory device controls the polarity, peak value, shape, and fall time length of the write pulse, has a high read window margin, and enables segmentation of the state, thereby enabling multi-level ) can be implemented.

1 is a block diagram of a memory device according to one embodiment.
2 is an example equivalent circuit of a memory device.
Figure 3 is a cross-sectional view of a memory cell according to one embodiment.
FIGS. 4A to 4C are graphs illustrating types of voltage pulses that can be applied to a switching material according to an embodiment.
5A and 5B are graphs showing threshold voltages of memory cells according to one embodiment.
FIGS. 6A to 6D are graphs exemplarily showing types of voltage pulses that can be applied to a phase change material according to an embodiment.
FIGS. 7A to 7F are graphs exemplarily showing types of voltage pulses that can be applied to memory cells according to one embodiment.
FIG. 7G is a graph showing the states of memory cells according to the voltage pulses of FIGS. 7A to 7F.
8A to 8C are graphs illustrating types of voltage pulses that can be applied to memory cells according to another embodiment.
Figure 9 is a perspective view of a memory device according to one embodiment.
Figure 10 is a block diagram schematically showing a neuromorphic device including a memory device.

Hereinafter, a memory device including a switching material and a phase change material will be described in detail with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Additionally, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

Hereinafter, the term “above” or “above” may include not only what is directly above in contact but also what is above without contact. Singular expressions include plural expressions unless the context clearly dictates otherwise. Additionally, when a part "includes" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary.

The use of the term “said” and similar referential terms may refer to both the singular and the plural. Unless the order of the steps constituting the method is clearly stated or stated to the contrary, these steps may be performed in any appropriate order and are not necessarily limited to the order described.

The connections or connection members of lines between components shown in the drawings exemplify functional connections and/or physical or circuit connections, and in actual devices, various functional connections, physical connections, and or may be represented as circuit connections.

The use of all examples or illustrative terms is simply for explaining the technical idea in detail, and the scope is not limited by these examples or illustrative terms unless limited by the claims.

1 is a block diagram of a memory device according to one embodiment.

Referring to FIG. 1 , the memory device 100 may include a memory cell 110, a write/read unit 120, and a control unit 130.

The memory cell 110 may include a selection layer whose resistance changes by pulses and a phase change material layer.

The write/read unit 120 can program the memory cell 110 and read the programmed memory cell 110. The write/read unit 120 may program the memory cell 110 to one of a plurality of resistance states and read the programmed memory cell 110. The write/read unit 120 performs a programming operation (write operation) to program the memory cell 110 to a target resistance state using a write pulse, and reads the programmed memory cell 110 using a read pulse. can perform a read operation.

The controller 130 may control write pulses and read pulses to be applied to the memory cells 110 during programming operations. The control unit 130 may control the resistance of the switching material and the phase change material by controlling the polarity, peak value, and shape of the writing pulse. The controller 130 may control the resistance of the phase change material by controlling the length of the fall time of the writing pulse. The memory cell 110 may be switched to the target resistance state by the write pulse.

Although the write/read unit 120 and the control unit 130 are shown as separate blocks in FIG. 1, the write/read unit 120 and the control unit 130 are arranged on one circuit board together with the memory cell 110. It may be an electronic circuit. For example, the write/read unit 120 is an electronic circuit ( For example, it may be a write/read circuit). In addition, the control unit 130 provides a control signal to the write/read unit 120 through a control bus to control the polarity, peak value, and shape of the write pulse applied to the memory cell 110 by the write/read unit 120. It may be a controlling electronic circuit (eg, a control circuit).

2 is an example equivalent circuit of a memory device.

Referring to FIG. 2, the memory device 100 includes a plurality of first electrode lines (WL) arranged in parallel and a plurality of second electrode lines (BL) arranged in parallel to intersect the first electrode line (WL). More may be included. A plurality of memory cells 110 may be disposed at the intersection of a plurality of first electrode lines WL and a plurality of second electrode lines BL. Each of the memory cells 110 may be connected to one of the first electrode lines WL and one of the second electrode lines BL. The write/read unit 120 may include a word line driver 121 connected to a plurality of first electrode lines (WL) and a bit line driver 122 connected to a plurality of second electrode lines (BL). The control unit 130 is connected to the word line driver 121 and the bit line driver 122 and can control the operations of the word line driver 121 and the bit line driver 122.

Figure 3 is a cross-sectional view of a memory cell according to one embodiment.

Referring to FIG. 3 , the memory cell 110 may include a selection layer 112 and a phase change material layer 114 electrically connected between the first electrode layer 111 and the second electrode layer 113. For example, the selection layer 112 may be electrically connected to the first electrode layer 111, and the phase change material layer 114 may be electrically connected to the second electrode layer 113. The selection layer 112 and the phase change material layer 114 may be electrically connected to each other in series.

According to one embodiment, the first electrode layer 111 and the second electrode layer 113 may be a path through which electric current flows. When a voltage greater than the threshold voltage is applied between the first electrode layer 111 and the second electrode layer 113, the selection layer 112 enters a low resistance state and current begins to flow, and the first electrode layer 111 and the second electrode layer 113 When a voltage smaller than the threshold voltage is applied between the two electrode layers 113, the selection layer 112 returns to a high resistance state and almost no current flows. Accordingly, the memory cell 110 may be turned on/off depending on the voltage applied between the first electrode layer 111 and the second electrode layer 113.

The first electrode layer 111 and the second electrode layer 113 may be formed of a conductive material. For example, the conductive material may be made of metal, conductive metal oxide, conductive metal nitride, or a combination thereof. For example, the conductive materials are carbon (C), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium aluminum nitride (TiAlN), titanium carbon silicon nitride (TiCSiN), and tantalum ( It may include one or more selected from Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN), but is not limited thereto.

The selection layer 112 includes a first element containing germanium (Ge), a second element containing arsenic (As) or antimony (Sb), tellurium (Te), selenium (Se), and sulfur (S). A third element containing at least one of, and indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), and nitrogen (N) , may include a switching material made of a chalcogenide material containing a fourth element including at least one of silicon (Si), calcium (Ca), and phosphorus (P). The selection layer 112 may include a switching material that exhibits ovonic threshold switching (OTS) characteristics. The switching material may change resistance depending on the polarity of the applied write pulse. The resistance of the switching material may change depending on the peak value of the applied write pulse.

The selection layer 112 may be formed using vapor deposition, for example, physical chemical vapor deposition. The selection layer 112 may be formed through a PVD process. The selection layer 112 may be formed through a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. The selection layer 112 may be formed to a thin thickness by co-sputtering deposition. For example, the thickness of the selection layer 112 may be about 5 nm or more and about 50 nm or less.

The phase change material layer 114 includes a first element containing germanium (Ge), a second element containing arsenic (As) or antimony (Sb), tellurium (Te), selenium (Se), and sulfur ( A third element containing at least one of S), and indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen ( It may include a phase change material made of a chalcogenide material containing a fourth element including at least one of N), silicon (Si), calcium (Ca), and phosphorus (P). The phase change material may have resistance that changes depending on the form of the applied write pulse, for example, the peak value of the pulse and/or the length of the fall time of the pulse.

The memory cell 110 may be written to store one of a plurality of different logic states by a programming operation. Different logic states may be represented by different resistances of memory cells 110. For example, a '1' logic state may be represented by a first resistor and a '0' logic state may be represented by a second resistor. Additionally, the memory cell 110 may have three or more multi-level states, that is, three or more different resistances, controlled by programming operations. The resistance shown by the memory cell 110 may vary depending on the selection layer 112 and the phase change material layer 114 included in the memory cell 110.

Select layer 112 may be written to store one of a plurality of different logic states by programming operations. Different logic states may be represented by different resistances of the selection layer 112. The resistance exhibited by the selection layer 112 may be based on the state of the switching material included in the selection layer 112 and exhibiting ovonic threshold switching characteristics.

The state of the switching material may be based, at least in part, on the polarity of a write pulse applied to memory cell 110 during a programming operation. The polarity of the writing pulse may vary depending on the polarity of the current and/or voltage. The state of the switching material may be based, at least in part, on the peak value of the write pulse applied to the memory cell 110 during a programming operation. The peak value of the writing pulse may vary depending on the magnitude of the current and/or voltage.

Phase change material layer 114 may be written to store one of a plurality of different logic states by programming operations. Different logic states may be represented by different resistances of the phase change material layer 114. The resistance shown by the phase change material layer 114 may be based on the state of the phase change material (PCM) included in the phase change material layer 114.

The state of the phase change material may be based, at least in part, on the type of write pulse applied to memory cell 110 during a programming operation. The shape of the writing pulse may vary depending on the quenching speed of the target phase change material. The resistance value of the phase change material may be determined depending on the heat treatment speed of the phase change material. For example, the falling time of the writing pulse may be shortened so that the writing pulse may have a rectangular shape. In this case, the phase change material is heated to a temperature higher than the melting temperature for a certain period of time by supplying a reset writing pulse, and then rapidly cooled, converting to an amorphous state and having a high resistance value. . Additionally, the fall time of the writing pulse may become longer, and the shape of the writing pulse may become trapezoidal. In this case, the phase change material is heated at a temperature higher than the crystallization temperature and lower than the melting temperature for a certain period of time by supplying a SET writing pulse, and then gradually cools, converting to a crystalline state and maintaining a low resistance value. You can have it.

The state of the phase change material may be based, at least in part, on the length of fall time of the write pulse applied to the memory cell 110 during a programming operation. The length of the fall time of the pulse may vary depending on the amorphous volume or crystalline volume of the target phase change material. As the proportion of the amorphous amount of the phase change material increases, the pulse may have a short fall time length, and as the proportion of the crystalline amount of the phase change material increases, the pulse may have a long fall time length. Since the resistance value can be differentiated according to the amorphous or crystalline amount of the phase change material, a multi-level memory cell 110 can be constructed using this. The state of the phase change material may be independent of the polarity of the current and/or voltage of the writing pulse. Write pulses and read pulses may be applied to the memory cell 110 using the first electrode line WL and the second electrode line BL of FIG. 2 .

FIGS. 4A to 4C are graphs illustrating types of voltage pulses that can be applied to a switching material according to an embodiment.

Referring to FIGS. 4A and 4B, the pattern of resistance change of the switching material according to the polarity change of the write pulse will be described. V ₁ and V ₂ have the same size and opposite polarity (V ₁ + V ₂ = 0). Let the resistance of the switching material according to the write pulse in FIG. 4a be R1, and the resistance of the switching material according to the write pulse in FIG. 4b with the polarity of the write pulse in FIG. 4a reversed be R2, then R1 has a value smaller than R2. do. This is due to the polarity-dependent nature of the switching material. For example, when the write pulse has a positive polarity, the threshold voltage of the switching material is lowered, and when the write pulse has a negative polarity, the threshold voltage of the switching material is increased.

Referring to FIGS. 4B and 4C, the pattern of change in resistance of the switching material according to the change in the peak value of the write pulse will be described. V ₂ has an absolute value smaller than V ₃ . If the resistance of the switching material according to the writing pulse of FIG. 4B is R2, and the resistance of the switching material according to the writing pulse of FIG. 4C is R3, R2 has a value smaller than R3. Accordingly, the strength of the resistance of the switching material can be changed according to the peak value of the write pulse having negative polarity.

By changing the polarity and peak value of the voltage pulse applied to the switching material of the selection layer, the resistance of the switching material can be changed, thereby allowing it to have different resistances (R1 < R2 < R3). Through different resistances, switching materials can be distinguished into different logic states, and multi-level cells can be implemented through distinct logic states.

5A and 5B are graphs showing threshold voltages of memory cells according to one embodiment.

Referring to FIG. 5A, it can be seen how the threshold voltage of the switching material changes according to the change in polarity and peak value of the write pulse. Regarding the polarity of the writing pulse, a relatively low threshold voltage is formed after writing with a pulse of positive polarity, and a relatively high threshold voltage is formed after writing with a pulse of negative polarity. . Regarding the peak value of the write pulse, when writing with a pulse of positive polarity, the threshold voltage decreases as the peak value of the writing pulse increases, and when writing with a pulse of negative polarity, the peak value of the writing pulse increases. Accordingly, the threshold voltage increases.

Referring to Figure 5b, the threshold voltage change pattern according to the time interval between the write pulse and the read pulse (write to read time (tWTR)) can be seen. When the time interval between writing and reading changes from 100㎲ to 10ns, the threshold voltage is maintained within a certain range. It can be seen that the pulse is driven stably even when the time interval between writing and reading is as small as 10ns. Accordingly, the memory device 100 may have a relatively fast operating speed.

The threshold voltage of the switching material is changed by changing the polarity and peak value of the voltage pulse applied to the switching material of the selection layer, and through different threshold voltages, the switching material can be distinguished into different logic states and Multi-level cells can be implemented through distinct logical states.

FIGS. 6A to 6D are graphs exemplarily showing types of voltage pulses that can be applied to a phase change material according to an embodiment.

Referring to FIGS. 6A and 6B, the resistance change pattern of the phase change material according to the fall time length (ㅿt) of the write pulse will be described. The write pulse in FIG. 6A has a longer fall time length than the write pulse in FIG. 6B. The first fall time length (tt ₁ ) of FIG. 6A may be greater than 1000 ns. The second fall time length (tt ₂ ) of FIG. 6B may be greater than 100 ns and less than or equal to 1000 ns. As the write pulse has a shorter fall time length, the proportion of the amorphous amount of the phase change material may increase, and as the write pulse has a longer fall time length, the proportion of the crystalline amount of the phase change material may increase. That is, when the write pulse of FIG. 6A is applied, the proportion of the amount of crystals in the phase change material increases, and when the write pulse of FIG. 6b is applied, the proportion of the amount of crystals in the phase change material is lower than when the write pulse of FIG. 6a is applied. It can be lowered. Let the resistance of the phase change material according to the writing pulse of FIG. 6A be R1, and the resistance of the switching material according to the writing pulse of FIG. 6B be R2, and R1 will have a value smaller than R2.

Referring to FIGS. 6B and 6C, the resistance change pattern of the phase change material according to the change in the shape of the writing pulse will be described. As the writing pulse in FIG. 6B is slowly cooled, the falling time becomes longer and has a trapezoidal shape, while the writing pulse in FIG. 6C has a falling time as it is rapidly cooled, and it has a rectangular shape. Specifically, the standard for dividing the shape of the write pulse into a trapezoidal shape and a rectangular shape may be the length of the fall time (ㅿt). The third fall time length (tt ₃ ) of FIG. 6C may be 100 ns or less. As shown in Figure 6c, if the length of fall time (ㅿ _t3 ) is less than 100ns, the shape of the write pulse is considered to be rectangular. If the length of fall time (ㅿ _t2 ) is greater than 100ns as shown in Figure 6b, the shape of the write pulse is can be considered a trapezoidal shape. A writing pulse having a trapezoidal shape is called a set pulse, and a writing pulse having a rectangular shape is called a reset pulse. Let the resistance of the phase change material according to the writing pulse of FIG. 6B be R2, and the resistance of the phase change material according to the writing pulse of FIG. 6C be R3, then R2 will have a value smaller than R3.

Referring to FIGS. 6C and 6D, the resistance change pattern of the phase change material according to the peak value of the writing pulse will be described. The write pulse in FIG. 6D has a higher voltage than the write pulse in FIG. 6C. In other words, V5 in FIG. 6D has a larger value than V4 in FIG. 6C. The peak value of the writing pulse may be proportional to the degree of amorphization. That is, when the write pulse of FIG. 6D is applied, the proportion of amorphous matter in the phase change material may be higher than when the write pulse of FIG. 6C is applied. Let the resistance of the phase change material according to the writing pulse of FIG. 6C be R3, and the resistance of the switching material according to the writing pulse of FIG. 6D be R4, and R3 will have a value smaller than R4.

By changing the polarity and peak value of the voltage pulse applied to the phase change material of the phase change material layer, the resistance of the phase change material can be changed, thereby allowing it to have different resistances (R1 < R2 < R3 < R4). Phase change materials can be distinguished into different logic states through different resistances, and multi-level cells can be implemented through the distinct logic states.

In addition, by combining the voltage pulse that can be applied to the switching material shown in FIGS. 4A to 4C and the voltage pulse that can be applied to the phase change material shown in FIGS. 6A to 6D and applying it to the memory cell, multi-level It is possible to implement a memory cell having

FIGS. 7A to 7F are graphs exemplarily showing types of voltage pulses that can be applied to memory cells according to one embodiment.

Referring to FIGS. 7A to 7F , the resistance change pattern as a write pulse is applied to the switching material and the phase change material will be described.

Referring to FIG. 7A, a first write pulse, which is a rectangular reset pulse with negative polarity and a first peak value, may be applied to the memory cell. In this case, the memory cell may have a first logic state (state 1) in which both the switching material and the phase change material have the highest resistance.

Referring to FIG. 7B, a second write pulse, which is a rectangular reset pulse with negative polarity and a second peak value smaller than the first peak value, may be applied to the memory cell. In this case, both the switching material and the phase change material may have a second logic state (state 2) with high resistance.

Referring to FIG. 7C, a third write pulse, which is a rectangular reset pulse with positive polarity and a second peak value smaller than the first peak value, may be applied to the memory cell. In this case, the switching material may have a low resistance and the phase change material may have a third logic state (state 3) having a high resistance.

Referring to FIG. 7D, a fourth write pulse, which is a trapezoidal set pulse with negative polarity and a second peak value smaller than the first peak value, may be applied to the memory cell. In this case, the switching material may have a high resistance and the phase change material may have a fourth logic state (state 4) having a low resistance.

Referring to FIG. 7E, a fifth write pulse, which is a trapezoidal set pulse with positive polarity, a second peak value smaller than the first peak value, and a second fall time length (tt ₂ ), is applied to the memory cell. may be approved. In this case, both the switching material and the phase change material may have a low-resistance fifth logic state (state 5).

Referring to FIG. 7F, a trapezoidal shape with positive polarity, a second peak value smaller than the first peak value, and a first fall time length (ㅿt ₁ ) longer than the second fall time length (ㅿt ₂ ). A sixth write pulse, which is a set pulse, may be applied to the memory cell. In this case, the switching material may have a low resistance and the phase change material may have a sixth logic state (state 6) with the lowest resistance.

FIG. 7G is a graph showing the states of memory cells according to the voltage pulses of FIGS. 7A to 7F.

Referring to FIG. 7G, numbers 1 to 6 correspond to first to sixth logic states, respectively, and the first to sixth logic states correspond to FIGS. 7A to 7F, respectively. Each logic state is clearly distinguished and appears in the cumulative distribution function (CDF) according to resistance. By adjusting the polarity, peak value, shape, and fall time length of the write pulse and applying the write pulse to the switching material of the selection layer and the phase change material of the phase change material layer, multiple logic states with different resistances can be displayed. . For example, the control unit 130 controls the write/read unit 120 to apply one of the first to sixth write pulses shown in FIGS. 7A to 7F to the memory cell 110. You can. Then, the memory cell 110 may have one of the first to sixth logic states. Multi-level cells can be implemented through these logic states with different resistances.

8A to 8C are graphs illustrating types of voltage pulses that can be applied to memory cells according to another embodiment.

Referring to FIGS. 8A to 8C, the resistance change pattern as a write pulse is applied to the switching material and the phase change material will be described.

Referring to FIG. 8A, a seventh write pulse having a first polarity and a third fall time length (tt ₃ ) may be applied to the selection layer and the phase change material layer by the control unit. The third fall time length (ㅿt ₃ ) may be 100 ns or less. The first polarity may be positive polarity or negative polarity. In this case, it may have a logical state A (state A).

Referring to FIG. 8B, a second polarity opposite to the first polarity, a second fall time length (tt ₂ ) different from the third fall time length (tt ₃ ), and a first peak value are used. 8 Write pulses may be applied to the selection layer and the phase change material layer by the control unit. If the first polarity is positive, the second polarity may be negative, and if the first polarity is negative, the second polarity may be positive. The second fall time length (ㅿt ₂ ) may be greater than 100 ns and less than or equal to 1000 ns. In this case, it may have a logical state B (state B).

Referring to FIG. 8C, the eighth write pulse may have a second peak value different from the first peak value. The absolute value of the second peak value may be greater than the absolute value of the first peak value. In this case, it may have a logical state C (state C).

The control unit 130 may control the write/read unit 120 to apply one of the seventh to eighth write pulses shown in FIGS. 8A to 8C to the memory cell 110. Then, the memory cell 110 may have one of logic states A to C. Multi-level cells can be implemented through these logic states with different resistances.

9 is a perspective view of a memory device according to one embodiment.

Referring to FIG. 9 , the memory device 200 includes a plurality of memory cells (MC), and the memory cell (MC) may be the memory cell 110 of FIG. 3 . The memory device 200 may have a 3D cross point array structure. The memory device 200 may include a first electrode line (WL) and a second electrode line (BL) located at different levels. The memory device 200 may include a first electrode line WL extending in a first direction (X direction) and spaced apart in a second direction (Y direction) perpendicular to the first direction. Additionally, the memory device 200 includes second electrode lines BL that are spaced apart from the first electrode line WL in the third direction (Z direction) and extend parallel to each other in a second direction intersecting the first direction. It can be included.

The memory cell MC may be disposed between the first electrode line WL and the second electrode line BL, respectively. The memory cell MC may be electrically connected to the first electrode line WL and the second electrode line BL and may be disposed at the intersection of the first electrode line WL and the second electrode line BL. Memory cells (MC) may be arranged in a matrix form. The memory cell MC may include a selection layer 210 and a phase change material layer 220. For example, the selection layer 210 and the phase change material layer 220 may be connected and disposed in series along the third direction (Z direction), and the selection layer 210 may be connected to the first electrode line WL and It is electrically connected to one of the second electrode lines BL, and the phase change material layer 220 may be electrically connected to the other electrode line. Various voltage signals or current signals may be provided through the first electrode line (WL) and the second electrode line (BL), and data may be written or read from the selected memory cell (MC) accordingly, and the remaining unselected memory cells (MC) may be provided. Writing or reading may be prevented from being performed on the memory cell MC.

An array of memory cells (MC) may have a multi-deck structure. Memory cells MC may be stacked in a third direction (Z direction). For example, the arrangement of the memory cells MC may have a multi-deck structure in which the first electrode line WL and the second electrode line BL are alternately stacked along the third direction (Z direction). In this case, the memory cell MC may be located between the first and second electrode lines WL and BL that are alternately stacked.

The memory cells MC may be arranged in the same structure along the third direction (Z direction). For example, in the memory cell (MC) disposed between the first electrode line (WL) and the second electrode line (BL), the selection layer 210 is electrically connected to the first electrode line (WL), and the The change material layer 220 is electrically connected to the second electrode line BL, and the selection layer 210 and the phase change material layer 220 may be connected in series, but are not limited to this. For example, unlike what is shown in FIG. 8, the positions of the selection layer 210 and the phase change material layer 220 in the memory cell MC may be changed. For example, in the memory cell MC, the phase change material layer 220 may be electrically connected to the first electrode line WL and the selection layer SW may be electrically connected to the second electrode line BL.

The memory cell MC may have a pillar shape. For example, the memory cell MC may have a cylindrical shape, or may have various pillar shapes such as a square pillar, an elliptical pillar, or a polygonal pillar.

The memory cell MC may have a side surface perpendicular to the substrate. In other words, the memory cell MC may have a constant cross-sectional area perpendicular to the stacking direction (Z direction), but this is an example and may have a structure in which the upper part is wider than the lower part, or the lower part is wider than the upper part. . Additionally, the selection layer 210 and the phase change material layer 220 may each independently have the same or different upper and lower areas. These shapes may vary depending on how each component is formed.

The selection layer 210 may control the flow of current to the memory device 200 electrically connected to the selection layer 210, thereby selecting the memory device 200. Specifically, the selection layer 210 may include a material whose resistance can change depending on the magnitude of the voltage applied across both ends. For example, the selection layer 210 may have ovonic threshold switching characteristics.

The selection layer 210 has excellent thermal stability and may be less damaged or deteriorated during the manufacturing process of semiconductor devices. Specifically, the selection layer 210 may have a crystallization temperature of 350°C or higher and 600°C or lower. For example, the crystallization temperature may be 380°C or higher, 400°C or higher, 580°C or lower, or 550°C or lower. Additionally, the selection layer 210 may have a sublimation temperature of 250°C or higher and 400°C or lower. For example, the sublimation temperature may be 280°C or higher, 300°C or higher, 380°C or lower, or 350°C or lower.

The selection layer 210 and the phase change material layer 220 may serve to store information. Specifically, the resistance values of the selection layer 210 and the phase change material layer 220 may vary depending on the applied voltage pulse. The memory device 100 can store and erase digital information such as '0' or '1' according to changes in resistance of the selection layer 210 and the phase change material layer 220.

A method of driving the memory device 200 is briefly described as follows. The memory device 200 allows current to flow by applying a voltage to the selection layer 210 and the phase change material layer 220 of the memory cell (MC) through the first electrode line (WL) and the second electrode line (BL). You can. The selection layer 210 and the phase change material layer 220 may be changed into one of a plurality of resistance states by an applied pulse. The selection layer 210 may include a switching material whose polarity changes depending on the applied pulse. The switching material can change between positive and negative polarity depending on the polarity of the pulse, and data can be stored in the memory device 200 through this change in polarity. The phase change material layer 220 may include a phase change material whose crystal state changes depending on the applied pulse. The phase of the phase change material can be reversibly changed by Joule's heat generated by the voltage applied to both ends of the memory element, and data is stored in the memory device 200 through this phase change. It can be saved. The phase change material layer 220 may have a multi-layer structure in which two or more layers with different physical properties are stacked, or a super-lattice structure in which a plurality of layers containing different materials are stacked alternately. ) may have a structure. Each element that makes up a phase change material can have a variety of chemical composition ratios (stoichiometry), and depending on the chemical composition ratio of each element, the crystallization temperature, melting point, phase change rate according to crystallization energy, and information retention of the phase change material are determined. It can be adjusted. For example, the chemical composition ratio can be adjusted so that the melting point of the phase change material is 500°C to about 800°C.

Additionally, any memory cell (MC) can be addressed by selecting the first electrode line (WL) and the second electrode line (BL), and between the selected first electrode line (WL) and the second electrode line (BL) By applying a predetermined pulse to the memory cell (MC), the memory cell (MC) can be programmed. Additionally, by measuring the current value through the second electrode line BL, information according to the resistance value of the corresponding memory cell MC, that is, programmed information, can be read.

When the material of the memory cell included in the memory device 200 includes a phase change material that reversibly changes between an amorphous state and a crystalline state, the memory device 200 may be a PRAM. The phase of such PRAM can be reversibly changed by Joule heat generated by the voltage applied to both ends of the memory device, and data can be stored in the memory device through this phase change. . For example, a phase change material may be in a high-resistance state in the amorphous phase and in a low-resistance state in the crystalline phase. By defining the high-resistance state as '0' and the low-resistance state as '1', data can be stored in the memory device.

In addition to PRAM, the memory device 200 may be RRAM, MRAM, or memristor.

From this, according to implementation examples based on the technical idea of the present disclosure, it is possible to provide a memory device that has a high read window margin and can implement multi-level by enabling segmentation of the state. You can confirm that it exists.

The memory devices described so far can be implemented in chip form and used as a neuromorphic computing platform. For example, Figure 10 is a block diagram schematically showing a neuromorphic device including a memory device. Referring to FIG. 10, the neuromorphic device 1000 may include a processing circuit 1010 and/or a memory 1020. The memory 1020 of the neuromorphic device 1000 may include the memory device 100 according to an embodiment.

The processing circuit 1010 may be configured to control functions for driving the neuromorphic device 1000. For example, the processing circuit 1010 may control the neuromorphic device 1000 by executing a program stored in the memory 1020 of the neuromorphic device 1000. The processing circuit 1010 may include hardware such as a logic circuit, a combination of hardware and software such as a processor executing software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) within the neuromorphic device 1000, and an arithmetic logic unit (ALU). , arithmetic logic unit), digital processor, microcomputer, FPGA (field programmable gate array), SoC (System-on-Chip), programmable logic unit, microprocessor, application specific semiconductor (ASIC) application-specific integrated circuit), etc. Additionally, the processing circuit 1010 can read and write various data from the external device 1030 and execute the neuromorphic device 1000 using the data. The external device 1030 may include a sensor array including an external memory and/or an image sensor (eg, a CMOS image sensor circuit).

The neuromorphic device 1000 shown in FIG. 10 can be applied to a machine learning system. The machine learning system may optionally use, for example, a convolutional neural network (CNN), a deconvolutional neural network, a long short-term memory (LSTM), and/or a gated recurrent unit (GRU). including recurrent neural networks (RNNs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and/or restricted neural networks (RBMs). A variety of artificial neural network organization and processing models, including Boltzmann machines, can be utilized.

These machine learning systems include, for example, linear regression and/or logistic regression, statistical clustering, Bayesian classification, decision trees, principal components, etc. It may include dimensionality reduction, such as principal component analysis, and other types of machine learning models, such as expert systems, and/or combinations of these, including ensemble techniques such as random forests. there is. These machine learning models include, for example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS), voice assistant services, and automatic voice recognition ( It can be used to provide various services such as ASR (automatic speech recognition) service, and can be installed and executed in other electronic devices.

A memory device including a switching material and a phase change material has been described with reference to the embodiment shown in the drawings, but this is merely an example, and various modifications and other equivalent embodiments can be made by those skilled in the art. You will understand that it is possible. Therefore, the disclosed embodiments should be considered from an illustrative rather than a restrictive perspective. The scope of rights is indicated in the patent claims, not the foregoing description, and all differences within the equivalent scope should be interpreted as being included in the scope of rights.

100, 200.....memory device 110.....memory cell
120....Writing/reading unit 130.....Control unit
111.....First electrode layer 112, 210.....Selective layer
113.....Second electrode layer 114, 220....Phase change material layer

Claims (23)

A memory cell including a selection layer and a phase change material layer connected in series with each other; and
Includes a control unit;
The selective layer includes a switching material,
The phase change material layer includes a phase change material,
The control unit applies a write pulse to the selection layer and the phase change material layer, and controls the polarity, peak value, and shape of the write pulse. According to claim 1,
The memory device wherein the controller controls the resistance of the phase change material by controlling the length of the fall time of the write pulse. According to claim 1,
The control unit applies a first write pulse to the memory cell,
The first write pulse has a negative polarity and is a rectangular reset pulse with a first peak value. According to clause 3,
The memory cells are:
A memory device having a first logic state in which both the switching material and the phase change material have the highest resistance when the first write pulse is applied. According to clause 3,
The control unit applies a second write pulse to the memory cell,
The second write pulse has a negative polarity and is a rectangular reset pulse having a second peak value smaller than the first peak value. According to clause 5,
The memory cells are:
A memory device having a second logic state in which both the switching material and the phase change material have high resistance when the second write pulse is applied. According to clause 5,
The control unit applies a third write pulse to the memory cell,
The third write pulse has a positive polarity and is a rectangular reset pulse having a second peak value smaller than the first peak value. According to clause 7,
The memory cells are:
A memory device having a third logic state in which the switching material has a low resistance and the phase change material has the highest resistance when the third write pulse is applied. According to clause 7,
The control unit applies a fourth write pulse to the memory cell,
The fourth write pulse has a negative polarity and is a trapezoidal set pulse with a second peak value smaller than the first peak value. According to clause 9,
The memory cells are:
A memory device having a fourth logic state in which the switching material has high resistance and the phase change material has low resistance when the fourth write pulse is applied. According to clause 9,
The control unit applies a fifth write pulse to the memory cell,
The fifth write pulse has positive polarity, has a second peak value smaller than the first peak value, and is a trapezoidal set pulse with a second fall time length. According to claim 11,
The memory cells are:
A memory device having a fifth logic state in which both the switching material and the phase change material have low resistance when the fifth write pulse is applied. According to claim 11,
The control unit applies a sixth write pulse to the memory cell,
The sixth write pulse has a positive polarity, a second peak value smaller than the first peak value, and a trapezoidal set pulse having a first fall time length longer than the second fall time length. According to claim 13,
The memory cells are:
A memory device having a sixth logic state in which the switching material has low resistance and the phase change material has the lowest resistance when the sixth write pulse is applied. According to claim 1,
The selective layer includes a first element containing germanium (Ge),
A second element containing arsenic (As) or antimony (Sb),
A third element containing at least one of tellurium (Te), selenium (Se), and sulfur (S), and
Indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen (N), silicon (Si), calcium (Ca), and a switching material made of a chalcogenide material containing a fourth element including at least one of phosphorus (P). According to claim 1,
The memory device wherein the selection layer includes a switching material that exhibits ovonic threshold switching material characteristics. According to claim 1,
A memory device in which the switching material changes resistance depending on the polarity of an applied write pulse. According to claim 1,
A memory device in which the switching material changes resistance depending on the peak value of an applied write pulse. According to claim 1,
The phase change material layer includes a first element containing germanium (Ge),
A second element containing arsenic (As) or antimony (Sb),
A third element containing at least one of tellurium (Te), selenium (Se), and sulfur (S), and
Indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen (N), silicon (Si), calcium (Ca), A memory device comprising a phase change material made of a chalcogenide material containing a fourth element including at least one of phosphorus (P). According to claim 1,
A memory device in which the phase change material changes resistance depending on the type of applied write pulse. According to claim 20,
The phase change material is a memory device whose resistance changes depending on the length of the fall time of the applied write pulse. a selective layer containing switching material;
a phase change material layer connected in series with the selection layer; and
A seventh write pulse having a first polarity and a third fall time length in the selection layer and the phase change material layer, and a second write pulse having a second polarity opposite to the first polarity and different from the third fall time length. A memory device comprising a control unit capable of applying an eighth write pulse having a fall time length of 2. According to clause 22,
The seventh write pulse has a first peak value, and the eighth write pulse has a second peak value different from the first peak value.

Images