KR960043540A - Cyclic multistage quasi-parallel analog / digital converter - Google Patents

Cyclic multistage quasi-parallel analog / digital converter Download PDF

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Publication number
KR960043540A
KR960043540A KR1019950011580A KR19950011580A KR960043540A KR 960043540 A KR960043540 A KR 960043540A KR 1019950011580 A KR1019950011580 A KR 1019950011580A KR 19950011580 A KR19950011580 A KR 19950011580A KR 960043540 A KR960043540 A KR 960043540A
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South Korea
Prior art keywords
digital
converter
analog
output
flash
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KR1019950011580A
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Korean (ko)
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KR0163893B1 (en
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조율호
이영범
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김광호
삼성전자 주식회사
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Publication of KR960043540A publication Critical patent/KR960043540A/en
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Publication of KR0163893B1 publication Critical patent/KR0163893B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

이 발명은 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기(Recycling Multistep Analog-to-Digital Converter)에 관한 것으로서, 선택된 샘플 앤드 홀드 회로와, 멀티플라잉 디지탈/아날로그 변환기와, 플래쉬 변환기와, 래치와, 이진 부호화 논리 회로와, 오차 보정 논리 회로로 구성되어, 고해상도를 제공하면서도 회로의 사이즈(Size)가 적고, 오차도 줄일 수 있은 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기에 관한 것이다.TECHNICAL FIELD The present invention relates to a cyclic structured multistage similar parallel analog-to-digital converter, comprising selected sample and hold circuits, multiplying digital / analog converters, flash converters, latches, and binary coding. The present invention relates to a cyclic multistage pseudo-parallel analog-to-digital converter composed of a logic circuit and an error correction logic circuit, which provides a high resolution while reducing the size of the circuit and reducing the error.

Description

순환구조형 다단 유사 병렬 아날로그/디지탈 변환기Cyclic multistage quasi-parallel analog / digital converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 이 발명의 실시예에 따른 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기의 구성을 나타내는 블럭도이다. 제4도는 이 발명의 실시예에 따른 순환구조형 3단 유사 병렬 아날로그/디지탈 변환기의 구성을 나타내는 블럭도이다.3 is a block diagram showing the configuration of a cyclic multistage pseudo-parallel analog-to-digital converter according to an embodiment of the present invention. 4 is a block diagram showing the configuration of a circular structured three-stage quasi-parallel analog-to-digital converter according to an embodiment of the present invention.

Claims (3)

외부의 아날로그 입력과 피드백 입력중에서, 선택적으로 입력신호를 샘플링하여, 일정 시간동안 유지했다가 출력하는 선택적 샘플 앤드 홀드 회로와, 상기한 선택적 샘플 앤드 홀드 회로의 출력을 입력으로 받고, 디지탈/아날로그 변환기 기능과 감산기능, 증폭기능을 동시에 수행하여 다시 상기한 선택적 샘플 앤드 홀드 회로로 출력하는 멀티플라잉 디지탈/아날로그 변환기와, 원하는 해상도에 비례하는 수의 비교기를 갖고, 상기한 선택적 샘플 앤드 홀드 회로의 출력을 입력으로 받아서 디지탈 신호로 변환하는 플래쉬 변환기와, 상기한 플래쉬 변환기에 포함되어 있으면 상기한 멀티플라잉 디지탈/아날로그 변환기에서 사용할 수 있도록 신호를 일정시간 동안 유지하다가 상기한 멀티플라잉 디지탈/아날로그 변환기에 출력하는 래치와, 상기한 래치에서 출력된 상기 플래쉬 변환기의 써모메터 코드 디지탈 출력을 이진 부호로 바꾸어 출력하는 이진 부호화 논리 회로와, 상기한 이진 부호화 논리 회로의 출력을 입력으로 받고, 상기 플래쉬 변환기에서 생길 수 있는 오차를 보정하여 출력하는 오차 보정 논리 회로로 이루어지는 것을 특징으로 하는 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기.Among the external analog input and feedback input, an optional sample and hold circuit for selectively sampling and maintaining the output signal for a predetermined time, and the output of the above described sample and hold circuit as inputs, and receive a digital / analog converter. The output of the selective sample and hold circuit includes a multiplying digital / analog converter which simultaneously performs a function, a subtraction function, and an amplifier function, and outputs it to the selective sample and hold circuit again, and a number of comparators proportional to a desired resolution. A flash converter for receiving a signal as an input and converting it into a digital signal, and if the flash converter is included in the flash converter, the signal is held for a predetermined time for use by the multiplying digital / analog converter and then output to the multiplying digital / analog converter. Latch to perform the above-mentioned latch A binary coded logic circuit for converting the digital coded digital output of the flash converter outputted by the binary code into a binary code, and receiving the output of the binary coded logic circuit as an input and correcting an error that may occur in the flash converter. A cyclic structured multistage quasi-parallel analog / digital converter comprising an error correction logic circuit. 제1항에 있어서, 상기한 멀티플라잉 디지탈/아날로그 변환기는 상기한 샘플 앤드 홀드 회로의 아날로그 출력과 상기한 플래쉬 변환기 내부에 포함된 래치의 디지탈 출력에 해당하는 아날로그 값과의 차이를 일정한 이득만큼 증폭시키는 것을 특징으로 하는 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기.The method of claim 1, wherein the multiplying digital to analog converter amplifies the difference between the analog output of the sample and hold circuit and the analog value corresponding to the digital output of the latch included in the flash converter by a constant gain. Circular multi-stage similar parallel analog / digital converter, characterized in that. 제1항에 있어서, 상기한 이진 부호화 논리 회로에서는 플래쉬 변환기의 써모메터 코드 출력을 이진 부호로 바꾸고 래치시키거나 시간 지연을 주어서, 다음번 순환기에서 하위비트를 생성할때까지 유지하는 것을 특징으로 하는 순환구조형 다단 유사 병렬 아날로그/디지탈 변환기.2. The circuit of claim 1, wherein in the binary encoding logic circuit, the thermo code output of the flash converter is converted into a binary code, latched, or given a time delay, and maintained until the next bit is generated in the next cycle. Structured multi-stage quasi-parallel analog / digital converter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011580A 1995-05-11 1995-05-11 Parallel a/d converter KR0163893B1 (en)

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KR1019950011580A KR0163893B1 (en) 1995-05-11 1995-05-11 Parallel a/d converter

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Application Number Priority Date Filing Date Title
KR1019950011580A KR0163893B1 (en) 1995-05-11 1995-05-11 Parallel a/d converter

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KR960043540A true KR960043540A (en) 1996-12-23
KR0163893B1 KR0163893B1 (en) 1999-03-20

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012239A (en) * 1997-07-28 1999-02-25 윤종용 Analog / Digital Inverter
KR19990018936A (en) * 1997-08-28 1999-03-15 윤종용 Analog-to-digital conversion circuit
CN112687218A (en) * 2019-10-17 2021-04-20 联詠科技股份有限公司 Display driver, device applied to display driver and display panel driving method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101017047B1 (en) * 2004-02-25 2011-02-23 매그나칩 반도체 유한회사 Analog to digital converter
KR101476539B1 (en) * 2013-07-03 2014-12-24 고려대학교 산학협력단 Multiplying digital-to-analog converter and operating method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012239A (en) * 1997-07-28 1999-02-25 윤종용 Analog / Digital Inverter
KR19990018936A (en) * 1997-08-28 1999-03-15 윤종용 Analog-to-digital conversion circuit
CN112687218A (en) * 2019-10-17 2021-04-20 联詠科技股份有限公司 Display driver, device applied to display driver and display panel driving method

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