KR960008950B1 - Pll circuit - Google Patents

Pll circuit Download PDF

Info

Publication number
KR960008950B1
KR960008950B1 KR88015008A KR880015008A KR960008950B1 KR 960008950 B1 KR960008950 B1 KR 960008950B1 KR 88015008 A KR88015008 A KR 88015008A KR 880015008 A KR880015008 A KR 880015008A KR 960008950 B1 KR960008950 B1 KR 960008950B1
Authority
KR
South Korea
Prior art keywords
pll circuit
pll
circuit
Prior art date
Application number
KR88015008A
Other languages
Korean (ko)
Other versions
KR890009107A (en
Inventor
Masashi Arai
Ryuizi Ogawa
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62288822A external-priority patent/JPH01129613A/en
Priority claimed from JP62292430A external-priority patent/JPH0748657B2/en
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of KR890009107A publication Critical patent/KR890009107A/en
Application granted granted Critical
Publication of KR960008950B1 publication Critical patent/KR960008950B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR88015008A 1987-11-16 1988-11-15 Pll circuit KR960008950B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62-288822 1987-11-16
JP62288822A JPH01129613A (en) 1987-11-16 1987-11-16 Pll circuit
JP62-292430 1987-11-19
JP62292430A JPH0748657B2 (en) 1987-11-19 1987-11-19 PLL circuit

Publications (2)

Publication Number Publication Date
KR890009107A KR890009107A (en) 1989-07-15
KR960008950B1 true KR960008950B1 (en) 1996-07-10

Family

ID=26557347

Family Applications (1)

Application Number Title Priority Date Filing Date
KR88015008A KR960008950B1 (en) 1987-11-16 1988-11-15 Pll circuit

Country Status (4)

Country Link
US (1) US4870684A (en)
EP (1) EP0316878B1 (en)
KR (1) KR960008950B1 (en)
DE (1) DE3882489T2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097219A (en) * 1988-12-15 1992-03-17 Mitsubishi Denki Kabushiki Kaisha Pll for controlling frequency deviation of a variable frequency oscillator
US4970474A (en) * 1989-08-14 1990-11-13 Delco Electronics Corporation Analog/digital phase locked loop
US4972446A (en) * 1989-08-14 1990-11-20 Delco Electronics Corporation Voltage controlled oscillator using dual modulus divider
DE4006654A1 (en) * 1990-03-03 1991-09-05 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR DETECTING CHARACTERISTICS
FR2680058B1 (en) * 1991-07-30 1994-01-28 Sgs Thomson Microelectronics Sa METHOD AND DEVICE FOR SYNCHRONIZING A SIGNAL.
US5257301A (en) * 1992-03-30 1993-10-26 Trw Inc. Direct digital frequency multiplier
US5430537A (en) * 1993-09-03 1995-07-04 Dynamics Research Corporation Light beam distance encoder
JP3467888B2 (en) * 1995-02-08 2003-11-17 三菱電機株式会社 Receiving device and transmitting / receiving device
US5815694A (en) * 1995-12-21 1998-09-29 International Business Machines Corporation Apparatus and method to change a processor clock frequency
JPH11203421A (en) * 1998-01-19 1999-07-30 Oki Electric Ind Co Ltd Semiconductor disk device
JP3966989B2 (en) * 1998-04-20 2007-08-29 株式会社東芝 Disc playback apparatus and disc playback method
US8456206B2 (en) * 2011-06-20 2013-06-04 Skyworks Solutions, Inc. Phase-locked loop lock detect
JP6813074B1 (en) * 2019-10-30 2021-01-13 株式会社明電舎 Power conversion system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2413604A1 (en) * 1974-03-21 1975-09-25 Blaupunkt Werke Gmbh PHASE-LOCKED REGULAR LOOP
JPS5228208A (en) * 1975-08-28 1977-03-03 Nippon Gakki Seizo Kk Fm multiplex stereo demodulator circuit
DE2616398C2 (en) * 1976-04-14 1978-06-01 Siemens Ag, 1000 Berlin Und 8000 Muenchen Circuit arrangement for regulating the pulse repetition frequency of a signal
DE3463883D1 (en) * 1983-05-27 1987-06-25 Philips Patentverwaltung Television receiver comprising a processing unit for stereophonic/twin sound signal generation
FR2600848B1 (en) * 1984-09-10 1992-06-05 Labo Cent Telecommunicat DEVICE FOR CONTROLLING AN OSCILLATOR TO A MICRO FREQUENCY SOURCE WITH VERY LOW PHASE NOISE AND FREQUENCY AGILE
US4691175A (en) * 1985-11-14 1987-09-01 Motorola, Inc. Adaptive phase locked loop having a variable locking rate
US4739284A (en) * 1987-05-04 1988-04-19 Motorola, Inc. Phase locked loop having fast frequency lock steering circuit
US4817150A (en) * 1987-08-31 1989-03-28 Rca Licensing Corporation Oscillator frequency control arrangement for a stereo decoder

Also Published As

Publication number Publication date
EP0316878A2 (en) 1989-05-24
KR890009107A (en) 1989-07-15
DE3882489T2 (en) 1994-02-17
EP0316878A3 (en) 1989-08-30
EP0316878B1 (en) 1993-07-21
US4870684A (en) 1989-09-26
DE3882489D1 (en) 1993-08-26

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080623

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee