KR950009411Y1 - A circuit for shared memory of multiprocessor system using time division processing - Google Patents

Abstract

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Description

Memory sharing circuit of multiple processors by time division

1 is a block diagram of a conventional hardware memory.

2 is a block diagram of a memory sharing circuit of a multiple processor by time division according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 1 ', 10: clock generator 2, 2', 20: address controller

3, 3 ', 30: address latch section 4, 4': memory control section

5, 5 ', 50: Memory 6: CPU1

6 ': CPU2 7, 70: buffer

40: PAL logic 60: MCPU

60 ': SCPU 80: interrupt

AB: Address Bus PB: Parallel Bus

DB: Data Bus

The present invention relates to multiple processing, and more particularly, to a memory sharing circuit of a multiprocessor by time division for sequentially executing several programs by time division method.

Multiprocessing is a form in which two or more CPUs constitute a system, and two or more hardware processors are used to communicate with each processor by sharing memory or directly sending a message from one processor to another.

In the present invention, the multiple processors are designed to execute several programs at the same time in a time-division manner so as to be suitable for the exchange hardware memory. Each processor executes only one program at a time and executes input / output operations for multiple programs in parallel. By doing so, external and internal data processing is possible.

1 is a block diagram of a conventional hardware memory, as shown by dotted lines A,... Based on A ', one module is configured in a symmetrical state.

The operation of the conventional hardware memory circuit will be described below with reference to FIG.

The clock generation unit 1, 1 'generates a clock by a counter, generates an address clock for accessing the memory, and supplies it to the address latch units 3, 3' and the address control unit 2, 2 '. The address controller 2, 2 'controls the address stored by the clock supplied from the clock generators 1, 1', and the address latch units 3, 3 'control the clock generators 1, 1'. Latches the clock from and the address from the CPU 6, 6 ', and the memory controller 4, 4' controls the counter clock to access the processor's memory and the address from the CPU 6, 6 '. Generates a signal, and stores data using a RAM in the memory 5 and 5 'according to a counter clock signal supplied from the memory control units 4 and 4', and the PB (ferrule) in the buffer unit 7. It functions to temporarily store external data input through the Ralbus) and data transmitted from the CPUs 6 and 6 'to the external module.

In the above-described conventional hardware memory, since the CPU is not time-divided in configuring the memory accessed by the CPU, it takes a lot of time to process user programs or data in the CPU, and there is confusion in execution. There are too many problems that cannot be designed by integrating hardware.

The present invention has been made to solve the above-mentioned problems. By appropriately distributing the operations of the direct access devices and peripheral devices of the memory according to time, the execution of these programs is alternately performed when several user programs exist in the memory at the same time. The purpose of the present invention is to provide an integrated hardware memory circuit by simplifying the design of circuit components compared to conventional hardware memories.

In order to achieve the above object, the present invention provides an MCPU (main CPU) for time-divisionally controlling the entire system, an SCPU (sub-CPU) for controlling data transmission with an external subscriber, and a clock having a different period by time division. A clock generation section for generating a signal, an address control section for controlling an address for accessing a memory at the counter address by the time division clock, an address latch section and an external module for latching an address output from the counter clock and the CPU bus; Memory for storing data accessed from the subscriber, a buffer for temporarily storing external data input to the system, and PAL logic for controlling the data transferred from the external module to the MCPU and SCPU by controlling the memory and the buffer. The clock generator when data is accessed from the external module From provides a shared memory of a multiprocessor circuit by time division, characterized in that comprising a interrupt to walk an interrupt to MCPU and SCPU.

2 is a configuration diagram of a memory sharing circuit of a multiprocessor by time division according to the present invention, and stores a data accessed from an external module and an external subscriber, and a memory sharing circuit for transmitting data controlled by a processor's CPU to an external module. to be.

Hereinafter, the operation of the present invention will be described in detail with reference to FIG. 2.

In order to alternate the performance of the programs stored in the main memory, switching between the programs is required and the clock controls this switching.

In FIG. 2, the clock generator 10 generates a clock of several periods that are time-divided to allocate an address 20 of the memory in time, and the address controller 20 time-divides the address period of the memory again to counter clock. And the MCPU address supplied from the MCPU 60 to the address latch unit 30 and the SCPU address supplied from the SCPU 60 to the address latch unit 30. The address latch unit 30 is supplied from the counter clock controlled by the address control unit 20 and the MCPU address supplied from the MCPU 60 and the SCPU 60 'to latch a signal for accessing the memory 50. Latch the SCPU address. The MCPU 60 not only controls the address by time division when the CPU accesses the memory but also assigns a flag register to an arbitrary address of the CPU memory in order to prevent memory access by another CPU. If there is data accessing the memory from an external module, the clock interrupts the MCPU 60 and SCPU 60 'of the processor to time-division and process the data input from the external module.

Since the addresses of the MCPU 60 and the SCPU 60 'are time-divisions of the addresses accessed to the memory 50 again, if a case in which data cannot be read and written from the memory 50 occurs, the device waits in the time-division command mode ( transition to the wait) state so that the above data can be read and written in the next time slot.

The buffer 70 temporarily stores data accessed from an external module to exchange data with the MCPU 60, SCPU 60 ', and memory 50 of the processor, and the PAL logic (Programmable Array Logic: 40). The buffer 70 and the memory 50 are controlled to allow the MCPU 60 and the SCPU 60 'to access the memory.

As described above, in the memory sharing circuit of the multiprocessor of the present invention, the addresses for accessing the memory are distributed in time to store the data in the memory, and the data accessing the memory from the external module is also internally clocked to the MCPU and SCPU by the clock. By interrupting and processing the external data by time-interrupting, the program stored in the memory circuit of the processor can be executed sequentially and the hardware design can be integrated by simply constructing the circuit as compared with the conventional hardware memory circuit.

Claims (1)

In a memory-sharing circuit of a multiprocessor by time division, an MCPU 60 for time-division controlling an address to be accessed by allocating a flag register to an arbitrary address when the memory is accessed, and data transfer with a subscriber SCPU (60 ') for controlling the time, the clock generation unit 10 for generating a clock having a different period of time-division is applied to the address control unit 20 and the interrupter 80, and the clock generator 10 An address control unit 20 for controlling an address for accessing a memory with a time-divisioned clock provided by the CPU, and a counter clock unit supplied from the address control unit 20 are provided from the CPU and the CPU 60. An address latch unit 30 for latching an address supplied to a bus, a memory 50 for storing data accessed from an external module and a subscriber, and external data input to a system PAL logic to control the data transmitted from the external module to the MCPU 60 and the SCPU 60 'by controlling the buffer 70 to buffer and store the buffer in a timely manner, and the memory 50 and the buffer 70. 40 and an interrupt unit 80 for interrupting the MCPU 60 and SCPU 60 'from the clock generator 10 when data is accessed from the external module to the processor. Memory-sharing circuit of multiple processors by time division.